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arch-arm: Add ARMv8.1 TTBR1_EL2 register

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This patch adds ARMv8.1 TTBR1_EL2 register into the decodeAArch64SysReg
table, but stil leaving it unimplemented (Accessing it through MSR/MRS
causes an exception)

Change-Id: I463b86cc544233aa1ee5b2fcba689d6b9f2a874b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10063
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2018-04-17 11:08:29 +01:00
parent c21a2a54ca
commit 1de574fcbd
3 changed files with 14 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/arch/arm/isa.cc
View File

@@ -1713,6 +1713,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
case MISCREG_TTBR0_EL1:
case MISCREG_TTBR1_EL1:
case MISCREG_TTBR0_EL2:
case MISCREG_TTBR1_EL2:
case MISCREG_TTBR0_EL3:
getITBPtr(tc)->invalidateMiscReg();
getDTBPtr(tc)->invalidateMiscReg();

4
src/arch/arm/miscregs.cc
View File

@@ -1689,6 +1689,8 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
switch (op2) {
case 0:
return MISCREG_TTBR0_EL2;
case 1:
return MISCREG_TTBR1_EL2;
case 2:
return MISCREG_TCR_EL2;
}
@@ -3519,6 +3521,8 @@ ISA::initializeMiscRegMetadata()
InitReg(MISCREG_TTBR0_EL2)
.hyp().mon()
.mapsTo(MISCREG_HTTBR);
InitReg(MISCREG_TTBR1_EL2)
.unimplemented();
InitReg(MISCREG_TCR_EL2)
.hyp().mon()
.mapsTo(MISCREG_HTCR);

16
src/arch/arm/miscregs.hh
View File

@@ -666,14 +666,16 @@ namespace ArmISA
MISCREG_CBAR_EL1, // 598
MISCREG_CONTEXTIDR_EL2, // 599
// Introduced in ARMv8.1
MISCREG_TTBR1_EL2, // 600
// These MISCREG_FREESLOT are available Misc Register
// slots for future registers to be implemented.
MISCREG_FREESLOT_1, // 600
MISCREG_FREESLOT_2, // 601
MISCREG_FREESLOT_3, // 602
MISCREG_FREESLOT_4, // 603
MISCREG_FREESLOT_5, // 604
MISCREG_FREESLOT_6, // 605
MISCREG_FREESLOT_1, // 601
MISCREG_FREESLOT_2, // 602
MISCREG_FREESLOT_3, // 603
MISCREG_FREESLOT_4, // 604
MISCREG_FREESLOT_5, // 605
// NUM_PHYS_MISCREGS specifies the number of actual physical
// registers, not considering the following pseudo-registers
@@ -1370,12 +1372,12 @@ namespace ArmISA
"cbar_el1",
"contextidr_el2",
"ttbr1_el2",
"freeslot1",
"freeslot2",
"freeslot3",
"freeslot4",
"freeslot5",
"freeslot6",
"num_phys_regs",