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arch-arm: Mask out unsupported trapped exception handling bits

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Floating-point trapped exception handlings are not currently
supported in gem5, therefore the corresponding bits are RAZ/WI in
FCPR.

Change-Id: Ica43af62d5f3bbc095e8dd872f0bd365231a5b5f
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10045
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Chuan Zhu
2017-12-29 20:04:14 +00:00
committed by Giacomo Travaglini
parent b299740e65
commit abbe32b6ac
1 changed files with 0 additions and 12 deletions
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12
src/arch/arm/isa.cc
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@@ -521,12 +521,6 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
{
const uint32_t ones = (uint32_t)(-1);
FPSCR fpscrMask = 0;
fpscrMask.ioe = ones;
fpscrMask.dze = ones;
fpscrMask.ofe = ones;
fpscrMask.ufe = ones;
fpscrMask.ixe = ones;
fpscrMask.ide = ones;
fpscrMask.len = ones;
fpscrMask.stride = ones;
fpscrMask.rMode = ones;
@@ -865,12 +859,6 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
{
const uint32_t ones = (uint32_t)(-1);
FPSCR fpscrMask = 0;
fpscrMask.ioe = ones;
fpscrMask.dze = ones;
fpscrMask.ofe = ones;
fpscrMask.ufe = ones;
fpscrMask.ixe = ones;
fpscrMask.ide = ones;
fpscrMask.len = ones;
fpscrMask.stride = ones;
fpscrMask.rMode = ones;