x86: Add a ld/st microop flag for marking an access uncacheable.
This percolates down to the memory request object which will have its "UNCACHEABLE" flag set. Change-Id: Ie73f4249bfcd57f45a473f220d0988856715a9ce Reviewed-on: https://gem5-review.googlesource.com/9881 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
This commit is contained in:
@@ -295,7 +295,7 @@ let {{
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class LdStOp(X86Microop):
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def __init__(self, data, segment, addr, disp,
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dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
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implicitStack):
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implicitStack, uncacheable):
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self.data = data
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[self.scale, self.index, self.base] = addr
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self.disp = disp
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@@ -311,6 +311,8 @@ let {{
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self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
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if nonSpec:
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self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
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if uncacheable:
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self.instFlags += " | (Request::UNCACHEABLE)"
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# For implicit stack operations, we should use *not* use the
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# alternative addressing mode for loads/stores if the prefix is set
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if not implicitStack:
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@@ -335,7 +337,7 @@ let {{
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class BigLdStOp(X86Microop):
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def __init__(self, data, segment, addr, disp,
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dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
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implicitStack):
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implicitStack, uncacheable):
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self.data = data
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[self.scale, self.index, self.base] = addr
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self.disp = disp
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@@ -351,6 +353,8 @@ let {{
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self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
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if nonSpec:
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self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
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if uncacheable:
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self.instFlags += " | (Request::UNCACHEABLE)"
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# For implicit stack operations, we should use *not* use the
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# alternative addressing mode for loads/stores if the prefix is set
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if not implicitStack:
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@@ -383,10 +387,10 @@ let {{
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class LdStSplitOp(LdStOp):
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def __init__(self, data, segment, addr, disp,
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dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
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implicitStack):
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implicitStack, uncacheable):
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super(LdStSplitOp, self).__init__(0, segment, addr, disp,
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dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
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implicitStack)
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implicitStack, uncacheable)
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(self.dataLow, self.dataHi) = data
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def getAllocator(self, microFlags):
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@@ -466,10 +470,10 @@ let {{
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dataSize="env.dataSize",
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addressSize=addressSize,
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atCPL0=False, prefetch=False, nonSpec=nonSpec,
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implicitStack=implicitStack):
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implicitStack=implicitStack, uncacheable=False):
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super(LoadOp, self).__init__(data, segment, addr,
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disp, dataSize, addressSize, mem_flags,
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atCPL0, prefetch, nonSpec, implicitStack)
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atCPL0, prefetch, nonSpec, implicitStack, uncacheable)
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self.className = Name
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self.mnemonic = name
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@@ -547,10 +551,10 @@ let {{
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dataSize="env.dataSize",
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addressSize="env.addressSize",
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atCPL0=False, prefetch=False, nonSpec=nonSpec,
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implicitStack=False):
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implicitStack=False, uncacheable=False):
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super(LoadOp, self).__init__(data, segment, addr,
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disp, dataSize, addressSize, mem_flags,
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atCPL0, prefetch, nonSpec, implicitStack)
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atCPL0, prefetch, nonSpec, implicitStack, uncacheable)
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self.className = Name
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self.mnemonic = name
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@@ -601,10 +605,11 @@ let {{
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def __init__(self, data, segment, addr, disp = 0,
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dataSize="env.dataSize",
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addressSize=addressSize,
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atCPL0=False, nonSpec=False, implicitStack=implicitStack):
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atCPL0=False, nonSpec=False, implicitStack=implicitStack,
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uncacheable=False):
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super(StoreOp, self).__init__(data, segment, addr, disp,
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dataSize, addressSize, mem_flags, atCPL0, False,
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nonSpec, implicitStack)
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nonSpec, implicitStack, uncacheable)
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self.className = Name
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self.mnemonic = name
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@@ -665,10 +670,11 @@ let {{
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def __init__(self, data, segment, addr, disp = 0,
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dataSize="env.dataSize",
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addressSize="env.addressSize",
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atCPL0=False, nonSpec=False, implicitStack=False):
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atCPL0=False, nonSpec=False, implicitStack=False,
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uncacheable=False):
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super(StoreOp, self).__init__(data, segment, addr, disp,
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dataSize, addressSize, mem_flags, atCPL0, False,
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nonSpec, implicitStack)
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nonSpec, implicitStack, uncacheable)
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self.className = Name
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self.mnemonic = name
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@@ -696,7 +702,8 @@ let {{
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def __init__(self, data, segment, addr, disp = 0,
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dataSize="env.dataSize", addressSize="env.addressSize"):
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super(LeaOp, self).__init__(data, segment, addr, disp,
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dataSize, addressSize, "0", False, False, False, False)
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dataSize, addressSize, "0",
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False, False, False, False, False)
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self.className = "Lea"
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self.mnemonic = "lea"
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@@ -717,7 +724,7 @@ let {{
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addressSize="env.addressSize"):
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super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
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addr, disp, dataSize, addressSize, "0", False, False,
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False, False)
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False, False, False)
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self.className = "Tia"
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self.mnemonic = "tia"
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@@ -729,7 +736,7 @@ let {{
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addressSize="env.addressSize", atCPL0=False):
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super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
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addr, disp, dataSize, addressSize, "Request::NO_ACCESS",
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atCPL0, False, False, False)
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atCPL0, False, False, False, False)
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self.className = "Cda"
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self.mnemonic = "cda"
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