Add a unit test for stats/info.
One test has been disabled due to not knowing the
expected behavior.
It is important to notice that Stats::Info can have
duplicate names using the new style. Stats::Group is
responsible for not allowing duplicate names in this
case.
Change-Id: I8b169d34c1309b37ba79fa9cf6895547b7e97fc0
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43009
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
When the Vega ISA got committed, it lacked the request counter
tracking for memory requests that existed in the GCN3 code.
Instead of copying over the same lines from the GCN3 code to the Vega
code, this commit makes the various memory pipelines handle updating the
request counter information instead, as every memory instruction calls a
memory pipeline.
This commit also adds an issueRequest in scalar_memory_pipeline, as
previously, the gpuDynInsts were explicitly placed in the queue of
issuedRequests.
Change-Id: I5140d3b2f12be582f2ae9ff7c433167aeec5b68e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45347
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
vector_register_file uses the exec_mask of a memory instruction in
order to determine if it should mark a register as in-use or not.
Previously, the exec_mask of memory instructions was only set on
execution of that instruction, which occurs after the code in
vector_register_file. This led to the code reading potentially garbage
data, leading to a scenario where a register would be marked used when
it shouldn't be.
This fix sets the exec_mask of memory instructions in schedule_stage,
which works because the only time the wavefront execMask() is updated is
on a instruction executing, and we know the previous instruction will
have executed by the time schedule_stage executes, due to the order the
pipeline is executed in.
This also undoes part of a patch from last year (62ec973) which treated
the symptom of accidental register allocation, without preventing the
registers from being allocated in the first place.
This patch also removes now redundant code that sets the exec_mask in
instructions.cc for memory instructions
Change-Id: Idabd35020000764fb06133ac2458606c1aaf6f04
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45346
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Certain memory writes were reading their registers in
initiateAcc, which lead to scenarios where a subsequent instruction
would execute, clobbering the value in that register before the memory
writes' initiateAcc method was called, causing the memory write to read
wrong data.
This patch moves all register reads to execute, preventing the above
scenario from happening.
Change-Id: Iee107c19e4b82c2e172bf2d6cc95b79983a43d83
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45345
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Alex Dutu <alexandru.dutu@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Instruction fetch should not commence if there already is an
instruction-count event in the queue.
The most conspicuous scenario where this leads to obvious breakage,
is guest debugging. Imagine the first bytes in the program pointed to
by _start are invalid instruction encoding, and we pass the --wait-gdb
flag. Then in GDB we set $pc to point to valid instructions, and we
"continue". gem5 will abort with "invalid instruction".
This is not how real targets behave: neither software- (e.g. ptrace)
based debuggers, nor low-level (e.g. OpenOCD or XMD connected over
JTAG to debug early initialization code eg when the MMU has not been
switched on yet, etc.) Fetching should start from where $pc was set
to. This patch tries to model this behavior.
Change-Id: Ibce6fdbbb082edf1073ae96745bc7867878f99ca
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27587
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Add a non-standard extension to the RSP protocol: the "." command
requests a dump of the simulated page table.
The dump consists of concatenated records, one record per page table
entry. Each record contains the entry's "virtual" value written as
hex, followed by a colon (:), followed by the entry's "physical" value
written as hex, followed by a semicolon (;).
At the time of writing, one practical use of this feature (in
combination with the "shared_backstore" parameter) is extremely fast
Miranda-Ingalls simulation of JIT compilers.
Change-Id: I333ed11d4ce671251d0b93cddae3bbcea44ea4ca
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47719
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The gem5art tests add the current repository as an artifact. Previously
this repository was called "gem5art". Since moving to the gem5 repo, it
is now called "gem5". Therefore the test checking the repository name
needed fixed.
Note: We need a better solution for testing gem5art's git functionality.
Using the current repository is not stable, as this fix shows. Noted
in Jira: https://gem5.atlassian.net/browse/GEM5-1013.
Change-Id: I017ff039ccb1c0a290f9aa1a09bd738c1820f88f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47220
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
In C, to refer to a type without a struct or enum tag on the type, you
need to typedef it like this:
typedef struct
{
} Foo;
Foo foo;
In C++, this is unnecessary:
struct Foo
{
};
Foo foo;
Remove all of the first form in C++ files and replace them with the
second form.
Change-Id: I37cc0d63b2777466dc6cc51eb5a3201de2e2cf43
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46199
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The adoption of the gem5 namespace [1] broke aarch64 builds with
the following error:
build/ARM/arch/arm/kvm/base_cpu.cc:198:22: error: aggregate
'gem5::kvm_reg_list regs_probe' has incomplete type and cannot be
defined
In file included from build/ARM/arch/arm/kvm/base_cpu.cc:38:0:
build/ARM/arch/arm/kvm/base_cpu.hh:115:28: note: forward declaration of
'struct gem5::kvm_reg_list'
std::unique_ptr<struct kvm_reg_list> tryGetRegList(uint64_t nelem)
const;
Forward declaring the struct defined in linux/kvm.hh (included in source
file) in the global namespace, rather than the gem5 one fixes the
problem
[1]: https://gem5-review.googlesource.com/c/public/gem5/+/46323
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I96c7d31aa4810edcf98e23cefeaf4895620b6444
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47619
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
When used with next_addr, findNearest will return the
next (even larger) address than the nearest larger
address. The problem is that when there is no valid
next, the function was dereferencing addrMap.end().
Fix this by marking next address as 0, since 0 is
not larger than any other address.
Places that use this function should be revisited
to make sure they account for this behavior, as
reported in the following Jira issue:
https://gem5.atlassian.net/browse/GEM5-936
Change-Id: I29ed80ff921b205209aeb5db05ffd3019d8595ce
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43591
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
To properly implement load-store instructions for use with
the TimingSimpleCPU model, the initiateAcc() part of the
instruction should only be responsible for performing the
effective address computation and then initiating memory
access.
The completeAcc() part of the instruction should then be
responsible for setting the condition register flags or
updating the base register based on the outcome of the
memory access. This fixes the following instructions:
* Load Byte and Zero with Update (lbzu)
* Load Halfword and Zero with Update (lhzu)
* Load Halfword Algebraic with Update (lhau)
* Load Word and Zero with Update (lwzu)
* Load Doubleword with Update (ldu)
* Load Floating Single with Update (lfsu)
* Load Floating Double with Update (lfdu)
* Load Byte and Zero with Update Indexed (lbzux)
* Load Halfword and Zero with Update Indexed (lhzux)
* Load Halfword Algebraic with Update Indexed (lhaux)
* Load Word and Zero with Update Indexed (lwzux)
* Load Word Algebraic with Update Indexed (lwaux)
* Load Doubleword with Update Indexed (ldux)
* Load Floating Single with Update Indexed (lfsux)
* Load Floating Double with Update Indexed (lfdux)
* Load Byte And Reserve Indexed (lbarx)
* Load Halfword And Reserve Indexed (lharx)
* Load Word And Reserve Indexed (lwarx)
* Load Doubleword And Reserve Indexed (ldarx)
* Store Byte with Update (stbu)
* Store Halfword with Update (sthu)
* Store Word with Update (stwu)
* Store Doubleword with Update (stdu)
* Store Byte with Update Indexed (stbux)
* Store Halfword with Update Indexed (sthux)
* Store Word with Update Indexed (stwux)
* Store Doubleword with Update Indexed (stdux)
* Store Byte Conditional Indexed (stbcx.)
* Store Halfword Conditional Indexed (sthcx.)
* Store Word Conditional Indexed (stwcx.)
* Store Doubleword Conditional Indexed (stdcx.)
* Store Floating Single with Update (stfsu)
* Store Floating Double with Update (stdsu)
* Store Floating Single with Update Indexed (stfsux)
* Store Floating Double with Update Indexed (stfdux)
Change-Id: If5f720619ec3c40a90c1362a9dfc8cc204e57acf
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40947
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This adds multi-mode support for remote debugging via GDB
with the addition of the XML target description files for
both 32-bit and 64-bit variants of the Power architecture.
Proper byte order conversions have also been added.
MSR has now been modeled to some extent but it is still
not exposed by getRegs() since its a privileged register
that cannot be modified from userspace. Similarly, the
target descriptions require FPSCR to also be part of the
payload and hence, it has been added too.
Change-Id: I156fdccb791f161959dbb2c3dd8ab1e510d9cd4b
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40946
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
