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To properly implement load-store instructions for use with the TimingSimpleCPU model, the initiateAcc() part of the instruction should only be responsible for performing the effective address computation and then initiating memory access. The completeAcc() part of the instruction should then be responsible for setting the condition register flags or updating the base register based on the outcome of the memory access. This fixes the following instructions: * Load Byte and Zero with Update (lbzu) * Load Halfword and Zero with Update (lhzu) * Load Halfword Algebraic with Update (lhau) * Load Word and Zero with Update (lwzu) * Load Doubleword with Update (ldu) * Load Floating Single with Update (lfsu) * Load Floating Double with Update (lfdu) * Load Byte and Zero with Update Indexed (lbzux) * Load Halfword and Zero with Update Indexed (lhzux) * Load Halfword Algebraic with Update Indexed (lhaux) * Load Word and Zero with Update Indexed (lwzux) * Load Word Algebraic with Update Indexed (lwaux) * Load Doubleword with Update Indexed (ldux) * Load Floating Single with Update Indexed (lfsux) * Load Floating Double with Update Indexed (lfdux) * Load Byte And Reserve Indexed (lbarx) * Load Halfword And Reserve Indexed (lharx) * Load Word And Reserve Indexed (lwarx) * Load Doubleword And Reserve Indexed (ldarx) * Store Byte with Update (stbu) * Store Halfword with Update (sthu) * Store Word with Update (stwu) * Store Doubleword with Update (stdu) * Store Byte with Update Indexed (stbux) * Store Halfword with Update Indexed (sthux) * Store Word with Update Indexed (stwux) * Store Doubleword with Update Indexed (stdux) * Store Byte Conditional Indexed (stbcx.) * Store Halfword Conditional Indexed (sthcx.) * Store Word Conditional Indexed (stwcx.) * Store Doubleword Conditional Indexed (stdcx.) * Store Floating Single with Update (stfsu) * Store Floating Double with Update (stdsu) * Store Floating Single with Update Indexed (stfsux) * Store Floating Double with Update Indexed (stfdux) Change-Id: If5f720619ec3c40a90c1362a9dfc8cc204e57acf Signed-off-by: Sandipan Das <sandipan@linux.ibm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40947 Reviewed-by: Boris Shingarov <shingarov@labware.com> Maintainer: Boris Shingarov <shingarov@labware.com> Tested-by: kokoro <noreply+kokoro@google.com>
This is the gem5 simulator. The main website can be found at http://www.gem5.org A good starting point is http://www.gem5.org/about, and for more information about building the simulator and getting started please see http://www.gem5.org/documentation and http://www.gem5.org/documentation/learning_gem5/introduction. To build gem5, you will need the following software: g++ or clang, Python (gem5 links in the Python interpreter), SCons, SWIG, zlib, m4, and lastly protobuf if you want trace capture and playback support. Please see http://www.gem5.org/documentation/general_docs/building for more details concerning the minimum versions of the aforementioned tools. Once you have all dependencies resolved, type 'scons build/<ARCH>/gem5.opt' where ARCH is one of ARM, NULL, MIPS, POWER, SPARC, or X86. This will build an optimized version of the gem5 binary (gem5.opt) for the the specified architecture. See http://www.gem5.org/documentation/general_docs/building for more details and options. The basic source release includes these subdirectories: - configs: example simulation configuration scripts - ext: less-common external packages needed to build gem5 - src: source code of the gem5 simulator - system: source for some optional system software for simulated systems - tests: regression tests - util: useful utility programs and files To run full-system simulations, you will need compiled system firmware (console and PALcode for Alpha), kernel binaries and one or more disk images. If you have questions, please send mail to gem5-users@gem5.org Enjoy using gem5 and please share your modifications and extensions.