arch-gcn3: Read registers in execute instead of initiateAcc
Certain memory writes were reading their registers in initiateAcc, which lead to scenarios where a subsequent instruction would execute, clobbering the value in that register before the memory writes' initiateAcc method was called, causing the memory write to read wrong data. This patch moves all register reads to execute, preventing the above scenario from happening. Change-Id: Iee107c19e4b82c2e172bf2d6cc95b79983a43d83 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45345 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com> Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Reviewed-by: Alex Dutu <alexandru.dutu@amd.com> Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
This commit is contained in:
Kyle Roarty
committed by
Matt Sinclair
Matt Sinclair
parent
5ff1fac819
commit
ccfee78f3a
@@ -5068,8 +5068,13 @@ namespace Gcn3ISA
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gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
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ScalarRegU32 offset(0);
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ConstScalarOperandU64 addr(gpuDynInst, instData.SBASE << 1);
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ConstScalarOperandU32 sdata(gpuDynInst, instData.SDATA);
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addr.read();
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sdata.read();
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std::memcpy((void*)gpuDynInst->scalar_data, sdata.rawDataPtr(),
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sizeof(ScalarRegU32));
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if (instData.IMM) {
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offset = extData.OFFSET;
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@@ -5093,10 +5098,6 @@ namespace Gcn3ISA
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void
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Inst_SMEM__S_STORE_DWORD::initiateAcc(GPUDynInstPtr gpuDynInst)
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{
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ConstScalarOperandU32 sdata(gpuDynInst, instData.SDATA);
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sdata.read();
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std::memcpy((void*)gpuDynInst->scalar_data, sdata.rawDataPtr(),
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sizeof(ScalarRegU32));
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initMemWrite<1>(gpuDynInst);
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} // initiateAcc
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@@ -5127,8 +5128,13 @@ namespace Gcn3ISA
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gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
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ScalarRegU32 offset(0);
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ConstScalarOperandU64 addr(gpuDynInst, instData.SBASE << 1);
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ConstScalarOperandU64 sdata(gpuDynInst, instData.SDATA);
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addr.read();
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sdata.read();
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std::memcpy((void*)gpuDynInst->scalar_data, sdata.rawDataPtr(),
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sizeof(ScalarRegU64));
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if (instData.IMM) {
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offset = extData.OFFSET;
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@@ -5152,10 +5158,6 @@ namespace Gcn3ISA
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void
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Inst_SMEM__S_STORE_DWORDX2::initiateAcc(GPUDynInstPtr gpuDynInst)
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{
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ConstScalarOperandU64 sdata(gpuDynInst, instData.SDATA);
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sdata.read();
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std::memcpy((void*)gpuDynInst->scalar_data, sdata.rawDataPtr(),
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sizeof(ScalarRegU64));
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initMemWrite<2>(gpuDynInst);
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} // initiateAcc
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@@ -5186,8 +5188,13 @@ namespace Gcn3ISA
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gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
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ScalarRegU32 offset(0);
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ConstScalarOperandU64 addr(gpuDynInst, instData.SBASE << 1);
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ConstScalarOperandU128 sdata(gpuDynInst, instData.SDATA);
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addr.read();
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sdata.read();
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std::memcpy((void*)gpuDynInst->scalar_data, sdata.rawDataPtr(),
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4 * sizeof(ScalarRegU32));
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if (instData.IMM) {
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offset = extData.OFFSET;
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@@ -5211,10 +5218,6 @@ namespace Gcn3ISA
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void
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Inst_SMEM__S_STORE_DWORDX4::initiateAcc(GPUDynInstPtr gpuDynInst)
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{
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ConstScalarOperandU128 sdata(gpuDynInst, instData.SDATA);
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sdata.read();
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std::memcpy((void*)gpuDynInst->scalar_data, sdata.rawDataPtr(),
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4 * sizeof(ScalarRegU32));
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initMemWrite<4>(gpuDynInst);
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} // initiateAcc
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@@ -35746,9 +35749,18 @@ namespace Gcn3ISA
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ConstVecOperandU32 addr1(gpuDynInst, extData.VADDR + 1);
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ConstScalarOperandU128 rsrcDesc(gpuDynInst, extData.SRSRC * 4);
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ConstScalarOperandU32 offset(gpuDynInst, extData.SOFFSET);
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ConstVecOperandI8 data(gpuDynInst, extData.VDATA);
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rsrcDesc.read();
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offset.read();
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data.read();
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for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
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if (gpuDynInst->exec_mask[lane]) {
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(reinterpret_cast<VecElemI8*>(gpuDynInst->d_data))[lane]
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= data[lane];
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}
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}
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int inst_offset = instData.OFFSET;
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@@ -35793,16 +35805,6 @@ namespace Gcn3ISA
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void
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Inst_MUBUF__BUFFER_STORE_BYTE::initiateAcc(GPUDynInstPtr gpuDynInst)
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{
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ConstVecOperandI8 data(gpuDynInst, extData.VDATA);
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data.read();
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for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
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if (gpuDynInst->exec_mask[lane]) {
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(reinterpret_cast<VecElemI8*>(gpuDynInst->d_data))[lane]
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= data[lane];
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}
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}
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initMemWrite<VecElemI8>(gpuDynInst);
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} // initiateAcc
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@@ -35842,9 +35844,18 @@ namespace Gcn3ISA
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ConstVecOperandU32 addr1(gpuDynInst, extData.VADDR + 1);
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ConstScalarOperandU128 rsrcDesc(gpuDynInst, extData.SRSRC * 4);
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ConstScalarOperandU32 offset(gpuDynInst, extData.SOFFSET);
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ConstVecOperandI16 data(gpuDynInst, extData.VDATA);
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rsrcDesc.read();
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offset.read();
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data.read();
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for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
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if (gpuDynInst->exec_mask[lane]) {
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(reinterpret_cast<VecElemI16*>(gpuDynInst->d_data))[lane]
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= data[lane];
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}
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}
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int inst_offset = instData.OFFSET;
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@@ -35889,16 +35900,6 @@ namespace Gcn3ISA
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void
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Inst_MUBUF__BUFFER_STORE_SHORT::initiateAcc(GPUDynInstPtr gpuDynInst)
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{
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ConstVecOperandI16 data(gpuDynInst, extData.VDATA);
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data.read();
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for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
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if (gpuDynInst->exec_mask[lane]) {
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(reinterpret_cast<VecElemI16*>(gpuDynInst->d_data))[lane]
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= data[lane];
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}
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}
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initMemWrite<VecElemI16>(gpuDynInst);
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} // initiateAcc
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@@ -35938,12 +35939,21 @@ namespace Gcn3ISA
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ConstVecOperandU32 addr1(gpuDynInst, extData.VADDR + 1);
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ConstScalarOperandU128 rsrcDesc(gpuDynInst, extData.SRSRC * 4);
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ConstScalarOperandU32 offset(gpuDynInst, extData.SOFFSET);
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ConstVecOperandU32 data(gpuDynInst, extData.VDATA);
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rsrcDesc.read();
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offset.read();
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data.read();
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int inst_offset = instData.OFFSET;
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for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
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if (gpuDynInst->exec_mask[lane]) {
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(reinterpret_cast<VecElemU32*>(gpuDynInst->d_data))[lane]
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= data[lane];
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}
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}
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if (!instData.IDXEN && !instData.OFFEN) {
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calcAddr<ConstVecOperandU32, ConstVecOperandU32,
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ConstScalarOperandU128, ConstScalarOperandU32>(gpuDynInst,
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@@ -35985,16 +35995,6 @@ namespace Gcn3ISA
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void
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Inst_MUBUF__BUFFER_STORE_DWORD::initiateAcc(GPUDynInstPtr gpuDynInst)
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{
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ConstVecOperandU32 data(gpuDynInst, extData.VDATA);
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data.read();
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for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
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if (gpuDynInst->exec_mask[lane]) {
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(reinterpret_cast<VecElemU32*>(gpuDynInst->d_data))[lane]
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= data[lane];
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}
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}
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initMemWrite<VecElemU32>(gpuDynInst);
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} // initiateAcc
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@@ -39998,11 +39998,20 @@ namespace Gcn3ISA
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gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
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ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
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ConstVecOperandU8 data(gpuDynInst, extData.DATA);
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addr.read();
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data.read();
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calcAddr(gpuDynInst, addr);
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for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
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if (gpuDynInst->exec_mask[lane]) {
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(reinterpret_cast<VecElemU8*>(gpuDynInst->d_data))[lane]
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= data[lane];
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}
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}
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if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
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gpuDynInst->computeUnit()->globalMemoryPipe
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.issueRequest(gpuDynInst);
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@@ -40019,16 +40028,6 @@ namespace Gcn3ISA
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void
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Inst_FLAT__FLAT_STORE_BYTE::initiateAcc(GPUDynInstPtr gpuDynInst)
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{
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ConstVecOperandU8 data(gpuDynInst, extData.DATA);
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data.read();
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for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
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if (gpuDynInst->exec_mask[lane]) {
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(reinterpret_cast<VecElemU8*>(gpuDynInst->d_data))[lane]
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= data[lane];
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}
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}
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initMemWrite<VecElemU8>(gpuDynInst);
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} // initiateAcc
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@@ -40068,11 +40067,20 @@ namespace Gcn3ISA
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gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
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ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
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ConstVecOperandU16 data(gpuDynInst, extData.DATA);
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addr.read();
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data.read();
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calcAddr(gpuDynInst, addr);
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for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
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if (gpuDynInst->exec_mask[lane]) {
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(reinterpret_cast<VecElemU16*>(gpuDynInst->d_data))[lane]
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= data[lane];
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}
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}
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if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
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gpuDynInst->computeUnit()->globalMemoryPipe
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.issueRequest(gpuDynInst);
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@@ -40089,17 +40097,6 @@ namespace Gcn3ISA
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void
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Inst_FLAT__FLAT_STORE_SHORT::initiateAcc(GPUDynInstPtr gpuDynInst)
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{
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ConstVecOperandU16 data(gpuDynInst, extData.DATA);
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data.read();
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for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
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if (gpuDynInst->exec_mask[lane]) {
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(reinterpret_cast<VecElemU16*>(gpuDynInst->d_data))[lane]
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= data[lane];
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}
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}
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initMemWrite<VecElemU16>(gpuDynInst);
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} // initiateAcc
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@@ -40139,11 +40136,20 @@ namespace Gcn3ISA
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gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
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ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
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ConstVecOperandU32 data(gpuDynInst, extData.DATA);
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addr.read();
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data.read();
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calcAddr(gpuDynInst, addr);
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for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
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if (gpuDynInst->exec_mask[lane]) {
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(reinterpret_cast<VecElemU32*>(gpuDynInst->d_data))[lane]
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= data[lane];
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}
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}
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if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
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gpuDynInst->computeUnit()->globalMemoryPipe
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.issueRequest(gpuDynInst);
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@@ -40160,16 +40166,6 @@ namespace Gcn3ISA
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void
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Inst_FLAT__FLAT_STORE_DWORD::initiateAcc(GPUDynInstPtr gpuDynInst)
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{
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ConstVecOperandU32 data(gpuDynInst, extData.DATA);
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data.read();
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for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
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if (gpuDynInst->exec_mask[lane]) {
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(reinterpret_cast<VecElemU32*>(gpuDynInst->d_data))[lane]
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= data[lane];
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}
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}
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initMemWrite<VecElemU32>(gpuDynInst);
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} // initiateAcc
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@@ -40210,11 +40206,20 @@ namespace Gcn3ISA
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gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
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ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
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ConstVecOperandU64 data(gpuDynInst, extData.DATA);
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addr.read();
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data.read();
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calcAddr(gpuDynInst, addr);
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for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
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if (gpuDynInst->exec_mask[lane]) {
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(reinterpret_cast<VecElemU64*>(gpuDynInst->d_data))[lane]
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= data[lane];
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}
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}
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if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
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gpuDynInst->computeUnit()->globalMemoryPipe
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.issueRequest(gpuDynInst);
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@@ -40231,16 +40236,6 @@ namespace Gcn3ISA
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void
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Inst_FLAT__FLAT_STORE_DWORDX2::initiateAcc(GPUDynInstPtr gpuDynInst)
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{
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ConstVecOperandU64 data(gpuDynInst, extData.DATA);
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data.read();
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for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
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if (gpuDynInst->exec_mask[lane]) {
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(reinterpret_cast<VecElemU64*>(gpuDynInst->d_data))[lane]
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= data[lane];
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}
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}
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initMemWrite<VecElemU64>(gpuDynInst);
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} // initiateAcc
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@@ -40281,11 +40276,28 @@ namespace Gcn3ISA
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gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
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ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
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ConstVecOperandU32 data0(gpuDynInst, extData.DATA);
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ConstVecOperandU32 data1(gpuDynInst, extData.DATA + 1);
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ConstVecOperandU32 data2(gpuDynInst, extData.DATA + 2);
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addr.read();
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data0.read();
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data1.read();
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data2.read();
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calcAddr(gpuDynInst, addr);
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for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
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if (gpuDynInst->exec_mask[lane]) {
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(reinterpret_cast<VecElemU32*>(
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gpuDynInst->d_data))[lane * 3] = data0[lane];
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(reinterpret_cast<VecElemU32*>(
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gpuDynInst->d_data))[lane * 3 + 1] = data1[lane];
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(reinterpret_cast<VecElemU32*>(
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gpuDynInst->d_data))[lane * 3 + 2] = data2[lane];
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}
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}
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if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
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gpuDynInst->computeUnit()->globalMemoryPipe
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.issueRequest(gpuDynInst);
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@@ -40302,25 +40314,6 @@ namespace Gcn3ISA
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void
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Inst_FLAT__FLAT_STORE_DWORDX3::initiateAcc(GPUDynInstPtr gpuDynInst)
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{
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ConstVecOperandU32 data0(gpuDynInst, extData.DATA);
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ConstVecOperandU32 data1(gpuDynInst, extData.DATA + 1);
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ConstVecOperandU32 data2(gpuDynInst, extData.DATA + 2);
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data0.read();
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data1.read();
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data2.read();
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for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
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if (gpuDynInst->exec_mask[lane]) {
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(reinterpret_cast<VecElemU32*>(
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gpuDynInst->d_data))[lane * 3] = data0[lane];
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(reinterpret_cast<VecElemU32*>(
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gpuDynInst->d_data))[lane * 3 + 1] = data1[lane];
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(reinterpret_cast<VecElemU32*>(
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gpuDynInst->d_data))[lane * 3 + 2] = data2[lane];
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}
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}
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initMemWrite<3>(gpuDynInst);
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} // initiateAcc
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@@ -40361,11 +40354,32 @@ namespace Gcn3ISA
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gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
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ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
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ConstVecOperandU32 data0(gpuDynInst, extData.DATA);
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ConstVecOperandU32 data1(gpuDynInst, extData.DATA + 1);
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ConstVecOperandU32 data2(gpuDynInst, extData.DATA + 2);
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ConstVecOperandU32 data3(gpuDynInst, extData.DATA + 3);
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addr.read();
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data0.read();
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data1.read();
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data2.read();
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data3.read();
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calcAddr(gpuDynInst, addr);
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for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
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if (gpuDynInst->exec_mask[lane]) {
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(reinterpret_cast<VecElemU32*>(
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gpuDynInst->d_data))[lane * 4] = data0[lane];
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(reinterpret_cast<VecElemU32*>(
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gpuDynInst->d_data))[lane * 4 + 1] = data1[lane];
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(reinterpret_cast<VecElemU32*>(
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gpuDynInst->d_data))[lane * 4 + 2] = data2[lane];
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(reinterpret_cast<VecElemU32*>(
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gpuDynInst->d_data))[lane * 4 + 3] = data3[lane];
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}
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}
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if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
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gpuDynInst->computeUnit()->globalMemoryPipe
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.issueRequest(gpuDynInst);
|
||||
@@ -40382,29 +40396,6 @@ namespace Gcn3ISA
|
||||
void
|
||||
Inst_FLAT__FLAT_STORE_DWORDX4::initiateAcc(GPUDynInstPtr gpuDynInst)
|
||||
{
|
||||
ConstVecOperandU32 data0(gpuDynInst, extData.DATA);
|
||||
ConstVecOperandU32 data1(gpuDynInst, extData.DATA + 1);
|
||||
ConstVecOperandU32 data2(gpuDynInst, extData.DATA + 2);
|
||||
ConstVecOperandU32 data3(gpuDynInst, extData.DATA + 3);
|
||||
|
||||
data0.read();
|
||||
data1.read();
|
||||
data2.read();
|
||||
data3.read();
|
||||
|
||||
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
|
||||
if (gpuDynInst->exec_mask[lane]) {
|
||||
(reinterpret_cast<VecElemU32*>(
|
||||
gpuDynInst->d_data))[lane * 4] = data0[lane];
|
||||
(reinterpret_cast<VecElemU32*>(
|
||||
gpuDynInst->d_data))[lane * 4 + 1] = data1[lane];
|
||||
(reinterpret_cast<VecElemU32*>(
|
||||
gpuDynInst->d_data))[lane * 4 + 2] = data2[lane];
|
||||
(reinterpret_cast<VecElemU32*>(
|
||||
gpuDynInst->d_data))[lane * 4 + 3] = data3[lane];
|
||||
}
|
||||
}
|
||||
|
||||
initMemWrite<4>(gpuDynInst);
|
||||
} // initiateAcc
|
||||
|
||||
|
||||
Reference in New Issue
Block a user