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arch-arm: Rename debug variables

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Pave the way for a "debug" namespace.

Change-Id: I1796711cbde527269637b30b0b09cd06c9e25fa1
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47304
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Daniel R. Carvalho
2021-06-08 14:27:27 -03:00
committed by Daniel Carvalho
parent 444cbe6250
commit 7ded9b414c
3 changed files with 15 additions and 20 deletions
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10
src/arch/arm/faults.cc
View File

@@ -1103,16 +1103,16 @@ AbortFault<T>::invoke(ThreadContext *tc, const StaticInstPtr &inst)
} else if (stage2) {
tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf);
tc->setMiscReg(T::HFarIndex, OVAddr);
} else if (debug > ArmFault::NODEBUG) {
} else if (debugType > ArmFault::NODEBUG) {
DBGDS32 Rext = tc->readMiscReg(MISCREG_DBGDSCRext);
tc->setMiscReg(T::FarIndex, faultAddr);
if (debug == ArmFault::BRKPOINT){
if (debugType == ArmFault::BRKPOINT){
Rext.moe = 0x1;
} else if (debug == ArmFault::VECTORCATCH){
} else if (debugType == ArmFault::VECTORCATCH){
Rext.moe = 0x5;
} else if (debug > ArmFault::VECTORCATCH) {
} else if (debugType > ArmFault::VECTORCATCH) {
Rext.moe = 0xa;
fsr.cm = (debug == ArmFault::WPOINT_CM)? 1 : 0;
fsr.cm = (debugType == ArmFault::WPOINT_CM)? 1 : 0;
}
tc->setMiscReg(T::FsrIndex, fsr);

5
src/arch/arm/faults.hh
View File

@@ -456,7 +456,7 @@ class AbortFault : public ArmFaultVals<T>
bool stage2;
bool s1ptw;
ArmFault::TranMethod tranMethod;
ArmFault::DebugType debug;
ArmFault::DebugType debugType;
public:
AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain,
@@ -465,7 +465,8 @@ class AbortFault : public ArmFaultVals<T>
ArmFault::DebugType _debug = ArmFault::NODEBUG) :
faultAddr(_faultAddr), OVAddr(0), write(_write),
domain(_domain), source(_source), srcEncoded(0),
stage2(_stage2), s1ptw(false), tranMethod(_tranMethod), debug(_debug)
stage2(_stage2), s1ptw(false), tranMethod(_tranMethod),
debugType(_debug)
{}
bool getFaultVAddr(Addr &va) const override;

20
src/arch/arm/self_debug.cc
View File

@@ -96,8 +96,7 @@ SelfDebug::testBreakPoints(ThreadContext *tc, Addr vaddr)
if (p.enable && p.isActive(pc) &&(!to32 || !p.onUse)) {
const DBGBCR ctr = p.getControlReg(tc);
if (p.isEnabled(tc, el, ctr.hmc, ctr.ssc, ctr.pmc)) {
bool debug = p.test(tc, pc, el, ctr, false);
if (debug){
if (p.test(tc, pc, el, ctr, false)) {
if (to32)
p.onUse = true;
return triggerException(tc, pc);
@@ -138,8 +137,7 @@ SelfDebug::testWatchPoints(ThreadContext *tc, Addr vaddr, bool write,
for (auto &p: arWatchPoints){
idxtmp ++;
if (p.enable) {
bool debug = p.test(tc, vaddr, el, write, atomic, size);
if (debug){
if (p.test(tc, vaddr, el, write, atomic, size)) {
return triggerWatchpointException(tc, vaddr, write, cm);
}
}
@@ -212,12 +210,8 @@ SelfDebug::isDebugEnabledForEL32(ThreadContext *tc, ExceptionLevel el,
bool
BrkPoint::testLinkedBk(ThreadContext *tc, Addr vaddr, ExceptionLevel el)
{
bool debug = false;
const DBGBCR ctr = getControlReg(tc);
if ((ctr.bt & 0x1) && enable) {
debug = test(tc, vaddr, el, ctr, true);
}
return debug;
return ((ctr.bt & 0x1) && enable) && test(tc, vaddr, el, ctr, true);
}
bool
@@ -730,12 +724,12 @@ SelfDebug::testVectorCatch(ThreadContext *tc, Addr addr,
return NoFault;
ExceptionLevel el = (ExceptionLevel) currEL(tc);
bool debug;
bool do_debug;
if (fault == nullptr)
debug = vcExcpt->addressMatching(tc, addr, el);
do_debug = vcExcpt->addressMatching(tc, addr, el);
else
debug = vcExcpt->exceptionTrapping(tc, el, fault);
if (debug) {
do_debug = vcExcpt->exceptionTrapping(tc, el, fault);
if (do_debug) {
if (enableTdeTge) {
return std::make_shared<HypervisorTrap>(0, 0x22,
EC_PREFETCH_ABORT_TO_HYP);