Commit Graph

19495 Commits

Author SHA1 Message Date
Zhantong Qiu
9ac075ea36 stdlib: added errout and output file option in SE process
In the set_se_binary_workload(), added stdout_file and stderr_file
arguments to setup process.errout and process.output.

Change-Id: I54db2248578f485a633d6b6212fa6c62bcbca4de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64151
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2022-10-11 00:32:50 +00:00
Bobby R. Bruce
0ac27fd0bc util-docker,tests: Update supported/test OS to Ubuntu 22.04
We add a Ubuntu 22.04 min- and all-dependency docker images. We also
update the compiler tests to compile with Ubuntu 22.04.

The Ubuntu 20.04 min-dependency image has been removed. It is no
longer required.

Change-Id: Iaf7f7e8598907beb16e154c971f327927f707cb9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64177
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2022-10-10 17:24:03 +00:00
Bobby R. Bruce
555ed60eaa util-docker,tests: Add Clang-14 compiler image and test
This increases gem5's supported compiler up to Clang Version 14.

Change-Id: Ia85e81f33367b7186dd54fc2aeb3541111ccdb57
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64176
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-10 17:24:03 +00:00
Bobby R. Bruce
57a5bebe80 util-docker,tests: Add Clang-13 compiler image and test
This increases gem5's supported compiler up to Clang Version 13.

Change-Id: I5a9b602b67626b195dcd8e297abbcfb70cf83cbe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64175
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-10 17:24:03 +00:00
Bobby R. Bruce
be64af890a util-docker,tests: Add GCC-12 compiler image and test
This increases gem5's supported compiler up to GCC Version 12

Change-Id: Ifed5b8456bd1ab36a2fa58d8be7911acbef29bdd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64174
Reviewed-by: Kunal Pai <kunpai@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2022-10-10 17:24:03 +00:00
Bobby R. Bruce
8c34a8bf92 util-docker: Add 'ubuntu-22.04_gcc-version'
Now that ubuntu 22.04 has been released we can use it to test newer GCC
compilers. GCC-11 has been moved to use this image.

Change-Id: I3b0dbd82112068f19682e5cf19ffbe81f3d18149
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64173
Reviewed-by: Kunal Pai <kunpai@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-10 17:24:03 +00:00
Bobby R. Bruce
6e182b025d mem-ruby: Fix clang-14 compilation warning "use of bitwise"
Clang Version 14 throws a warning "use of bitwise '&/|' with boolean
operands" for cases where bitwise operations are used where boolean
operations are intended.

This occurred in "WriteMast.hh", "data.isa", and "decode.cc" where
boolean values were being compared using the bitwise operands. While
bitwise operations are equivalent, they have been changed to boolean
operations in this patch to avoid the clang-14 warning.

Change-Id: Ic7583e13a325661712c75c8e1b234c4878832352
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64172
Reviewed-by: Tom Rollet <tom.rollet@huawei.com>
Reviewed-by: Kunal Pai <kunpai@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-10 17:24:03 +00:00
Bobby R. Bruce
abad2d6532 mem: Fix 'unused variable' warnings
The `Addr line_addr` in "src/mem/snoop_filter.cc" variable was only
used in an assert, stripped when compiling gem5.fast.
Clang-13 throws a warning for this variable. This has been fixed by
merging the variable and associated logic into the assert statement.

The variables in inet.cc and Sequencer.cc were also causing an 'unused
variable' warning to be thrown due to variables that were only used in
assert statements. In these cases the logic could not be moved into the
assert statement and, as such, the `GEM5_VAR_USED` MACRO is used to
remove this warning.

Change-Id: I6511d0863608c38b79e4558c7dcf35a323fe8362
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64171
Reviewed-by: Kunal Pai <kunpai@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2022-10-10 17:24:03 +00:00
Jason Lowe-Power
d2a6d2f7ee stdlib: Add _post_instantiate function
This function will be called on the board after m5.instantiate is
called. This is useful, for instance, to start traffic generators.
Currently all implementations simply `pass`.

Change-Id: Ie2ab3fdddca5f3978d98191e5c08504561587fbb
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64016
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-07 23:52:14 +00:00
Jason Lowe-Power
55f80ae0a1 stdlib: Allow cache_hierarchy to be optional
This changeset makes the cache_hierarchy optional on the board. This
will allow us to enable the TestBoard to have memory directly connected
to the traffic generator.

Change-Id: I62d310e74c43724ea38e3b71a4d91d9e06d6e855
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64015
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2022-10-07 23:51:18 +00:00
Jason Lowe-Power
007a99e9a0 stdlib: Update the default exit events and warning
This change updates the default actions taken when the user doesn't
specify generators for the exit events in the simulator. Rather than
defining default generators, this change makes the generators more
generic and gives a new decorator to mark them as default.

This change then updates the default generators in the simulator and
only makes some of them issue a default warning. For exit events such as
EXIT, the default will no longer print a warning.

Change-Id: I5552f52392f3aea577034ed278a9ff9e8b5b0b01
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64251
Reviewed-by: Zhantong Qiu <ztqiu@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-07 23:50:41 +00:00
Yu-hsin Wang
0e20edac34 systemc: fix flexible conversion when reusing transactions
To make the all extension states correct, we still need to proceed the
plugins when reusing the transactions, since we don't know the detail of
the plugins.

Change-Id: I18acd64f54be4c82a0678b98e834ea9548de1f58
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63871
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-07 09:40:43 +00:00
Matthew Poremba
ec696c00b2 gpu-compute: Add missing initial reg state in WF
There are two initial scalar register fields that are not initialized in
the wavefront when a task is dispatch. This changeset adds the missing
DispatchId and PrivateSegSize fields. These fields are typically used
when an application is compiled with debug support and are typically not
used in the applications in gem5's test suite.

Change-Id: I5b5fa75e4badfd9ba7588e4cd485ebf75fd5d627
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64191
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-06 23:14:40 +00:00
Bobby R. Bruce
e844f17045 tests: Exclude ARM KVM tests from nightly run
Our Jenkin's server is an X86 host and cannot run ARM KVM.

Change-Id: Id10988aefa2534e73407c6a241fb3d5c9d958b7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64111
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2022-10-06 17:30:06 +00:00
Matthew Poremba
925b1b5c8e arch-vega: Implement V_XAD_U32 instruction
Used in rodinia:heartwall.  This instruction is new in vega and does not
exist in GCN3.

Change-Id: I6127290d1c85688a7f82e149e97762ca55e05fc6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63972
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-06 16:42:40 +00:00
Quentin Forcioli
e94c9f362c base: singleStep can't be interupted by trap from other thread.
Change-Id: I0c46e3ea623b304b7ae8f8867d90c5d0008e8b3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63533
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-06 14:35:40 +00:00
Quentin Forcioli
bff69e4792 base: adding a scheduleTrapEvent
This function centralize setting up a new trapEvent making sure that
the contextId match with the ThreadContext use for the Event.

Change-Id: I2a5f77da049d140b9ceffd42011fd8a1da59092e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63532
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2022-10-06 14:35:23 +00:00
Quentin Forcioli
2ae9692dfe base, sim: Adding support for message to GDB from python
Adding a small python function that allows to display
messages directly in GDB from the python interpreter.
This function is inside the Workload SimObject
(The stub is not a SimObject).
ex:
     system.workload.sendToGdb("message to display")

Change-Id: I46ddae079b10d298743e023f95bf15608f50e358
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63531
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-06 14:34:55 +00:00
Quentin Forcioli
eeaeee15aa base: adding queryAttached and querySymbol to GDB
In some cases/version these queries might be needed
to make the remote GDB connect correctly to the stub.

Change-Id: I98cdc9b4a952b4dc64f9357e6148af6e3351ef92
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63530
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-06 14:34:30 +00:00
Quentin Forcioli
3e43603dcc base: adding support for O packet
O packet allow the GDB stub to send a message to display for the GDB
remote.
This function could be used to implement certains specific command
response.

Change-Id: I1c9a1ca956efcf19c93a8503d97c1fb27f555966
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63529
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-06 14:34:15 +00:00
Quentin Forcioli
bb78d14c08 base: Adding stop reason and T Packet to the GDB stub
The remote protocol describes 2 type of stop respond packet.

S packets (which are the one that where used before) and T packets.

T packet support multiple fields to give more information about:
   - thread/core which stopped
   - registers values
   - A stopReason string that are predefined value and that can
     differentiate between different types of break that would
     issue the same signal.

Change-Id: Id8ed7115898bf825dd14395f586c393d6f5aa2bc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63528
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-06 14:33:40 +00:00
Quentin Forcioli
cee2aa39b6 base: cmdIsThreadAlive implementation
Some GDB implementations, specifically ARM's, needed this to be able to
switch between thread.

Change-Id: I0d4db0c008c336eac51008bcfefd04c375c333f7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63527
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-06 14:33:23 +00:00
Quentin Forcioli
e6287f7b19 base: making GDB's getbyte and send more resilient
Add a try_getbyte function that feature a timeout. This function uses
select to detect update on the file descriptor used to communicate with
the remote.
It is used to implement getbyte and to clean the file
descriptor before sending a message with send.

Now getbyte and send can recover from certains error like interruption
by other signals (EINTR) or delays causing the remote server to send
error packet to the stub.

Change-Id: Ie06845ba59dee0ad831632d5bc2b15132c9d5450
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63526
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-06 14:32:29 +00:00
Quentin Forcioli
832b0ee6b9 base: Adding multi-letter command support to GDB stub
The GDB remote protocol defines multi-letter
 command names that start with a "v".
I added vKill and vMustReplyEmpty as an example.

Change-Id: I10177729c7d6a3e7d469ce66a63bfcfd21aa6f83
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63525
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2022-10-06 14:32:19 +00:00
Ayaz Akram
335d2e187e arch-x86, mem: Add support to tag tlb entries with PCID
This change adds support to tag tlb entries with PCID to
avoid the conflict between different processes with same
virtual addresses sharing a tlb. This eventually is required
to enable smt support for x86.

Change-Id: Ia91dc371482793962e3fc83afe7a3fd2cdb60eab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35836
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-05 17:44:59 +00:00
Ayaz Akram
09aeb51350 arch-x86, mem: Add support for PCID to x86
This change adds Process Context Identifier (PCID) support
to x86, so that tlb entries can be tagged using pcid.

Change-Id: I695eccc4b08476b32d4b3728fc3c42b2ad6f5a28
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35835
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-05 17:44:59 +00:00
Ayaz Akram
ea26611a01 arch-x86: Assign thread context id to APIC id
This change tries to enable a unique APIC id for a single thread
to enable smt support for x86

Change-Id: I3e7034b358623577c5ad4be3e51f08e48291ce49
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35837
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-05 17:44:59 +00:00
Bobby R. Bruce
f59eb93660 tests: Add 'checkpoint-path' to simpoints stdlib example
The
'configs/example/gem5_library_checkpoints/simpoints-se-checkpoint.py'
example would dump the savepoint in the CWD. This is fine when running
as an example, but we also run this script as a test. In this case the
checkpoint litters the repository.

To fix this, an optional 'checkpoint-path' argument is added to this
example which specifies where the checkpoint is to be saved. In the
tests, the checkpoint is saved to 'tests/gem5/resources'. This is our
default location for resources needed/produced by tests and is ignored
by git.

Change-Id: I3dccc574b9e64d32386fd822ed7248ee365a0a08
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64092
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-04 21:31:51 +00:00
Bobby R. Bruce
64a087e5e8 tests: Add 'checkpoint-path' to checkpoint stdlib example
The
'configs/example/gem5_library_example_tests/test_gem5_library_examples.py'
example would dump the savepoint in the CWD. This is fine when running
as an example, but we also run this script as a test. In this case the
checkpoint litters the repository.

To fix this, an optional 'checkpoint-path' argument is added to this
example which specifies where the checkpoint is to be saved. In the
tests, the checkpoint is saved to 'tests/gem5/resources'. This is our
default location for resources needed/produced by tests and is ignored
by git.

Change-Id: Ib985433786c99c37794a1c67cc4337a5dfd0498d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64091
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-10-04 21:31:51 +00:00
Bobby R. Bruce
3e51091806 tests: Add Simpoints example scripts as tests
These both ensure these example scripts still work as intended and
provides tests for the stdlib Simpoint API.

Change-Id: I549c3d22458a5013a335857c83a4e78dc425e37d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63931
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2022-10-04 21:31:51 +00:00
Giacomo Travaglini
cc3c15f1e0 configs, tests: Use proper releases in KVM simulations
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I071f3d9c4eb5e4c7df3052bb8db93fece30cd069
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64073
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-04 09:45:20 +00:00
Giacomo Travaglini
597a2ce4c1 arch-arm: Add ArmRelease factory function to be used in KVM mode
From gem5 v22.0, EL2 and EL3 are automatically implemented
in the default release object [1]. This means any FS simulation
will start at EL3, which is the highest implemented EL.

Unfortunately this doesn't work in KVM mode, which is assuming
a VM does not start at EL3:

As soon as updateKvmState is called [2] gem5 tries to set
the VM PSTATE to EL3 and KVM fails the ioctl PSTATE write

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/51011
[2]: https://github.com/gem5/gem5/blob/v22.0.0.2/\
    src/arch/arm/kvm/armv8_cpu.cc#L237

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Icf951bcfb47e0c2ff9abe64b1b9006934303ad48
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64072
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-04 09:45:20 +00:00
Earl Ou
317bfd62bd dev: fix device number check error in IDE controller
Fixed a typo between 3 and 4.

Change-Id: I1470e30c4d472587db0b9da5512b24ab92f1fd65
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64052
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2022-10-04 01:21:37 +00:00
Giacomo Travaglini
4f09acb2f5 arch-arm: Add the remove method to the ArmRelease class
This allows to remove an extension from a release object

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I60189c37ffcefab991955c3d0bb560a6a79f0977
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64071
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-03 23:00:57 +00:00
paikunal
da5a4d3d8a stdlib, configs: Add example FS script for RISCV Matched
This script loads riscv-bootloader-vmlinux-5.10 onto a
riscv-ubuntu-20.04-img disk image on the RISCVMatched
prebuilt board found at
src/python/gem5/prebuilt/riscvmatched directory.

Change-Id: Ic2b4b19bac0a66d40d667b82a43c7791ff918847
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64014
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-03 22:27:59 +00:00
Giacomo Travaglini
7c0ab07ee2 dev-arm: Fix GICv3 GICD_ITARGETSR address range
According to the GICv3 manual, GICD_ITARGETSR address range goes from
0x0800 to 0x0c00 (as already implemented in the GICv2 model [1])

[1]: https://github.com/gem5/gem5/blob/v22.0.0.0/\
    src/dev/arm/gic_v2.cc#L64

Change-Id: I064e91d070d1a7b79f41a06ffd2197e4c07dae32
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64074
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-03 17:45:10 +00:00
Giacomo Travaglini
336e732d54 misc: Replace namespace Trace with lowercase trace
This is what the coding style demands

Change-Id: Ida6a71ad9c2c02cccd584bbaf37a6da751c5b856
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63891
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
2022-10-02 16:30:15 +00:00
Matthew Poremba
2f1d67f8fe dev-amdgpu: Remove cached copy of device memory
This map was originally used for fast access to the GART table. It is no
longer needed as the table has been moved to the AMDGPUVM class. Along
with commit 12ec5f9172 which reads
functionally from device memory, this table is no longer needed and is
essentially a duplicate copy of device memory for anything written over
the PCI BAR.

This changeset removes the map entirely which will reduce the memory
footprint of simulations and potentially avoid stale copies of data
when reading over the PCI BAR.

Change-Id: I312ae38f869c6a65e50577b1c33dd055078aaf32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63951
Reviewed-by: Matt Sinclair <mattdsinclair.wisc@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2022-10-01 14:04:45 +00:00
vramadas95
a3842f877a configs, gpu-compute: Add configurable L1 access latencies
Previously the L1 request and response latencies were not configurable
in the GPU config scripts. As a result, the simulations used the default
values from GPU.py. This commits adds support to change this value as an
input parameter. The parameters to use are "--mem-req-latency" followed
by the value and "--mem-resp-latency" followed by the value. The default
values are the same as those in GPU.py (which is 50). These new
parameters should be set instead of changing the mandatory queue latency when configuring the L1 cache.

Change-Id: I812d77758ea12530899953f308c91f4c8b05866d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63971
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2022-10-01 06:55:43 +00:00
paikunal
4662e18981 stdlib: Edit RiscvMatched RTC
Fixed the bug that made FS mode break.
Changed RTC value as fix.

Change-Id: I0effa1ecd32a8a8845e619d940f8e0efe549cfc1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64013
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-01 03:44:06 +00:00
Jason Lowe-Power
9a1074d27f scons: Fix variable not found error
Change-Id: I09708fea777a57a35e55409c8997ed0b25de2b46
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64012
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Melissa Jost <melissakjost@gmail.com>
2022-10-01 01:17:13 +00:00
Jason Lowe-Power
e7a73c7b59 tests: Fix error in Arm test
I missed this one in the last changeset.

Change-Id: I71d7fa2ac4ff36d4aef5d950e6ed8973ffc32a4e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63991
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Melissa Jost <melissakjost@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-09-30 14:39:39 +00:00
Carlos Falquez
a57f08f355 mem-garnet: Add masked functionalRead support
Recently the CHI protocol was introduced in Ruby.
The protocol introduces an alternative interface for
functional reads:

bool functionalRead(PacketPtr, WriteMask&)

This commit adds functionalRead(PacketPtr, WriteMask&)
implementations for various Garnet components.

Change-Id: Idd571899d679407b7b000c1a83a0a5420868cf28
Signed-off-by: Carlos Falquez <c.falquez@fz-juelich.de>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46900
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-09-29 06:46:21 +00:00
Tiago Mück
14312b650a configs: fix CHI config for Garnet
CHI.py was not working with Garnet as ruby_system.network.buffer_size
only exists in SimpleNetwork.

Change-Id: I00e952f8881d385e3591c149e08c9c7a53fda2cd
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63811
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-09-28 18:56:04 +00:00
Tiago Mück
ae266b3a85 configs: fix CustomMesh router parent
This fixes the routers being set as the links' children. This is
necessary here as we only assign the routers to the network once
all routers and links are created.

Change-Id: I2ac90b575bad593ddbb8ab716872a30a5c4c6979
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63677
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-09-28 18:56:04 +00:00
Tiago Mück
027b508a38 mem-ruby: fix missing transition in CHI-mem
JIRA: https://gem5.atlassian.net/browse/GEM5-1195

Change-Id: I0aae4b9042cb6565c77cc8781b514a9e65ab161b
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63676
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-09-28 18:56:04 +00:00
Tiago Mück
c6a460eff4 mem-ruby: fix CHI memory controller
Break up the transition to READING_MEM into two separate steps so
contention at the requestToMemory queue won't block the TBE
initialization.

JIRA: https://gem5.atlassian.net/browse/GEM5-1195

Change-Id: Ifa0ee589bde67eb30e7c0b315ff41f22b61e8db7
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63675
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-09-28 18:56:04 +00:00
Tiago Mück
3871f57dc3 configs: set requestToMemory buffer size for CHI
Currently TBEs for write requests are deallocated when the request is
pushed to memory, so an unlimited requestToMemory buffers size allows
for an unlimited number of outstanding write requests.

Set the requestToMemory buffers size prevents this.
The buffer size should be greater than the enqueue latency to allow at
least one enqueue per cycle.

JIRA: https://gem5.atlassian.net/browse/GEM5-1195

Change-Id: I31829b6bbabd8b45e1142790038c27bd459fa709
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63674
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-09-28 18:56:04 +00:00
Tiago Mück
06a8a47322 configs: fix CHI mem buffers
Disabling randomization for the memory request and response buffers.
CHI requires that memory responses for the same address arrive in
the same order the request was sent.

Change-Id: Ia4236188679beaf2969978675414a870ccd9f94a
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63673
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-09-28 18:56:04 +00:00
Tiago Mück
ba3aa067a3 configs: CHI inc transitions_per_cycle
Previous limit may unintentionally throttle performance for controllers
with a large TBE table and high traffic.

Change-Id: I34d6f8727519b259bb3d4a80b1fff6c59197c508
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63672
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-09-28 18:56:04 +00:00