Commit Graph

15258 Commits

Author SHA1 Message Date
Nikos Nikoleris
91c0056481 arch-arm: Downgrade constexpr causing build errors to const
Change-Id: Idf5ae62603b6181d44aaaef91b774fa7b26eb718
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28167
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-30 09:14:42 +00:00
Gabe Black
41c88839a9 sim: Add an option to suppress the return value in invokeSimcall.
Sometimes when using the GuestABI mechanism, gem5 wants to know that a
function was called and with what arguments to do its own processing,
but doesn't want to return its own value since it will still let the
simulated system execute its own function. There are also situations
where gem5 wants to return a value, but not through the normal
mechanism. That happens when, for instance, a gem5 op is triggered by a
memory access, and that access is what should return the value, not a
particular fixed register.

This option is a template parameter rather than a function argument so
that if it's not going to be used, no "Return" type needs to be defined
since it's not present at all in the chain of functions invokeSimcall
expands to.

This will also make it easier to reuse generic ABIs in those situations
without having to make custom wrappers.

Change-Id: I969e78495c8f4e73f4de1a3dfb4d74c9b30f5af5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28288
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-30 08:47:33 +00:00
Gabe Black
4773c6faff misc: Use the protobuf version to choose between ByteSize(Long).
Older versions of protobuf are apparently still what's provided with
some current versions of some distributions. To avoid breaking the build
on those distributions and to avoid an annoying deprecation warning on
newer systems, check GOOGLE_PROTOBUF_VERSION to choose which to use.

According to the CHANGES.txt file here:

https://github.com/protocolbuffers/protobuf/blob/master/CHANGES.txt

The new ByteSizeLong function was introduced in version 3.1.0 in 2016.

Change-Id: I7f8eeda144bf9556d17d7a0a741996f3137b48b4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28287
Reviewed-by: Tommaso Marinelli  <tommarin@ucm.es>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 21:46:11 +00:00
Anouk Van Laer
cc2f48ccfc sim-power: Addition of PowerDomains
PowerDomains group multiple objects together to regulate their power
state. There are 2 types of objects in a PowerDomain: leaders and
followers. The power state of a PowerDomain is the most performant
power state of any of the leaders. The power state of the followers is
determined by the power state of the PowerDomain they belong to: they
need to be in a power state which is more or equally performant to the
power state of the PowerDomain.

Leaders can be ClockedObjects or other PowerDomains. Followers can
only be ClockedObjects. PowerDomains can be be nested but a
PowerDomain can only be a leader of another PowerDomain, NOT a
follower. PowerDomains are not present in the hierarchy by default,
the user needs to create and configure them in the configuration file.

The user can add an hierachy by setting the led_by parameter. gem5
will then create leaders and followers for each domain and calculate
the allowed power states for the domain.

Objects in a PowerDomain need to have at least the ON state in the
possible_states.

An example of a powerDomain config is:

pd = PowerDomain()
cpu0 = BaseCPU()
cpu1 = BaseCPU()
shared_cache = BaseCache()
cache.power_state.led_by = pd
pd.led_by = [cpu0, cpu1]

This will create a PowerDomain, where the CPUs determine their own
power states and the shared cache (via the PowerDomain) follows those
power states (when possible).

Change-Id: I4c4cd01f06d45476c6e0fb2afeb778613733e2ff
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28051
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 21:03:31 +00:00
Anouk Van Laer
4b2f2b5ced sim-power: Specify the states a PowerState object can be in
This commit adds the concept of possible power states to the
PowerState SimObject. This is a list of the power states a specific
object can be in. Before transitioning to a power state, a PowerState
object will first check if the requested power states is actually an
allowed state. The user can restricted the power states a
ClockedObject can go to during configuration. In addition, this change
sets the power states, a CPU can be in.

Change-Id: Ida414a87554a14f09767a272b54b5d19bfc8e911
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28050
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 21:03:31 +00:00
Anouk Van Laer
818961969a sim-power: Creation of PowerState class
This commit does not make any functional changes but just rearranges
the existing code with regard to the power states. Previously, all
code regarding power states was in the ClockedObjects. However, it
seems more logical and cleaner to move this code into a separate
class, called PowerState. The PowerState is a now SimObject. Every
ClockedObject has a PowerState but this patch also allows for objects
with PowerState which are not ClockedObjects.

Change-Id: Id2db86dc14f140dc9d0912a8a7de237b9df9120d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28049
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 21:03:31 +00:00
Nikos Nikoleris
84003b7cc7 configs: Change fs_power.py to use absolute paths for stats
fs_power.py is an example script that demonstrates how power models
can be used with gem5. Previously, the formulas used to calculate the
dynamic and static power of the cores and the L2 cache were using
stats in equations as determined by their path relative to the
SimObject where the power model is attached to or full paths. This CL
changes these formulas to refer to the stats only by their full paths.

Change-Id: I91ea16c88c6a884fce90fd4cd2dfabcba4a1326c
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27893
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 21:03:31 +00:00
Nikos Nikoleris
274c0e0ae1 sim-power: Fix the way the power model accesses stats
With the introduction of StatGroups the organization of stats has
changed and the power modeling framework has been broken. This CL uses
the new function Stats::resolve to retrieve pointers to the necesary
stats and use them in the power estimation formulas.

Change-Id: Iedaa97eeddf51f7a0a1f222918715da309943be3
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27892
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 21:02:32 +00:00
Nikos Nikoleris
1afe851d15 base, python, sim: Add support for resoving a stat using its name
This CL adds resolve, a function in the Stats namespace that allows
access to a stat as specified by its name.

Change-Id: I4fa8bed394b4cb35d9c6cf5d8db062b8d6bb9ca5
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27891
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 21:02:32 +00:00
Nikos Nikoleris
8cac579e5e base: Add support for resolving stats within groups by name
This change adds a member function to the Group class that returns a
stat given its name. The function will go through all stats in the
group and its subgroups and will return the stat that matches the
name. For example, if g is the Group system.bigCluster.cpus then a
call to

p = g.resolveStat("ipc")

will return a pointer to the stat system.bigCluster.cpus.ipc.

Change-Id: I5af8401b38b41aee611728f6d1a595f99d22d9de
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27890
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 21:02:32 +00:00
Nikos Nikoleris
ee5f32a382 sim: Add function that returns all variables in a MathExpr
This changes adds support for retrieving all variables in a math
expression. The added function can be called in all valid expressions
and will return the variables in a vector of strings.

Change-Id: I086ba04aa1f798400c97a0b6bf982018a2457c64
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27889
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 21:02:32 +00:00
Ciro Santilli
741ac4c6cb tests: create tests for various traffic generators on NULL
New tests were added for:

- garnet_synth_traffic.py
- ruby_random_test.py
- ruby_direct_test.py

These tests are factored out with the tests for:

- memcheck.py
- ruby_mem_test.py

Each new test was calibrated to last about 5 seconds on a Lenovo ThinkPad
P51.

Change-Id: Ie13d3963e1163cffae5dce329b623fbebbf2b983
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26808
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 18:33:50 +00:00
Ciro Santilli
4e1117f2ba tests: fix the memcheck test
The file was raising due to the undefined constant `verifiers`, leading
the test to be ignored.

./main.py list -v

would show this as:

```
Traceback (most recent call last):
  File "/gem5/tests/../ext/testlib/loader.py", line 239, in load_file
    execfile(path, newdict, newdict)
  File "/gem5/tests/gem5/memcheck/test_memcheck.py", line 32, in <module>
    verifiers=verifiers,
NameError: name 'verifiers' is not defined

Exception thrown while loading "/gem5/tests/gem5/memcheck/test_memcheck.py"
Ignoring all tests in this file.
```

The test has been modified to have an empty verifiers list, which should
still catch bugs since src/mem/mem_checker.cc has several asserts already
which would be caught by the test system due to the exit status.

Also make the following changes to the test:

-   move it to tests/gem5/memory/test.py with other memory tests.

    This makes it easier to see all the tests in the source in one go, and
    might make it easier to factor certain memory things out later on.

-   reduce --maxtick to a value that finishes in 7 seconds on a Lenovo
    ThinkPad P51.

    The previous value would take 50x longer, which feels too long for a
    single test.

-   enable --prefetchers to also stress a prefetcher in the test

Change-Id: I58bd598b1142f349d25fa4fa4a8e41529e61a9ee
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26807
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 18:33:50 +00:00
Ciro Santilli
b4ab0c168c mem: make MemTest panic on a packet error
Before this change, running:

./build/NULL/gem5.opt configs/example/ruby_mem_test.py -m 20000000 \
  --functional 10

would only print warning for memory errors such as:

warn: Read access failed at 0x107a00

and there was no way to make the simulation fail.

This commit makes those warnings into errors such as:

panic: Read access failed at 0x107a00

unless --suppress-func-errors is given.

This will be used to automate MemTest testing in later commits.

Change-Id: I1840c1ed1853f1a71ec73bd50cadaac095794f91
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26804
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 18:33:50 +00:00
Ciro Santilli
4f16a4e65a configs: remove exec of Options.py from ruby_mem_test.py
The removed exec statement does not appear to be needed however,
since Options is already imported above with:

from common import Options

Change-Id: I934a65d21fa5099a786224a5476d609e4d707205
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26803
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 18:33:50 +00:00
Nils Asmussen
689025dbef arch-riscv: report that we don't have debugging support.
According to the debugging spec (page 47), a debugger can test which
triggers are enabled by writing 0 to TSELECT and reading it back. If a
different value is read, the trigger is not supported.

Therefore, we currently always set a different value to indicate that
we do not support any triggers.

Change-Id: If222e913c4517adb2da4f6f0ffeedb4e4808a586
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25659
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
9c6920d6f7 arch-riscv: respect IALIGN, influenced by toggling 'c' extension.
According to the privileged ISA spec, SEPC[0]/MEPC[0] reads always 0
and SEPC[1]/MEPC[1] reads 0 if the compressed extension is disabled.

Additionally, the compressed extension can only be disabled if the next
instruction is 4-byte aligned.

Change-Id: I590c05e4000b59a5ba283f47933f7a92959d8e38
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25658
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
39f1ff79ec arch-riscv: let FPU instructions fault if status.FS = off.
These checks are required for some tests in the RISC-V test suite.
However, actually we also need to set the INITIAL/CLEAN/DIRTY flags
accordingly, which is not done yet.

Change-Id: If5d6ac22069b51a57b6353cd6d45b77ee51a4d55
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25657
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
3bb461072c arch-riscv: make uret,sret,mret SerializeAfter,NonSpeculative.
These instructions potentially change the privilege level, upon which
the execution of other instructions depends. For that reason, we need to
make *ret SerializeAfter and we also don't want to execute them
speculatively.

Change-Id: If3b5ba6ec3b4102d53c51cf723eba5d5da3eaa2f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25656
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
d3f3a84cfb arch-riscv: make accesses to CSRs SerializeAfter.
According to page 57 in the RISC-V manual, CSR accesses "need to be
performed in program order with respect to those instructions whose
execution behavior is affected by the state of the accessed CSR".

Thus, we need to make them SerializeAfter to ensure that the following
instructions are executed with the potential changes to the CSR. In
theory, we could be smarter here by only considering write accesses to
CSRs and considering the following instructions, but for now we simply
serialize for every CSR access.

Change-Id: I69391fccaec31c34d944c55bac2f04d37947ebfe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25655
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
33d651b254 arch-riscv: fault according to status.{TVM,TSK,TW}.
Change-Id: I38dddadb3373d2156b8fc57eabff861a062021cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25654
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
c11aed1931 arch-riscv: added dummy implementation of wfi instruction.
Change-Id: I7ca86f57c7d794bf544e34e747875049a3f29d6a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25653
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
55e7d3e5b6 arch-riscv: fault on mstatus accesses from lower privilege modes.
Change-Id: If2e35445770eaa52f5af6f9ef02fb5e11bef8da4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25652
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
aaf294af5c arch-riscv: ignore writes to SXL/UXL fields in status register.
We currently only support SXL=UXL=2 (64 bit). These fields are WARL,
so that we have to make sure that no other value can be set.

Change-Id: I62ddc7d68b8c31ca655ba1ccee7a294912f46b09
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25651
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
54d769308d arch-riscv: added (un)serialization of miscRegFile.
Change-Id: I127dbf4a6bb4a144eaee05a87495830dce82eb58
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25650
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
6d3bf34a2a arch-riscv: show names of MiscRegs on accesses.
Printing the number of the MiscRegs makes it hard to debug problems.
Therefore, this commit adds a name table and prints the name of the
register.

Change-Id: Icd53d5524a5d5daf3e50f253cdda56341663f26e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25649
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
b295e0f3a8 arch-riscv: fixed read of {M,S,U}TVEC.
As stated in 4.1.4 of the privileged ISA manual, the BASE field in the
STVEC register contains the bits [SXLEN-1:2] of the base address, not
the base address shifted left by 2.

Change-Id: I799ec0dc1cbd7b271b91b53adb033a5d1ca3306f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25648
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
4056876301 configs: added bare metal FS support for RISC-V.
Change-Id: Id412186d868680b9af97503a5337fc394fd84f68
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26989
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
2403018690 cpu,configs: let RISC-V use the PT walker cache.
Change-Id: I19b1dd9e3c55c433c897988d36e6715017273c66
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26988
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
a4bd492158 arch-riscv: fixed formatting.
Change-Id: I134993a4aced07e75bf62fec56081b0f9d8fc18c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26986
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
7d0c6eae62 arch-riscv: implement RemoteGDB::acc for FS mode.
Change-Id: I78b37db43fbb16d4dafa74294117e8beba62f903
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26985
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
fa6de5d5fd arch-riscv: implement sfence.vma to flush TLBs.
Change-Id: I424123d3c94c9673269f922cd6755f0bbf5b6cc0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26984
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
476d96cb53 arch-riscv: make sure only supported modes can be set in SATP.
Change-Id: I37c67e491d64bf03d1125e23db28611fa0b16038
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26983
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
2527c6c9da arch-riscv: added TLB and page table walker.
That is, RISC-V has now a TLB and page table walker for Sv39 paging
according to the privileged ISA 1.11.

Both the TLB and PT walker are based on x86 (the code duplication of the
page table walkers will be reduced by a separate commit).

Change-Id: I5e29683bdd40c0d32c06e4d75a8382bf313f2086
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25647
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 11:41:55 +00:00
Gabe Black
f8926cd56f arm: Add a unit test for some aspects of the aapcs64 ABI.
This test covers the templates which attempt to classify types, but not the
actual gathering of arguments of distribution of return values. As before, we
can't really use standard C++ to accurately test for HFAs and HVAs, so we stick
with approximating them by detecting arrays of the right types.

For example, I think technically we should also accept a struct with only 4
float members, but c++ templates aren't able to match against types in that way
as far as I know.

Change-Id: I1d7756a964a86c0c5ea13e068a5fc74603e14e30
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28268
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 11:30:58 +00:00
Gabe Black
0c7f131ed2 arm: Fix some bugs in the aapcs64 implementation.
The templates which checked for short vectors, and our approximation of
HFA, HVA and HXA types were not correct. This change actually simplifies
them along with getting them to produce correct results. In the case of
HXA, there was a logic bug where an && was used where an || was
intended.

There may still be bugs in the actual collection of arguments and
setting of return values since those aspects are harder to test.

Change-Id: Ice3177205a98c678ecb43ba600813b3909c44e6b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28267
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-28 21:54:04 +00:00
Matthew Poremba
fa5bf60c78 configs: Add missing requestToMemory MessageBuffers
In commit 53b6e21 two protocol config files were missed when the new
requestToMemory MessageBuffers were added. This fixes the issue such
that all Ruby protocols are working again.

Change-Id: Iaa04c792eaf6d659ba13c19f003e7e31b71ffdb4
JIRA: https://gem5.atlassian.net/browse/GEM5-468
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28187
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-28 14:41:28 +00:00
Jordi Vaquero
3afcfe3b53 arch-arm: Fix clasta/b and lasta/b simd&fp instructions
The simd&fp version of this instructions required zeroing the result
vector except for the first element, that contains the result.

Change-Id: I231ad3c44d89f34acae26d299ab676e2ed09acdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28247
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-28 12:56:29 +00:00
Giacomo Travaglini
eabd4f3a9b configs: Do not require args.kernel to be set in baremetal.py
This is allowing to us run baremetal.py with the --dtb-gen option
without needing to specify a --kernel argument

Change-Id: I98f1bc865d2f4e2230b1a85453efe83d95ec8a55
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28148
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-28 09:51:36 +00:00
Giacomo Travaglini
a0038f7aec sim, arch-arm: Restore capability of running without a kernel
The following patch:

https://gem5-review.googlesource.com/c/public/gem5/+/24283

Removed the capability of starting a gem5 simulation without
a kernel object. This patch is restoring it

Change-Id: I6d751bac386cbb250b3593bb12463140dc964ab3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28147
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-28 09:51:36 +00:00
Gabe Black
26454e8072 util: Add an abstraction layer for call types in the m5 utility.
These make the calling code in m5.c a little bit more generic. Each call
type will have a function to check the arguments and see if that type is
being requested and/or has any additional options set in the arguments.
If so, those are processed, and argc and argv are adjusted.

Then another function returns the appropriate dispatch table to use for
that invocation scheme. This is behind a function instead of, for
instance, a global variable because it gives the call type a little bit
more control over what's happening, for instance if it would use
different implementations in slightly different circumstances.

Change-Id: I661cf202ec657466496767cbdf331fe27995ab26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27241
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-04-28 01:07:43 +00:00
Gabe Black
1708a71e5b util: Add a helpful macro for merging two tokens to m5ops.h.
I've needed this type of macro often when writing code which uses the
M5OP_FOREACH macro, and so rather than re-write it each time, lets just
put a version here. This is such a common type of macro to need that
you'd think it would be part of a standard header somewhere, but to my
knowledge it isn't.

Change-Id: I0df0d9d2fd7ce1b9e6c355d6e4db197ccfff7c35
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27239
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-04-28 01:07:43 +00:00
Gabe Black
6072c1ad28 util: Use a dispatch table to call ops in the m5 utility.
This way different implementations can be substituted in depending on
how the low level ops should actually be triggered (inst, addr,
semihosting, (etc?)).

Change-Id: I7c6eab7d87cc973d0bc9c1889037a0f89ce057e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27238
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-04-28 01:07:43 +00:00
Gabe Black
3e88a4aa01 misc,util: Remove explicit ';'s from M5OP_FOREACH.
It may be the case that each item M5OP_FOREACH iterates over should end
in a ',' and not a ';', for instance when putting each item into an
array or initializing a structure. If the caller still wants a ';', they
can add it into the definition of the M5OP macro.

Change-Id: Idd6538b0aad27df39658c3f749c6ff5e4fe55e6d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27237
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-28 01:07:43 +00:00
Gabe Black
3b6f2fc14f misc: Add the SE mode m5 ops to m5ops.h.
These shouldn't be called in fs mode through the m5 utility and
probably shouldn't be called directly either, but this makes them
consistent with the other functions which are mentioned in
asm/generic/m5ops.h.

Change-Id: I80df8b4d507350bc6d2763e770e38e0370931632
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27236
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-28 01:07:43 +00:00
Gabe Black
ac858434c6 sim,misc: Rename M5OP_ANNOTATE to M5OP_RESERVED1.
The M5OP_ANNOTATE constant is unused and treated as a reserved op in
gem5. Rename it to make it official and consistent.

Change-Id: Id5fe6a3aa402a2e0cd187503abff9b09e81b3724
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27235
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-04-28 01:07:43 +00:00
Gabe Black
e81e48c16b misc: Tidy up M5OP_FOREACH and the constants in m5ops.h.
Make sure all the operations that have constants (and aren't deprecated
or reserved) and present in M5OP_FOREACH in order of their constants.
Also move M5OP_ANNOTATE up so that all the constants are also in order.

Change-Id: I8d9f69b020aeb39311a24606a286a76de10a51cc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27234
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-28 01:07:43 +00:00
Gabe Black
4af8df1ecd util: Delete the execfile m5 utility command.
This command was just a thin wrapper around the readfile command, and
can be easily duplicated by piping the output of that command to
/tmp/execfile and then running it.

Change-Id: Ib77166ee9f07571d57e4d21e9615def55e5391a8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27233
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-04-28 01:07:43 +00:00
Gabe Black
5e888d44fe util: Eliminate the sw99param m5 utility command.
This is a small additional layer on top of the initparam command and
just breaks the returned value into 12 bit chunks. It presumes that
there is some particular meaning to the default initparam value which
may or may not be true. It's not entirely clear what the 12 bit chunks
that this command returns are actually good for, and it's been around
long enough that there isn't really any good documentation about what
it's intended purpose was.

Change-Id: I21af0e0cf7501f47026a6dd31920d46cfccff167
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27232
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-04-28 01:07:43 +00:00
Gabe Black
21eba2a6fa util: Improve the usage text of the m5 utility.
Make sure there *is* help text for every command, alphabetize the
commands, explain all the arguments and what the command as a whole
does.

Change-Id: Icf74f8c638545c8658c99169dce728f7b1127806
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27231
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-04-28 01:07:43 +00:00