arch-riscv: report that we don't have debugging support.

According to the debugging spec (page 47), a debugger can test which
triggers are enabled by writing 0 to TSELECT and reading it back. If a
different value is read, the trigger is not supported.

Therefore, we currently always set a different value to indicate that
we do not support any triggers.

Change-Id: If222e913c4517adb2da4f6f0ffeedb4e4808a586
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25659
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

src/arch/riscv/isa.cc

@@ -200,6 +200,9 @@ void ISA::clear()
                                   (1ULL << FS_OFFSET);
     miscRegFile[MISCREG_MCOUNTEREN] = 0x7;
     miscRegFile[MISCREG_SCOUNTEREN] = 0x7;
+    // don't set it to zero; software may try to determine the supported
+    // triggers, starting at zero. simply set a different value here.
+    miscRegFile[MISCREG_TSELECT] = 1;
 }
 
 bool
@@ -359,6 +362,13 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
                 setMiscRegNoEffect(misc_reg, new_val);
             }
             break;
+          case MISCREG_TSELECT:
+            {
+                // we don't support debugging, so always set a different value
+                // than written
+                setMiscRegNoEffect(misc_reg, val + 1);
+            }
+            break;
           case MISCREG_ISA:
             {
                 auto cur_val = readMiscRegNoEffect(misc_reg);