Commit Graph

572 Commits

Author SHA1 Message Date
Gabe Black
e6c0ba97db scons: Put all config variables in an env['CONF'] sub-dict.
This makes what are configuration and what are internal SCons variables
explicit and separate, and makes it unnecessary to call out what
variables to export to C++.

These variables will also be plumbed into and out of kconfiglib in later
changes.

Change-Id: Iaf5e098d7404af06285c421dbdf8ef4171b3f001
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56892
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-28 20:31:21 +00:00
Giacomo Travaglini
4bbcd98598 dev-arm: Remove unused ELIsInHost redirection for CNTKCTL_EL1
The redirection to CNTHCTL_EL2 is already handled in
ISA::redirectRegVHE

Change-Id: Ia3290c5bdb75c6e45f08a47c1b75881bc52add5f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58115
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-25 09:51:56 +00:00
Giacomo Travaglini
9e65dcaeec arch-arm, dev-arm: Implement EL2 Secure Virtual Timer
Change-Id: Ie4d4ff27b6375593ca4a6f6ae2a5e428ada943be
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58112
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-25 09:51:37 +00:00
Giacomo Travaglini
e6797303c4 arch-arm, dev-arm: Implement EL2 Secure Physical Timer
Change-Id: I052f72695e670fad492079ab912268d05c797100
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58111
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-25 09:50:15 +00:00
Giacomo Travaglini
f1dce36f97 arch-arm, dev-arm: Implement EL2 Non-secure Virtual Timer
Change-Id: I0cc499e1309c35d946c5b9231846263f97bfa2b0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58110
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-24 16:04:58 +00:00
Giacomo Travaglini
cfc570dd1c dev-arm: Rename GenericTimer interrupts
The Arm Architecture Reference Manual has moved from
"Armv7-oriented" names for generic timer interrupts to
names more consistent with Armv8 (Exception Levels based).

We are therefore renaming those interrupts as follows:

int_phys_s -> int_el3_phys
int_phys_ns -> int_el1_phys
int_virt -> int_el1_virt
int_hyp -> int_el2_ns_phys

Change-Id: Id6e34a0e4311953938b25bca168a34357e3c8643
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58109
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-24 16:04:58 +00:00
Giacomo Travaglini
9e62fcf2bd dev-arm: Add a KVM Gicv3 model to VExpress_GEM5_Foundation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Ic5cfeeec59630253acb3ccc451553eb4eb7907e2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55615
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-10 08:59:25 +00:00
Giacomo Travaglini
45a07f1eeb dev-arm: Gicv3 implementation of the Gicv3Registers interface
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Iba23604cc6f7d5a1de91c287b4546154fcb20535
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55612
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-03 16:36:29 +00:00
Giacomo Travaglini
342ad01168 dev-arm: Use ArmISA::getAffinity in GICv3 redistributor
The GICv3 redistributor was reading the MPIDR value and manually
extracting the affinity numbers from it. This is not necessary as there
is already a getAffinity helper function

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I6ef150937b51bb065575ed2f432f4f5f0bc38b07
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55704
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-03 16:36:11 +00:00
Giacomo Travaglini
c28feb20f2 arch-arm: Templatize MuxingKvmGic to support flexible hierarchy
By templatizing the MuxingKvmGic we decouple it from the GicV2
class, unlocking non GICv2 (e.g. GICv3) KVM and guest implementations

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I26838903fa7c9f8b9de40678021329cb3390cc74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55611
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-03 16:36:11 +00:00
Giacomo Travaglini
0865772b28 arch-arm, dev-arm: Remove generic BaseGicRegisters interface
The GICv3 register interface is different from the GICv2 one: from
the presence of redistributor registers up to the system register
implementation of the cpu-interface

We therefore make the current BaseGicRegisters interface GICv2 specific.
We will define a different Gic3Registers interface for GICv3 state
transfer

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I42f15f48cab6e26aaf519e13c2ce70f661801117
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55703
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-03 16:36:11 +00:00
Gabe Black
ac5f79af28 cpu-kvm: Move the validKvmEnvironment method into KvmVM.
This makes the generic System class consistent whether you have KVM
enabled or not.

Change-Id: Ie6928961200943d1d4e3bd129a4e4269e9f12950
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56263
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-02 01:45:58 +00:00
Giacomo Travaglini
0eba590d01 arch-arm: De-virtualize updateIntState
De-virtualize updateIntState and replace it with the new blockIntUpdate
in the MuxingKvmGic class.

The monolithic updateIntState is GicV2 specific and it is not compatible
with the more complex IRQ update logic in GicV3, which is delegating the
update to the destributor/redistributor/cpuinterface classes

Rather than stubbing the update function the MuxingKvmGic class, we
override the blockIntUpdate to return true in case a KVM gic is in use.
This is loosening the interface, not restricting any GIC implementation
to a specific update interface/design

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Ib8d9c99b720c779a2255ac47ee2a655ff281581d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55609
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-01 10:42:57 +00:00
Giacomo Travaglini
4f833b539a arch-arm: Avoid Gic write side effect with blockIntUpdate
When trasferring the state between two GICs (essentially
writing architectural registers) an interrupt might be posted
by the model. We don't want this to happen as the GIC might
be in an inconsistent state. We therefore disable side effects
by relying on the blockIntUpdate method.

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I0e5a86551705254ebacb81b7b358470faad0230c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55608
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-01 10:42:57 +00:00
Giacomo Travaglini
05d733d0cd arch-arm: Generalize KVM Gic state copying logic
By moving the Gic state copying logic from the MuxingKvmGic to the
BaseGic we allow different Gic releases (e.g Gicv2, Gicv3) to override
the implementation accoding to their personal architectural state

It is also possible to use the same logic outside of the KVM
context

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I88d6fca69a9b61a889c5ec53221404b8396cc12d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55607
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-01 10:42:57 +00:00
Yu-hsin Wang
a8c85b1c40 dev-arm: Mask el2_watchdog in VExpressFastmodel platform
el2_watchdog depends on SystemCounter. However, we have mask
system_counter in the platform. We should also mask the el2_watchdog
accordingly.

Change-Id: I2ed774549272438d654e0573ffe9f482a6659d37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55306
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-01-12 08:07:43 +00:00
Yu-hsin Wang
cd9fc30d92 dev-arm: Add missing sim_objects of VExpressFastmodel
Change-Id: Ic6a9e5f1381c6c6412faa6d19f1448ca0e08b1e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55304
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-01-12 01:25:07 +00:00
Alistair Delva
75cd1ff764 dev-arm: Add RealView support for initrd/initramfs
Update the RealView bootloader simulator to set up the initrd_addr. The
load address is derived from the dtb_addr plus the maximum allowable DTB
blob size.

Change-Id: I2eaeb1ade38d24ad8e02230cc99d12873c2f56f9
Signed-off-by: Alistair Delva <adelva@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54185
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-01-05 23:07:07 +00:00
Gabe Black
1c233ee9d2 scons: Add sim_object and enums arguments to SimObject().
This will explicitly declare what SimObject and Enum types need to be set
up in C++, which will make importing all the SimObject modules during
the setup phase of SCons uneccessary.

Change-Id: Id2d7603daf33b236ceaa0789e2f089f589d34e62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49406
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-08 08:01:23 +00:00
Giacomo Travaglini
664fdd747a arch-arm, dev-arm: Add currEL function to the ISA class
This utility is strictly ISA related. We are still keeping the
version accepting the TC as an argument; this is just
wrapping the ISA call.

In this way we are simplifying life for ISA devices, which have
a reference to the ISA object rather than a reference to the TC

Change-Id: Icb286d174538b50962d31aa3f6e836b3c791dc1c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53624
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-07 18:58:49 +00:00
Giacomo Travaglini
adaab745a3 arch-arm, dev-arm: Move inSecureState helper to ISA class
The helper function should be really part of the Arm ISA class

Change-Id: Ida0393a12426c8973a9b8171ec2922c2dcec9f5a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53268
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-07 18:58:49 +00:00
Gabe Black
2805f3dee1 misc: Stop including arch/pcstate.hh.
Change-Id: Ic9ea62ae9c59fd838175fd6af4c075101d46a0b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52067
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-11-30 23:30:06 +00:00
Gabe Black
636783856f dev-arm: Ensure all fields of GicV2 are initialized.
The constructor tried to initialize all values, but in particular missed
intGroup, and may have missed other values as well.

Change-Id: Ibcd610e40259e46e3cde9b76c7f9ddc816832dfd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52406
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-09 21:40:58 +00:00
Gabe Black
ba5f68db3d misc: Use python 3's argumentless super().
When calling a method in a superclass, you can/should use the super()
method to get a reference to that class. The python 2 version of that
method takes two parameters, the current class name, and the "self"
instance. The python 3 version takes no arguments. This is better for a
at least three reasons.

First, this version is less verbose because you don't have to specify
any arguments.

Second, you don't have to remember which argument goes where (I always
have to look it up), and you can't accidentally use the wrong class
name, or forget to update it if you copy code from a different class.

Third, this version will work correctly if you use a class decorator.
I don't know exactly how the mechanics of this work, but it is referred
to in a comment on this stackoverflow question:

https://stackoverflow.com/questions/681953/how-to-decorate-a-class

Change-Id: I427737c8f767e80da86cd245642e3b057121bc3b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52224
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-09 13:04:44 +00:00
Gabe Black
314dae4b86 dev-arm: Set cntkctl and cnthctl in the CoreTimers constructor.
The cntkctl and cnthctl registers were not initialized by the CoreTimers
constructor which upset valgrind when they were later used by
handleStream.

Change-Id: Iaedbb2d957aeb428fd563be2e24ccb8d2cf57f26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52403
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-06 08:39:46 +00:00
Gabe Black
6107dd11c6 misc: Remove include of arch/page_size.hh, and fix up includes.
Remove the only remaining use of arch/page_size.hh, and fix up a couple
files which were using one of the constants defined in a specific arch
version of it without including the file they needed directly.

Change-Id: I6da5638ca10c788bd42197f4f5180e6b66f7b87f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50765
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-10-22 21:43:02 +00:00
Giacomo Travaglini
847f642f0e arch-arm: Add TxSZ to PageTableOps::index
This patch is adding the input address (IA) size (TSZ) to the
index method, as it is limiting the number of bits used to
determine the descriptor index from the input address

Change-Id: Ibc8f9ce94ea0ce06093bd90546ca1a906518b700
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51807
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-21 08:06:44 +00:00
Giacomo Travaglini
1b6c050ebf arch-arm, dev-arm: Use PageTableOps in Arm TableWalker
As the VMSA is shared between the CPU MMU and the SMMU, we move the
PageTableOps data structures to the arch/arm/pagetable.hh/cc sources.

Both MMUs will make use of them

Change-Id: I3a1113f6ef56f8d879aff2df50a01037baca82ff
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51672
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-21 08:06:44 +00:00
Gabe Black
73025695c7 scons: Use tags to gate ISA files and not env['TARGET_ISA'].
Change-Id: Ib81a4c570fbb050fa7d82919edacfed004c6800e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50336
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2021-10-19 20:41:03 +00:00
Quentin Forcioli
9854685277 dev-arm: Added trusted DRAM to vexpress Realview
Added the 32MB of trusted DRAM to the VExpress_GEM5_Base Realview.
This trusted DRAM is however not protected against unsecure access.

This commit is part of series of commit to enable booting OPTEE on gem5.

Change-Id: Icbbaec8488dd72e1cbe70015a7f7904de35b38bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49989
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-12 09:29:50 +00:00
Giacomo Travaglini
152760ee51 arch-arm: Define an ArmRelease class to handle ISA extensions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I3240853bd2123a6f24b2bb64c90ad457696f0d93
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51010
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-09-29 22:16:03 +00:00
Giacomo Travaglini
377155c10b arch-arm: Syncronize GIC CPU interface when changing EL
From the GIC architecture specification (ihi0069) [1]

"The assertion and de-assertion of IRQs and FIQs are affected by the
current Exception level and Security state of the PE. As part of the
Context Synchronization that occurs as the result of taking or returning
from an exception, the CPU interface ensures that IRQ and FIQ are both
appropriately asserted or deasserted for the Exception level and
Security state that the PE is entering."

Kudos to Quentin Forcioli for finding the bug

[1]: https://developer.arm.com/documentation/ihi0069/latest

Change-Id: I10444a3aad5c06aabc13e1cbd70a32192531a31d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50508
Reviewed-by: Quentin Forcioli <quentin.forcioli@telecom-paris.fr>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-09-20 09:03:19 +00:00
Gabe Black
00876fff20 misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].
The [[maybe_unused]] attribute is now standard, so we can use that
directly without hiding it behind a macro.

Change-Id: If24ffd7e50bdb503cb3e6ea61f226ea794e84b8f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48511
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-29 10:17:51 +00:00
Gabe Black
cb266a099f misc: Replace GEM5_FALLTHROUGH with [[fallthrough]].
Now that the [[fallthrough]] attribute is standard (as of c++-17), we
can use it directly instead of hiding it behind a macro.

Change-Id: I4d11e35b619532b1a3fd8d042265e18c80d86f9b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48505
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-24 21:57:04 +00:00
Gabe Black
d58b4f004e misc: Remove typedef (struct|enum) Foo in cpp files.
In C, to refer to a type without a struct or enum tag on the type, you
need to typedef it like this:

typedef struct
{
} Foo;

Foo foo;

In C++, this is unnecessary:

struct Foo
{
};

Foo foo;

Remove all of the first form in C++ files and replace them with the
second form.

Change-Id: I37cc0d63b2777466dc6cc51eb5a3201de2e2cf43
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46199
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-07 08:35:12 +00:00
Daniel R. Carvalho
4b2118ed4b misc: Remove sim/cur_tick dependency from sim/core.hh
Remove this unnecessary dependency. Fixed all incorrect
includes of sim/core.hh.

Change-Id: I3ae282dbaeb45fbf4630237a3ab9b1a593ffbe0c
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43592
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-06 09:59:11 +00:00
Daniel R. Carvalho
974a47dfb9 misc: Adopt the gem5 namespace
Apply the gem5 namespace to the codebase.

Some anonymous namespaces could theoretically be removed,
but since this change's main goal was to keep conflicts
at a minimum, it was decided not to modify much the
general shape of the files.

A few missing comments of the form "// namespace X" that
occurred before the newly added "} // namespace gem5"
have been added for consistency.

std out should not be included in the gem5 namespace, so
they weren't.

ProtoMessage has not been included in the gem5 namespace,
since I'm not familiar with how proto works.

Regarding the SystemC files, although they belong to gem5,
they actually perform integration between gem5 and SystemC;
therefore, it deserved its own separate namespace.

Files that are automatically generated have been included
in the gem5 namespace.

The .isa files currently are limited to a single namespace.
This limitation should be later removed to make it easier
to accomodate a better API.

Regarding the files in util, gem5:: was prepended where
suitable. Notice that this patch was tested as much as
possible given that most of these were already not
previously compiling.

Change-Id: Ia53d404ec79c46edaa98f654e23bc3b0e179fe2d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46323
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-01 19:08:24 +00:00
Daniel R. Carvalho
223b0b388e mem: Conclude deprecation of MemObject
This has been marked as deprecated a few versions ago,
so it is safe to conclude its deprecation process.

Change-Id: I20d37700c97264080a7b19cf0cf9ccf8a5b65c32
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47299
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-28 20:25:07 +00:00
Yu-hsin Wang
3aa64284b1 dev-arm: add ArmSigInterruptPin
ArmSigInterruptPin helps connecting ArmInterruptPin with general
interrupt pin.

Change-Id: I4235fa0714054079a111163caca8dd3985999095
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45266
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-02 00:19:51 +00:00
Daniel R. Carvalho
98ac080ec4 base-stats,misc: Rename Stats namespace as statistics
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Stats became ::statistics.

"statistics" was chosen over "stats" to avoid generating
conflicts with the already existing variables (there are
way too many "stats" in the codebase), which would make
this patch even more disturbing for the users.

Change-Id: If877b12d7dac356f86e3b3d941bf7558a4fd8719
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45421
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-29 11:13:49 +00:00
Daniel R. Carvalho
a658ea043f base,dev,mem-ruby: Rename m5 namespace as gem5
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::m5 became ::gem5.

Change-Id: I250b4354113fcd6005dc4144ae378552cb8f6717
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45437
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-05-29 11:13:49 +00:00
Daniel R. Carvalho
4dd099ba3d misc: Rename Enums namespace as enums
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Enums became ::enums.

Change-Id: I39b5fb48817ad16abbac92f6254284b37fc90c40
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45420
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-29 11:13:49 +00:00
Daniel R. Carvalho
e291376f07 cpu,mem: Rename ContextSwitchTaskId namespace
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::ContextSwitchTaskId becomes ::context_switch_task_id.

Change-Id: If3884a5da7afe6144954d556b3b54f659bb7afb5
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45411
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-05-29 11:13:49 +00:00
Daniel R. Carvalho
71460cb13e sim,misc: Rename Int namespace as as_int
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

sim_clock::Int became sim_clock::as_int.

"as_int" was chosen because "int" is a reserved
keyword, and this namespace acts as a selector of
how to read the internal variables.

Another possibility to resolve this would be to
remove the namespaces "Float" and "Int" and use
unions instead.

Change-Id: I65f47608d2212424bed1731c7f53d242d5a7d89a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45436
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-05-26 23:08:21 +00:00
Daniel R. Carvalho
c487767cff sim,misc: Rename Float namespace as as_float
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

sim_clock::Float became sim_clock::as_float.

"as_float" was chosen because "float" is a reserved
keywords, and this namespace acts as a selector of
how to read the internal variables. Another
possibility to resolve this would be to remove the
namespaces "Float" and "Int" and use unions instead.

Change-Id: I7b3d9c6e9ab547493d5596c7eda080a25509a730
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45435
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-05-26 23:08:21 +00:00
Daniel R. Carvalho
0967a43c10 misc: Rename SimClock namespace as sim_clock
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::SimClock became ::sim_clock.

Change-Id: I25b8cfc93f283081bc2add9fdef6fec7d7ff3846
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45402
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-05-26 22:30:33 +00:00
Daniel R. Carvalho
3016478068 base-stats: Rename Units namespace as units
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

Stats::Units became Stats::units.

Change-Id: I9ce855b291db122d952098a090a2984b42152850
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45415
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-05-26 22:30:33 +00:00
Daniel R. Carvalho
fd660886c7 dev: Put PS2 classes in the ps2 namespace
These classes belong in the ps2 namespace. Use this
opportunity to rename PS2Device as ps2::Device, and
PS2TouchKit as ps2::TouchKit.

Unfortunately, since the ps2::Mouse and ps2::Keyboard
namespaces are being deprecated, these names cannot be
used as of now to rename PS2Mouse and PS2Keyboard.

Change-Id: I9a57b87053a6a0acb380a919e09ab427fdb8eca4
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45395
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-05-25 09:22:17 +00:00
Daniel R. Carvalho
78915f1895 dev-arm: Rename SCMI namespace as scmi
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::SCMI became ::scmi.

Change-Id: I68f729124079ecce02120577d2b89b25f10bde4a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45392
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-05-21 10:05:09 +00:00
Daniel R. Carvalho
fef8e578bf dev: Rename ps2 variables as ps2Device
Pave the way for a ps2 namespace.

Change-Id: I61fa33c57aee3e7c6df02a364420e4f83901f60b
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45389
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-05-21 10:05:09 +00:00