This reimplements the previously reverted change: Always generate default
create() methods.
The pybind code should only be generated when python is enabled. This
change passes whether python is enabled into the SimObject code creation
method. Then, the params code is optionally included.
Note: Due to some problems in GCC's linker (or something else...) we
need to have a single file with all of the generated code for the
SimObject.
Change-Id: I0f93b3d787d47f26db2de6c4447730f7df87a0dc
Issue-on: https://gem5.atlassian.net/browse/GEM5-1003
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46820
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Update in a pmp addr register can have effect on other
pmp rules, for example if TOR mode is used.
According to specs, update in a pmp entry is made using
an update to a pmpaddr reg, followed by an update to pmpcfg
reg which should be followed by sfence.vma. Currently,
in gem5 update in cfg register (combination of 8 pmpcfg
regs.), which should happen after a pmpaddr reg. update,
leads to an update in all pmp rules. However, there seems to
be a case where we receive an interrupt right before execution
of an instruction to update cfg register, which leads to unindented
side-effects of S mode addresses falsely falling into a wrong
pmp region. Updating pmp rules right after pmpaddr update, might
be redundant, but should not break anything otherwise.
Change-Id: I3776ee6ba40e1249c98d11076a2d176de40a957e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47059
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Sub-groups should not contain empty names. To make sure
that is the case, generate tokens even if the string is
empty.
Before the name 'group1..group2' would generate 2 tokens:
'group1' and 'group2'. As such, validateStatName would
not be able to detect it was an invalid name. With this
change three tokens will be generated: 'group1', '',
and 'group2'. The empty string will then trigger the
item->empty() check, which will successfully inform that
such stat name is not valid.
SLICC was breaking this rule with one of its stats by
creating a sub-group (inTransLatHist) whose parent had
an empty name, so it has been fixed.
Change-Id: Ica5ca684911374d59a0a809636594d048d755deb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43590
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Previously Serializable::serializeAll called SimObject::
serializeAll. This created an unnecessary dependency. This
change makes Serializable responsible for the generation
of the checkpoint file, and then the SimObjects will
perform the serialization of the object using that file.
With this change serialize.hh contains only functions
related to the (un)serialization of basic types or
objects that inherit from Serializable. As a general
rule, functions related to the (un)serialization of
specific/other types must be defined in the file that
introduces that type.
Change-Id: I9438b799d7e9d4c992a62c7f9d1f15f3f3250a5a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38740
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
SimObjects keep a static list with all existing
SimObjects. This list is then used to serialize
all objects declared in the system. If these
macros were used then an object would be serialized
more than once, which is not a correct behavior.
Change-Id: Idc4433ec2a23a21ee5ee2b7cc2facfe3dd979859
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46720
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
With this change serialize.hh is no longer responsible
for the (un)serialization of events. As a general rule,
rules to (un)serialize non-basic types should be defined
at the file that introduces that type. Therefore,
(UN)SERIALIZE_EVENT have been moved to eventq.hh.
Globals has a single instance which must be serialized
and unserialized. Instead of having a stray global
variable handled by Serialization, we pass its management
to Root. As a side effect, Globals is assigned its own
files: sim/globals.(cc/hh).
Finally, 'unserializeGlobals()' is removed, so that
Root can fully handle Globals' serialization. This
breaks checkpoint compatibility, so a checkpoint
upgrader is added.
Change-Id: I9c8e57306f83f9cc30ab2b745a4972755191bec4
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43586
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Device memories are used for PCI devices which have their own pools of
backing store memory such as amdgpu device. The check for an address
being in device memory previously did not handle multiple interleaved
memory devices with the same address range. Therefore, the device memory
check would fail if the interleaving masks did not match. This updates
the method to iterate through all device memories that handle the
RequestorID and returns true if any of the device memories contain the
packet address.
Change-Id: I9339d39c1cb54a5b9075c4a122c118fe61dc6fdb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46381
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
There are special counters in the framebuffer that are tested during
driver initialization. The expected behavior of the counters is to
return the previously read value + 1. There is one (known) counter used
in driver initialization at a fixed BAR address offset.
Change-Id: Id2dbb5fa9365b0a0453b15013c45aa67a2eec190
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46163
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Although the binary ROM blob and MMIO trace will be placed in
gem5-resources later as 'golden' versions, the scripts are added to
provide instructions for power users of Full System amdgpu that may want
to recreate the files themselves or use a GPU other than the Vega10 GPU
currently modeled.
Change-Id: Ica7ef3b9820b30be32a148ce6cf1d2f81dc2adf9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46162
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
The flow for Full System amdgpu is the use KVM to boot linux and begin
loading the driver module. However, the amdgpu module requires reading
the VGA ROM located at 0xc0000 in X86. KVM does not support having a
small 128KiB hole at this location, therefore we take a checkpoint and
switch to a timing CPU to continue loading the drivers before the VGA
ROM is read.
This creates a checkpoint just before the first MMIOs. This is indicated
by three interrupts being sent to the PCI device. After three interrupts
in a row are counted a checkpoint exit event occurs. The interrupt
counter is reset if a non-interrupt PCI read is seen.
Change-Id: I23b320abe81ff6e766cb3f604eca2979339938e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46161
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The O3CPU, which supports transactional memory (HTM), is using
the inHtmTransactionalState and getHtmCheckpointPtr methods
to check if we are in the middle of a transaction and return
false or a nullptr if that's not the case.
We need to avoid aborting simulation (panic) when those methods are
called in the O3CPU + Checker simulation.
This patch is providing the minimal support to re-enable O3 + Checker
runs and it is not providing HTM support in the CheckerCPU (meaning, we
won't be able to use the Checker in a transactional simulation)
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I7f71d5290c53b0402763d69f137ecaa1208253fb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46624
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This script previously existed entirely within our Jenkins instance.
However, in the interests of transparancy, and allowing users to run the
Nightly tests on their own machines, this script should be added to the
repo. This also allows the community to change the nightly tests without
contacting the Jenkins' administrators.
Change-Id: I6cc3d7597776dbdeb9efb31766d579a2be733d68
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46520
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
