Commit Graph

18218 Commits

Author SHA1 Message Date
Richard Cooper
378778fcb7 ext: Add extra defines to libelf to support Apple silicon.
The current version of libelf does not include a configuration
compatible with Apple silicon. This patch adds the required defines.

Change-Id: I9b7b9b1f711973159f31666d3fe480c2dc01a6b7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52723
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Austin Harris <mail@austin-harris.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-15 08:34:33 +00:00
Eduardo José Gómez Hernández
9979cdda37 arch-x86: Fix rcl implementation triggers "bits" assert
With some values of rotations and datasizes, is it possible to call
"bits" with first being smaller than seccond. To prevent it, rcl,
similar to other rotations had an if to check if the value to rotate
is bigger than 1, however, rcl was checking for 'shiftAmt' instead
of 'realShiftAmt'.

This was not detected before because:
 1 - The assert triggered in "bits" is from a recent commit
 2 - The result is correct.

Change-Id: I669f4e064e12b035538e5dd0cc61eb4546603512
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52803
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-13 09:05:28 +00:00
Gabe Black
5290ae8dbd scons: Make the perf and prof builds into options.
That makes it possible to add profiling options to debug or opt builds,
and not just the fast build which the perf/prof builds were implicitly
modeled after.

Change-Id: Id8502825146b01b4869e18d1239e32ebe3303d87
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51988
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-11-12 21:43:40 +00:00
Giacomo Travaglini
93049b5143 testlib: Explicitly use python3 when running regressions
Change-Id: I7968bea5db15a25c97abb68333c04e3ff1ae78f9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52743
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-12 08:59:39 +00:00
Yu-hsin Wang
2771572f76 arch-arm: gdb support Thumb ISA
BaseRemoteGDB only checks if the breakpoint size equals to MachInst size.
However, there are two kinds of instruction size in ARM. We should allow
the 16-bits breakpoint for Thumb ISA.

Change-Id: I79c0e1503092ecf233c719f2e354739edb8e6b25
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52624
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-12 01:17:59 +00:00
Yu-hsin Wang
13caaf4dcc arch-arm: add missing override for remote_gdb
Change-Id: Iecbf56d97784367e416f950658515343734f3bec
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52685
Reviewed-by: Earl Ou <shunhsingou@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-12 01:16:33 +00:00
Gabe Black
14b3fd396a fastmodel: Implement Iris::MMU::translateFunctional.
This new pure virtual method was not implemented, preventing the
automatic create() method from being generated, and causing a linking
error.

Change-Id: I5619da5216d5161cb5e227de627b02f395bea0e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52705
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Earl Ou <shunhsingou@google.com>
2021-11-12 01:10:58 +00:00
Gabe Black
f7284c66b2 fastmodel: Fix params for the IrisTLB.
Add PARAMS(), and include the params header file.

This fixes the build when fast model is enabled.

Change-Id: If4babbade9bf896084060f3f3b3b620947d0c83a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52704
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Earl Ou <shunhsingou@google.com>
2021-11-12 01:10:58 +00:00
Gabe Black
2d11080e71 fastmodel: Delete the unused ArmFastModelBin.
Change-Id: I29fb6cdfac809fb0a3577470143714b1da2d4562
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52703
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Earl Ou <shunhsingou@google.com>
2021-11-12 01:10:58 +00:00
Bobby R. Bruce
bd6da8f88d tests: Fix riscv boot exit tests
Due to this change:
https://gem5-review.googlesource.com/c/public/gem5/+/52089
full RISCV boot tests were added, which makes the "tick_exit" parameter
optional (left to 'None' if simulating a full boot). However, the
simulation function was not updated to not pass the "tick_exit"
parameter if not set. This cause an error. This patch fixes this.

Change-Id: I9c62a6a46d9334a2e9fbad2221b42a1ff4843a54
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52644
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-11 16:06:53 +00:00
Bobby R. Bruce
b65b59d2d2 tests: Remove 'override-download' flag from insttest
This flag was previously passed to the 'simple_binary_run.py' to
override downloads. However, since this patch:
https://gem5-review.googlesource.com/c/public/gem5/+/52086
we no longer use the flag. It appears in this patch the insttest test
was not updated and, as such, this test failed:
https://jenkins.gem5.org/job/nightly/38/

This, in part, will fix the nightly build.

Change-Id: I4fb5ab175c73687304c04fe426f81519d23574a7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52643
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-11 16:06:53 +00:00
Yu-hsin Wang
76046ee3ce fastmodel: CortexR52 support gdb
We change several things to support basic gdb.

1. Correct the memory translation.
memory_getUsefulAddressTranslations returns an empty list. So there's no
memory translation in R52.

2. Implement FPSCR for gdb collecting status.

3. Correct the breakpoint memory space.

Change-Id: Icc824502faec5ac228003f0de7e9dbe26babe7ef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52623
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Earl Ou <shunhsingou@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-11 01:32:16 +00:00
Giacomo Travaglini
1a72fc6c85 configs: Replace connectAllPorts with connectCachedPorts
Uncached ports are not used in Arm configs (X86 only [1])

[1]: https://github.com/gem5/gem5/blob/stable/src/cpu/BaseCPU.py#L181

Change-Id: I0f71f605ef73d9adc418414c891569bc475b2587
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52583
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-10 10:24:01 +00:00
Gabe Black
10e4d43345 cpu-o3: Manually flatten the index for vector reg elements.
There is a function for this purpose in RegId called flatIndex(), which
I had attempted to use with PhysRegId which inherits from RegId.
Unfortunately, PhysRegId redefines the flatIndex() method and makes it
do something completely different, which is to turn map the index into a
linearization of all registers in the CPU.

Instead of using the decoy wrong method, and because the one we actually
want is not accessible, we can just manually compute the flattened index
in the two places we use it.

Change-Id: I8bd02f0be0f4fb3742da48b2955e9e75ec57245b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52603
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-10 07:04:09 +00:00
Jui-min Lee
20e045a05f arch-riscv: Add NMI support
NMI is platform dependent according to riscv spec, so we intentionally
propose a very minimal design that doesn't give user any new accessible
register to interact with the NMI mechanism.

In current design, the NMI reset vector is fixed to 0x0 and always set
mcause to zero. mret from NMI handler is still possible, but it's up to
the user to detect whether a M-mode trap handler is interrupted and to
recover from it (if at all possible).

1. Add new fault type to represent NMI fault
2. Add non-standard registers to save the status of NMI
   a. nmivec[63:2] = NMI reset vector address
   b. nmie[0:0] = is NMI enabled = not in NMI handler
   c. nmip[0:0] = is NMI pending
3. Add new function in RiscvInterrupts to raise/clear NMI

Bug: 200169094
Test: None
Change-Id: Ia81e1c9589bc02f0690d094fff5f13412846acbe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52363
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-10 06:29:33 +00:00
Gabe Black
636783856f dev-arm: Ensure all fields of GicV2 are initialized.
The constructor tried to initialize all values, but in particular missed
intGroup, and may have missed other values as well.

Change-Id: Ibcd610e40259e46e3cde9b76c7f9ddc816832dfd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52406
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-09 21:40:58 +00:00
Bobby R. Bruce
4929c1260e tests: Move MI_Example tests to Long/Nightly
Two tests, one in test_kvm_fork_run.py and another in
test_kvm_cpu_switch.py, were trying to run the MI_Example protocol as
part of the quick/kokoro run. MI_Example requires the building of X86,
though we try to use GCN3_X86 exclusively to avoid compiling an
additional target. As such, these MI_Example tests have been moved to
the long/nightly run.

Change-Id: I3c196e7e336148a1b7a124b5810348a2e587fe24
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52563
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-09 19:09:41 +00:00
Jason Lowe-Power
1e8aeee698 ext: Update pybind11 to v2.8.1
Change-Id: Ia1c7081377f53fd470addf35526f8b28a949a7b0
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52523
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
2021-11-09 15:34:32 +00:00
Gabe Black
ba5f68db3d misc: Use python 3's argumentless super().
When calling a method in a superclass, you can/should use the super()
method to get a reference to that class. The python 2 version of that
method takes two parameters, the current class name, and the "self"
instance. The python 3 version takes no arguments. This is better for a
at least three reasons.

First, this version is less verbose because you don't have to specify
any arguments.

Second, you don't have to remember which argument goes where (I always
have to look it up), and you can't accidentally use the wrong class
name, or forget to update it if you copy code from a different class.

Third, this version will work correctly if you use a class decorator.
I don't know exactly how the mechanics of this work, but it is referred
to in a comment on this stackoverflow question:

https://stackoverflow.com/questions/681953/how-to-decorate-a-class

Change-Id: I427737c8f767e80da86cd245642e3b057121bc3b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52224
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-09 13:04:44 +00:00
Bobby R. Bruce
e4cff7b5ca stdlib: Remove 'exit_on_work_items' from boards' constructor
This has been moved to the `set_kernel_disk_workload` function, and is
set to True by default.

Change-Id: I9df2fa2946dd942b5011f05b948542097310352e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52223
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-11-09 00:49:58 +00:00
Bobby R. Bruce
4307d8b73f stdlib: Remove unneeded imports in the gem5 Python Library
Change-Id: I6d4ccc4e18bd36d4a9dad9b6782ebcc0e64c4e44
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52203
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-11-09 00:49:58 +00:00
Bobby R. Bruce
3a692d48e1 stdlib,tests,configs: Create 'SEBinaryWorkload' class
This enables an SE mode execution of binary if added a Board's
superclass.

This has been abstracted from the SimpleBoard.

The 'set_workload' function has been renamed 'set_se_binary_workload'.
This is clearer on its purpose and doesn't overlap with other
'set_workload' functions.

Change-Id: I714425a3b6b98b91e762ad076eba583bc5953ddd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52186
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-11-09 00:49:58 +00:00
Bobby R. Bruce
856c23d373 stdlib: Add missing @overrides to RISCVBoard
Change-Id: I6879c9744c28038c5d40984785f2f502a2fd1c5a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52185
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-09 00:49:58 +00:00
Bobby R. Bruce
ddb4a84efd stdlib: Move 'connect_things' to AbstractBoard constructor
This patch moves 'connect_things' to the AbstractBoard constructor,
thereby meaning it does not need to be called directly in gem5
configuration scripts. This method has been changed to private as a
result.

As boards that inherit from AbstractBoard require certain things to be
setup prior to `connect_things` being called, a new abstract function,
`_setup_board` has been created. This is called in the AbstractBoard
constructor before `connect_things` and can be overridden by boards to
setup board properties as required.

Change-Id: I558a4321b850a6b19e20b7d56d0bcae5805114b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52184
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-09 00:49:58 +00:00
Bobby R. Bruce
65e1314d75 stdlib: Move 'connect_things' to the AbstractBoard
This is in order to enforce a strict ordering of how gem5 components are
incorporated into a board. The `connect_things` function is now final so
it cannot be overridden.

Change-Id: I4c0e7ac9d307b399854f5326bb57bcf561f92054
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52183
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-11-09 00:49:58 +00:00
Bobby R. Bruce
6c68745818 tests: Update RISCV boot tests to use Ubuntu resource
This ubuntu disk image will execute an 'm5 exit' after boot and can
therefore be used to execute "boot exit" tests as part of our
long/nightly tests. These are included in this patch.

Change-Id: Ia5bdb1bfc3d9100b2ea15e23bddb49f7c4faf32d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52089
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-11-09 00:49:58 +00:00
Bobby R. Bruce
b504398df8 stdlib,tests,configs: Replace Resource override download
The override parameter in the constructor has been renamed to to
'download_md5_mismatch'. This makes the purpose of this parameter
clearer.

The default value has been changed from False to True. We found in most
cases we want to re-download files if the md5 values have changes. Not
wanting to do so is the corner case. This allows us to remove a lot of
parameters from test and example scripts, included in this patch.

Change-Id: I99fc7743f5adf78bf6f4f8efc6222e6df83ac6da
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52086
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-09 00:49:58 +00:00
Bobby R. Bruce
bde1c46d2d stdlib,configs: Remove setting resource_directory in examples
As part of https://gem5-review.googlesource.com/c/public/gem5/+/51369
we have a default resource directory. We therefore no longer need to set
`resource_directory` to get a consistent download location.

Change-Id: I0bef9930db9157a999dc063bd49377de1fe75102
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51950
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-11-09 00:49:58 +00:00
Bobby R. Bruce
76251f9407 stdlib: Fix resource downloader download to cwd upon failure
There are some cases where default downloading to `~/.cache/gem5` will
not work (for example, running gem5 in a Docker container, an error
observed here:
https://gem5-review.googlesource.com/c/public/gem5/+/51950).

To fix this, the `_get_default_resource_dir` has been altered to iterate
through a list of default resource directory targets. This change will
mean if `~/.cache/gem5` is not available then the resource is downloaded
to the current working directory of gem5.

Change-Id: I84e523f3adc182e140959243ff9335510d6b7185
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52423
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-09 00:49:58 +00:00
Bobby R. Bruce
1b0b59f49f stdlib: Create 'KernelDiskWorkload' abstract class
The purpose of this class is to:

* Create a standard way to set a typical kernel/disk image workload.
* Cleans up the manner in which readfile values/contents are set.
* Allows a user to specify their own kernel arguments, but still sets
sensible defaults.

As of this commit, this interface has been added to the X86Board and the
RISCVBoard.

Change-Id: I34f4c2b829f1ae5c1cae12039436cbb345a89d09
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51949
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-09 00:49:58 +00:00
Bobby R. Bruce
03f93d40b2 stdlib: Automatically set disk root partition in set_workload
The linux kernel `root` parameter must be specified in the board's
`set_workload` function. However, the root partition on a disk image
passed to this function can change. Therefore, for gem5 resources disk
images, we inspect the metadata to obtain the root partition and
automatically set this.

This patch is dependent on the following gem5 resources change to
function correctly:
https://gem5-review.googlesource.com/c/public/gem5-resources/+/51887

Note: This patch will only automatically set the root partition
information for disk images in gem5 resources.

Issue-on: https://gem5.atlassian.net/browse/GEM5-1102
Change-Id: I9a19706f3ba78bf026b6bfdff4bff84a3c8ccdb2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51948
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-09 00:49:58 +00:00
Bobby R. Bruce
2e57850499 stdlib: Remove SimpleBoard as a superclass
Previously SimpleBoard inherited from AbstractBoard and X86Board and
RiscvBoard inherited from the SimpleBoard. This has been shown to be a
needless level of abstraction. As such, this commit refactors the code
to have X86Board and RiscvBoard inherit directly from AbstractBoard.
Code common to the SimpleBoard, X86Board, and RiscvBoard has been moved
to the AbstractBoard.

Change-Id: I5a2c7404efeb4f8ddcb5d8006e3c163d10b88b2c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51790
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-09 00:49:58 +00:00
Gabe Black
4b361aa4bc arch,cpu: Refactor PCState construction a little.
Make the Addr constructor explicit to avoid implicit/hidden conversions
from Addr.

Also, add a copy constructor to the PCState types, and explicitly enable
the assignment operator.

Change-Id: Ibef17ece7fd06b2f9709c46d118e88a80da0b194
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52036
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-11-08 02:16:01 +00:00
Gabe Black
3f937352fa arch: Add a virtual clone() method to PCState.
This will let callers create a separate copy of a PCState class
instance. This makes it more explicit when creating copies of a PCState
to make sure the programmer is more aware, and avoids having to know
what the actual type is to make a copy.

Change-Id: I728a278afdb55b800c753a5b7f65f62f4a80c043
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52035
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-11-08 02:16:01 +00:00
Gabe Black
284f75b61e arch: Add some helpers to make it easier to cast PCState.
These helpers will make it easier to cast a PCStatePtr into an ISA
specific class with less syntactic fluff. They are currently implemented
with a static_cast for performance reasons, but could be implemented
with a dynamic_cast and an assert for extra debugging if you were
willing to pay the performance overhead. In the future this might be
switched/enabled as an extra debugging mode, like how locking can have
extra checks enabled in the Linux kernel.

Change-Id: Ibc2443c6b991ebc2e5d0240a88436849cb6de2b9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52033
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-11-08 02:16:01 +00:00
Gabe Black
a5984cc497 arch: Extract PCStateCommon from PCStateBase.
This class has a lot of common functionality which all PCState classes
use, but in order to make it a true base class which provides the
complete interface for PCState-s throughout gem5, all its methods would
need to become virtual. That doesn't have to be the case today because
we use the literal full ISA specific PC class directly, but we need to
move away from that.

This change leaves PCStateBase empty, since we don't know what will need
to be accessible in base classes through a common/virtual interface.

Also, move methods which do not depend on the InstWidth template
parameter out of SimplePCState and into PCStateCommon. This avoids
having duplicate methods with the same contents which don't depend on
InstWidth.

Change-Id: I31309c4f35e897db1bc8318439fae1567a82b35e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52031
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Earl Ou <shunhsingou@google.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-08 02:16:01 +00:00
Jason Lowe-Power
6f49a1fe29 mem: Initialize all stats in MemInterface
Change-Id: I1ee9ca14127abb7311ee8282b3fef1051277592c
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52503
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-11-06 18:25:43 +00:00
Gabe Black
314dae4b86 dev-arm: Set cntkctl and cnthctl in the CoreTimers constructor.
The cntkctl and cnthctl registers were not initialized by the CoreTimers
constructor which upset valgrind when they were later used by
handleStream.

Change-Id: Iaedbb2d957aeb428fd563be2e24ccb8d2cf57f26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52403
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-06 08:39:46 +00:00
Gabe Black
a8b9bc4770 cpu-o3: Remove unnecessary this->s from DynInst and SimpleFreeList.
These were left over from when these were template classes.

Change-Id: I102d2016fbba0ca09f16e10d8741ae0e2f967681
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52484
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-05 22:57:29 +00:00
Gabe Black
e7cd655f14 base: Set enableUnits in ScalarPrint declared in DistPrint::operator().
The setup() method of ScalarPrint, inherited from BasePrint, is not
called by its constructor, and is not called on the ScalarPrint "print"
in DistPrint::operator(). This sets most of the values in BasePrint.
Instead, this method sets these values itself based on the values of the
DistPrint itself.

Unfortunately it looks like this method forgot to set enableUnits, which
ends up otherwise uninitialized when the printUnits method is called.
This change fixes that.

Change-Id: Ib1ea78796539f6d9222d19dad597a4e64aa69808
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52483
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-05 22:56:48 +00:00
Kyle Roarty
223cd52431 arch-gcn3,arch-vega: Don't write exec in v_cmp_f_i32
Per the GCN3 and VEGA ISAs, v_cmpx_* writes exec, while v_cmp_* doesn't.

This removes the erroneous exec write in the VOP3 implementation of
v_cmp_f_i32.

Change-Id: I048e35917163c45b879f38d31a88f3f3d56c0baf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52445
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-05 19:52:40 +00:00
Gabe Black
e34fa5d86a mem-cache: Ensure all fields of the CacheBlk class are initialized.
The constructor only initialized two fields, data and _tickInserted. The
print() method at least accesses the coherence status bits, which
valgrind determined were being accessed without being initialized.

This change adds a default initializer to all fields to prevent any
value from flapping around uninitialized.

Change-Id: Ie4c839504d49f9a131d8e3c3e8be02ff22f453a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52404
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-04 22:53:51 +00:00
Gabe Black
6d60e76a60 mem-cache: Don't generate debug output unless you're going to use it.
The BaseCache::handleFill function would generate an "old_state" string
unconditionally, just in case it would need to print it out later on in
the function if the Cache debug variable was set. This is very wasteful.
We should only generate that string if we are actually going to use it
later on.

Change-Id: I4a570d1cd2814e5a089eac1233dedd1801d68975
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52405
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-04 19:48:08 +00:00
Bobby R. Bruce
d6e402ad1e misc: Add 'stdlib' tag to MAINTAINERS.yaml
This tag is for the "gem5 standard library" which can be found in
`src/python/gem5`.

Change-Id: Idf276635cd3f1d729cfbb4b7195b20fbdddd6584
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51791
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-04 18:50:27 +00:00
Gabe Black
e5059539a6 cpu-kvm,arch-x86,arch-arm,dev: Pair operator new with operator delete.
When allocating memory with operator new(size_t), we should also delete
that memory with operator delete(). Note that this is a generic form of
new and delete which do not construct an object in the allocated space,
or delete the object when freeing the space.

There were a number of places where we were over-allocating a structure
so that there would be room after it for other data, at least sometimes
to allocate C structures which would have a trailing array of some other
structure with an undefined size. Those structures were then being
stored in a std::unique_ptr with the default deleter, which just calls
full blown delete and not operator delete.

It seems that this is often ok, and I was not able to find anything that
spelled out in bold letters that it isn't. I did find this sentence:

"If the pointer passed to the standard library deallocation function was
not obtained from the corresponding standard library allocation function,
the behavior is undefined."

On this webpage:

https://en.cppreference.com/w/cpp/memory/new/operator_delete

This is a *little* vague, since they might mean you can't mix malloc and
delete, or new and free. Strictly interpretting it though, it could mean
you can't mix operator new with regular delete, or any other mismatched
combination.

I also found that exactly how this causes problems depends on what heap
allocator you're using. When I used tcmalloc, gem5 would segfault within
that library. When I disabled tcmalloc to run valgrind, the segfault
went away. I think this may be because sometimes you get lucky and
undefined behavior is what you actually wanted, and sometimes you don't.

To fix this problem, this change overrides the deleter on all of these
unique_ptr-s so that they use operator delete. Also, it refactors some
code in arch/x86/kvm/x86_cpu.cc so that the function that allocates
memory with operator new returns a std::unique_ptr instead of a raw
pointer. This raw pointer was always immediately put into a unique_ptr
anyway, and, in addition to tidying up the call sights slightly, also
avoids having to define a custom deleter in each of those locations
instead of once in the allocation function.

Change-Id: I9ebff430996cf603051f5baa8708424819ed8465
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52383
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-04 04:39:24 +00:00
Bobby R. Bruce
245909cf78 tests: Removing Atomic CPU with Ruby tests
test_kvm_fork_run.py and test_kvm_cpu_switch.py both contained tests
which attempted to run a Ruby cache with an Atomic CPU. This is not
permitted. As such these tests have been removed.

Change-Id: I7996bda6313f59f76d7f9b73bef8351d72547481
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52384
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-04 00:51:26 +00:00
Bobby R. Bruce
515764d8b5 python: Remove incorrect usage of typing 'Optional'
There has been some confusion about usage of 'Optional'. In some areas
of the codebase it was assumed this specifies an optional parameter
(i.e., one which may or may not set, as it has a default value). This is
incorrect. 'Optional[<type>]' is shorthand for 'Union[<type>, None]',
i.e., it is used to state the value may be 'None'. This patch corrects
this throughout the gem5 codebase.

Change-Id: I77a6708dee448e8480870d073e128aed3d6ae904
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52143
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-03 21:47:10 +00:00
Giacomo Travaglini
470939fa84 arch: Fix serialization/deserialization of Vector registers
This bug has been introduced by [1].
Without this fix a vector register is only partially unserialized, effectively
breaking checkpoiting for vectored applications. For example if I am
initializing a vector register with the following checkpointed value:

0xaaaaaaaa_aaaaaaaa_aaaaaaaa_aaaaaaaa

The ParseParam logic will produce instead

0xaaaaaaaa_aaaaaaaa_00000000_00000000

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/41994

Change-Id: I5010d9f39d57fcee390e7419a64dbcd293e51fa0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51947
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2021-11-03 13:26:44 +00:00
Yu-hsin Wang
0d64ec9a29 base: fix name setter doesn't pass correct stat style
There are two kinds of stats in the system. The old one requires an
unique name, while the new one requires an local name. The setName
function has a flag to specify the difference. In the constructor of
InfoAccess, it sets correct flag to the setName function. However, if
you set the name later with the setter, it wouldn't set the flag for
you. This leads the name conflict in new style stats with same local
name. We should also pass the correct flag in the name setter.

Change-Id: I0fcaad3cca65d0f2859c5f6cb28a00813a026a0c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52323
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-03 04:36:31 +00:00
Eric Ye
514c2cb48a scons: Don't fail builds if TERM is not set
Bug: 204817626

Test: Scons build
Change-Id: I154c69503eaededda353d6b2925553b6cecb07eb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52304
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-03 03:40:26 +00:00