arch-x86: Fix rcl implementation triggers "bits" assert

With some values of rotations and datasizes, is it possible to call
"bits" with first being smaller than seccond. To prevent it, rcl,
similar to other rotations had an if to check if the value to rotate
is bigger than 1, however, rcl was checking for 'shiftAmt' instead
of 'realShiftAmt'.

This was not detected before because:
 1 - The assert triggered in "bits" is from a recent commit
 2 - The result is correct.

Change-Id: I669f4e064e12b035538e5dd0cc61eb4546603512
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52803
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/x86/isa/microops/regop.isa

@@ -990,7 +990,7 @@ let {{
                 CCFlagBits flags = cfofBits;
                 uint64_t top = PSrcReg1 << realShiftAmt;
                 uint64_t bottom = flags.cf << (realShiftAmt - 1);
-                if(shiftAmt > 1) {
+                if(realShiftAmt > 1) {
                     bottom |= bits(PSrcReg1, dataSize * 8 - 1,
                             dataSize * 8 - realShiftAmt + 1);
                 }