derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fastmodel: CortexR52 support gdb

Browse Source 
We change several things to support basic gdb.

1. Correct the memory translation.
memory_getUsefulAddressTranslations returns an empty list. So there's no
memory translation in R52.

2. Implement FPSCR for gdb collecting status.

3. Correct the breakpoint memory space.

Change-Id: Icc824502faec5ac228003f0de7e9dbe26babe7ef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52623
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Earl Ou <shunhsingou@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Yu-hsin Wang
2021-10-01 13:20:23 +08:00
parent 1a72fc6c85
commit 76046ee3ce
2 changed files with 23 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

51
src/arch/arm/fastmodel/CortexR52/thread_context.cc
View File

@@ -49,31 +49,9 @@ CortexR52TC::CortexR52TC(
bool
CortexR52TC::translateAddress(Addr &paddr, Addr vaddr)
{
// Determine what memory spaces are currently active.
Iris::CanonicalMsn in_msn;
switch (ArmISA::currEL(this)) {
case ArmISA::EL3:
in_msn = Iris::SecureMonitorMsn;
break;
case ArmISA::EL2:
in_msn = Iris::NsHypMsn;
break;
default:
in_msn = Iris::GuestMsn;
break;
}
Iris::CanonicalMsn out_msn = ArmISA::isSecure(this) ?
Iris::PhysicalMemorySecureMsn : Iris::PhysicalMemoryNonSecureMsn;
// Figure out what memory spaces match the canonical numbers we need.
iris::MemorySpaceId in = getMemorySpaceId(in_msn);
iris::MemorySpaceId out = getMemorySpaceId(out_msn);
panic_if(in == iris::IRIS_UINT64_MAX || out == iris::IRIS_UINT64_MAX,
"Canonical IRIS memory space numbers not found.");
return ThreadContext::translateAddress(paddr, out, vaddr, in);
// No MMU here.
paddr = vaddr;
return true;
}
void
@@ -89,6 +67,23 @@ CortexR52TC::initFromIrisInstance(const ResourceMap &resources)
extractResourceMap(ccRegIds, resources, ccRegIdxNameMap);
}
void
CortexR52TC::sendFunctional(PacketPtr pkt)
{
auto msn = Iris::PhysicalMemoryMsn;
auto id = getMemorySpaceId(msn);
auto addr = pkt->getAddr();
auto size = pkt->getSize();
auto data = pkt->getPtr<uint8_t>();
pkt->makeResponse();
if (pkt->isRead())
readMem(id, addr, data, size);
else
writeMem(id, addr, data, size);
}
RegVal
CortexR52TC::readIntReg(RegIndex reg_idx) const
{
@@ -148,9 +143,7 @@ const std::vector<iris::MemorySpaceId> &
CortexR52TC::getBpSpaceIds() const
{
if (bpSpaceIds.empty()) {
std::vector<Iris::CanonicalMsn> msns{
Iris::SecureMonitorMsn, Iris::GuestMsn, Iris::NsHypMsn,
Iris::HypAppMsn};
std::vector<Iris::CanonicalMsn> msns{Iris::GuestMsn, Iris::NsHypMsn};
for (auto &msn : msns) {
auto id = getMemorySpaceId(msn);
if (id != iris::IRIS_UINT64_MAX)
@@ -609,7 +602,7 @@ Iris::ThreadContext::IdxNameMap CortexR52TC::miscRegIdxNameMap({
// ArmISA::MISCREG_NZCV?
// ArmISA::MISCREG_DAIF?
// ArmISA::MISCREG_FPCR?
// ArmISA::MISCREG_FPSR?
{ ArmISA::MISCREG_FPSCR, "FPSCR" },
// ArmISA::MISCREG_DSPSR_EL0?
// ArmISA::MISCREG_DLR_EL0?
// ArmISA::MISCREG_SPSR_EL2?

1
src/arch/arm/fastmodel/CortexR52/thread_context.hh
View File

@@ -56,6 +56,7 @@ class CortexR52TC : public Iris::ThreadContext
bool translateAddress(Addr &paddr, Addr vaddr) override;
void initFromIrisInstance(const ResourceMap &resources) override;
void sendFunctional(PacketPtr pkt) override;
// Since this CPU doesn't support aarch64, we override these two methods
// and always assume we're 32 bit. More than likely we could be more