21 Commits

Author SHA1 Message Date
Tommaso Marinelli
b5e27f5ed8 configs: Generalize class types in CHI RNF/MN generators (#1851)
Classes CHI_RNF and CHI_MN can be specialized to override base
class/subclass attributes, like it happens in CustomMesh with
router_list (see configs/example/noc_config/2x4.py). To avoid missing
these attributes, it is needed to generalize the class types when
instantiating the objects in the recently added generators.
2024-12-18 21:16:26 -08:00
2channelkrt
f799d91309 ruby-chi: fix wrong ruby-CHI base class name (#1817)
fix ruby-CHI base class name so it actually runs

previously was combined with PR #1797
2024-12-04 15:47:44 -08:00
Giacomo Travaglini
76541929c9 configs: Instantiate RNFs and MN via callbacks
This commit allows top level configs making use of the Ruby module
to define node generation callbacks.
The config_ruby function will check the system object for two
factory methods

1) _rnf_gen, if defined, will be called to generate RNFs
2) _mn_gen, if defined, will be called to generate MNs

Change-Id: I9daeece646e7cdb2d3bfefa761a9650562f8eb4b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2024-12-02 08:33:11 -08:00
Jason Lowe-Power
42fe5accea configs,mem-ruby: Procotol-spec. names in CHI
Use the protocol-specific controller names in CHI.

**Important**: This could change some scripts. As long as people use
CHI_config (likely), this shouldn't be a problem, but if you have a
different version of CHI_config.py locally, you will need to make the
following updates:

`Cache_Controller` -> `CHI_Cache_Controller`
`Memory_Controller` -> `CHI_Memory_Controller`

Website updates coming soon!

Change-Id: I7afdcede884ac5f9a9a76cc3d3dd35941e4e2faa
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2024-11-19 10:53:59 -08:00
Erin Le
e1db67c4bd configs, dev, learning-gem5, python, tests: more clarification
This commit contains the rest of the base 2 vs base 10 cache/memory
size clarifications. It also changes the warning message to use
warn(). With these changes, the warning message should now no
longer show up during a fresh compilation of gem5.

Change-Id: Ia63f841bdf045b76473437f41548fab27dc19631
2024-08-23 18:02:42 -07:00
Jason Lowe-Power
b3e7af9d79 Support for classic prefetchers in Ruby (#502)
This patch adds supports for using the "classic" prefetchers with ruby
cache controllers.

This pull request includes a few commits making the changes in this
order:
- Refactor decouples the classic cache and prefetchers interfaces
- Extras probes for later integration with ruby
- General ruby-side support
- Adds support for the CHI protocol

Commit [mem-ruby: support prefetcher in CHI
protocol](2bdb65653b)
may be used as example on how to add support for other protocols.

JIRA issues that may be related to this pull request:
    https://gem5.atlassian.net/browse/GEM5-457
    https://gem5.atlassian.net/browse/GEM5-1112
2023-11-30 10:24:29 -08:00
Bobby R. Bruce
d11c40dcac misc: Run pre-commit run --all-files
This ensures `isort` is applied to all files in the repo.

Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9
2023-11-29 22:06:41 -08:00
Tiago Mück
91cf58871e mem-ruby: support prefetcher in CHI protocol
Use RubyPrefetcherProxy to support prefetchers in the
CHI cache controller

L1I/L1D/L2 prefechers can now be added by specifying a non-null
prefetcher type when configuring a CHI_RNF.

Related JIRA:
https://gem5.atlassian.net/browse/GEM5-457
https://gem5.atlassian.net/browse/GEM5-1112

Additional authors:
    Tuan Ta <tuan.ta2@arm.com>

Change-Id: I41dc637969acaab058b22a8c9c3931fa137eeace
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
2023-11-28 18:30:50 -06:00
Bobby R. Bruce
298119e402 misc,python: Run pre-commit run --all-files
Applies the `pyupgrade` hook to all files in the repo.

Change-Id: I9879c634a65c5fcaa9567c63bc5977ff97d5d3bf
2023-10-10 21:47:07 -07:00
Víctor Soria
6411b2255c mem-ruby,configs: Add CHI far atomics support
Introduce far atomic operations in CHI protocol.
Three configuration parameters have been used to tune this behavior:

  policy_type:       sets the atomic policy to one of the described in our paper
  atomic_op_latency: simulates the AMO ALU operation latency
  comp_anr:          configures the Atomic No return transaction to split
                     CompDBIDResp into two different messages DBIDResp and Comp

Change-Id: I087afad9ad9fcb9df42d72893c9e32ad5a5eb478
2023-10-04 19:19:08 +02:00
Giacomo Travaglini
e73655d038 misc: Use python f-strings for string formatting
This patch has been generated by applying flynt to the
gem5 repo (ext has been excluded)

JIRA: https://gem5.atlassian.net/browse/GEM5-831

Change-Id: I0935db6223d5426b99515959bde78e374cbadb04
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68957
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2023-03-16 09:05:29 +00:00
Tiago Mück
3871f57dc3 configs: set requestToMemory buffer size for CHI
Currently TBEs for write requests are deallocated when the request is
pushed to memory, so an unlimited requestToMemory buffers size allows
for an unlimited number of outstanding write requests.

Set the requestToMemory buffers size prevents this.
The buffer size should be greater than the enqueue latency to allow at
least one enqueue per cycle.

JIRA: https://gem5.atlassian.net/browse/GEM5-1195

Change-Id: I31829b6bbabd8b45e1142790038c27bd459fa709
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63674
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-09-28 18:56:04 +00:00
Tiago Mück
06a8a47322 configs: fix CHI mem buffers
Disabling randomization for the memory request and response buffers.
CHI requires that memory responses for the same address arrive in
the same order the request was sent.

Change-Id: Ia4236188679beaf2969978675414a870ccd9f94a
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63673
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-09-28 18:56:04 +00:00
Tiago Mück
ba3aa067a3 configs: CHI inc transitions_per_cycle
Previous limit may unintentionally throttle performance for controllers
with a large TBE table and high traffic.

Change-Id: I34d6f8727519b259bb3d4a80b1fff6c59197c508
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63672
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-09-28 18:56:04 +00:00
Bobby R. Bruce
787204c92d python: Apply Black formatter to Python files
The command executed was `black src configs tests util`.

Change-Id: I8dfaa6ab04658fea37618127d6ac19270028d771
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47024
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-08-03 09:10:41 +00:00
Samuel Stark
38d360a475 configs, mem-ruby: Implement DVMOps in CHI
1) Handling TLBI/TLBI_SYNC requests from the PE in the CHI Request Node
(Generating DVMOps)

2) Adding a new machine type for the Misc Node (MN) that handles DVMOps
from the Request Node (RN), following the protocol specified within
the Amba 5 CHI Architecture Specification [1]

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

[1]: https://developer.arm.com/documentation/ihi0050/latest

Change-Id: I9ac00463ec3080c90bb81af721d88d44047123b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57298
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-18 08:52:53 +00:00
Daecheol You
092d33f3f5 configs: Modify createAddrRanges to support NUMA configuration
When system is configured for NUMA, it has multiple memory ranges,
and each memory range is mapped to a corresponding NUMA node.
For this, the change enables createAddrRanges to map address ranges to
only a given HNFs.

JIRA: https://gem5.atlassian.net/browse/GEM5-1187

Change-Id: If4a8f3ba9aac9f74125970f63410883d2ad32f01
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56610
Reviewed-by: Tiago Muck <tiago.muck@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-28 00:19:30 +00:00
Giacomo Travaglini
d77407c0e4 configs: RubySequencer doesn't have "out_ports"
"out_ports" are actually called "interrupt_out_port"
This error has been introduced by [1]

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/52584

Change-Id: If0a8d22b2cd1ef0d4240f37f8a0adcf5a826fb9d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54524
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-21 17:52:01 +00:00
Giacomo Travaglini
65c32dc491 configs: Replace master/slave terminology from ruby scripts
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Iabc82a19e8d6c7cf619874dc2926276c349eba7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52865
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-11-22 09:53:14 +00:00
Giacomo Travaglini
de7337a32a misc: Replace master/slave terminology from BaseCPU.py
In order to fix several regression failures [1] the master/slave
terminology in src/cpu/BaseCPU.py was reintroduced [2].

This patch is addressing the issue by providing 2 different
ways of connecting cpu ports:

*) connectBus: The method assumes an object with a bus interface is
passed as an argument, therefore it tries to bind cpu ports to the
bus.mem_side_ports and bus.cpu_side_ports

*) connectAllPorts: No assumption on the port owning device is made.
The method simply accepts ports as arguments which will be directly
connected to the peer cpu ports
This will be used for example by ruby Sequencers

[1]: https://gem5.atlassian.net/browse/GEM5-775
[2]: https://gem5-review.googlesource.com/c/public/gem5/+/34495

Change-Id: I715ab8471621d6e5eb36731d7eaefbedf9663a71
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52584
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2021-11-16 18:17:47 +00:00
Tiago Mück
21dfaa49ca configs: changed CHI --noc-config format
Changed format from yaml to plain python. The new py configuration
file, when provided, must specialize the CHI node types defined in
configs/ruby/CHI_config.py (moved from configs/ruby/CHI.py). This
is required in order to setup the node->router bindings when the
CustomMesh topology is used.

See configs/example/noc_config/2x4.py (replaces
configs/example/noc_config/2x4.yaml) for an example.

--noc-config was also renamed to --chi-config, since the CHI node types
can be fully specialized in the configuration file.

Change-Id: Ic0c5407dba3d2483d5c30634c115b5410a5228fd
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43123
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-18 19:02:21 +00:00