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configs: Replace master/slave terminology from ruby scripts

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Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Iabc82a19e8d6c7cf619874dc2926276c349eba7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52865
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Giacomo Travaglini
2021-11-09 10:21:58 +00:00
parent f1fc49ed13
commit 65c32dc491
11 changed files with 154 additions and 155 deletions
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10
configs/ruby/AMD_Base_Constructor.py
View File

@@ -116,11 +116,11 @@ def construct(options, system, ruby_system):
cp_cntrl.create(options, ruby_system, system)
# Connect the CP controllers to the ruby network
cp_cntrl.requestFromCore = ruby_system.network.slave
cp_cntrl.responseFromCore = ruby_system.network.slave
cp_cntrl.unblockFromCore = ruby_system.network.slave
cp_cntrl.probeToCore = ruby_system.network.master
cp_cntrl.responseToCore = ruby_system.network.master
cp_cntrl.requestFromCore = ruby_system.network.in_port
cp_cntrl.responseFromCore = ruby_system.network.in_port
cp_cntrl.unblockFromCore = ruby_system.network.in_port
cp_cntrl.probeToCore = ruby_system.network.out_port
cp_cntrl.responseToCore = ruby_system.network.out_port
exec("system.cp_cntrl%d = cp_cntrl" % i)
#

1
configs/ruby/CHI_config.py
View File

@@ -351,7 +351,6 @@ class CPUSequencerWrapper:
self.__dict__['support_inst_reqs'] = True
# Compatibility with certain scripts that wire up ports
# without connectCpuPorts
self.__dict__['slave'] = dseq.in_ports
self.__dict__['in_ports'] = dseq.in_ports
def connectCpuPorts(self, cpu):

38
configs/ruby/MESI_Three_Level.py
View File

@@ -173,16 +173,16 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the L1 controllers and the network
l1_cntrl.requestToL2 = MessageBuffer()
l1_cntrl.requestToL2.master = ruby_system.network.slave
l1_cntrl.requestToL2.out_port = ruby_system.network.in_port
l1_cntrl.responseToL2 = MessageBuffer()
l1_cntrl.responseToL2.master = ruby_system.network.slave
l1_cntrl.responseToL2.out_port = ruby_system.network.in_port
l1_cntrl.unblockToL2 = MessageBuffer()
l1_cntrl.unblockToL2.master = ruby_system.network.slave
l1_cntrl.unblockToL2.out_port = ruby_system.network.in_port
l1_cntrl.requestFromL2 = MessageBuffer()
l1_cntrl.requestFromL2.slave = ruby_system.network.master
l1_cntrl.requestFromL2.in_port = ruby_system.network.out_port
l1_cntrl.responseFromL2 = MessageBuffer()
l1_cntrl.responseFromL2.slave = ruby_system.network.master
l1_cntrl.responseFromL2.in_port = ruby_system.network.out_port
for j in range(num_l2caches_per_cluster):
@@ -203,18 +203,18 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the L2 controllers and the network
l2_cntrl.DirRequestFromL2Cache = MessageBuffer()
l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave
l2_cntrl.DirRequestFromL2Cache.out_port = ruby_system.network.in_port
l2_cntrl.L1RequestFromL2Cache = MessageBuffer()
l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
l2_cntrl.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
l2_cntrl.responseFromL2Cache = MessageBuffer()
l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
l2_cntrl.responseFromL2Cache.out_port = ruby_system.network.in_port
l2_cntrl.unblockToL2Cache = MessageBuffer()
l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master
l2_cntrl.unblockToL2Cache.in_port = ruby_system.network.out_port
l2_cntrl.L1RequestToL2Cache = MessageBuffer()
l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master
l2_cntrl.L1RequestToL2Cache.in_port = ruby_system.network.out_port
l2_cntrl.responseToL2Cache = MessageBuffer()
l2_cntrl.responseToL2Cache.slave = ruby_system.network.master
l2_cntrl.responseToL2Cache.in_port = ruby_system.network.out_port
# Run each of the ruby memory controllers at a ratio of the frequency of
# the ruby system
@@ -230,11 +230,11 @@ def create_system(options, full_system, system, dma_ports, bootmem,
for dir_cntrl in dir_cntrl_nodes:
# Connect the directory controllers and the network
dir_cntrl.requestToDir = MessageBuffer()
dir_cntrl.requestToDir.slave = ruby_system.network.master
dir_cntrl.requestToDir.in_port = ruby_system.network.out_port
dir_cntrl.responseToDir = MessageBuffer()
dir_cntrl.responseToDir.slave = ruby_system.network.master
dir_cntrl.responseToDir.in_port = ruby_system.network.out_port
dir_cntrl.responseFromDir = MessageBuffer()
dir_cntrl.responseFromDir.master = ruby_system.network.slave
dir_cntrl.responseFromDir.out_port = ruby_system.network.in_port
dir_cntrl.requestToMemory = MessageBuffer()
dir_cntrl.responseFromMemory = MessageBuffer()
@@ -250,15 +250,15 @@ def create_system(options, full_system, system, dma_ports, bootmem,
ruby_system = ruby_system)
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
exec("ruby_system.dma_cntrl%d.dma_sequencer.in_ports = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
# Connect the dma controller to the network
dma_cntrl.mandatoryQueue = MessageBuffer()
dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
dma_cntrl.responseFromDir.slave = ruby_system.network.master
dma_cntrl.responseFromDir.in_port = ruby_system.network.out_port
dma_cntrl.requestToDir = MessageBuffer()
dma_cntrl.requestToDir.master = ruby_system.network.slave
dma_cntrl.requestToDir.out_port = ruby_system.network.in_port
all_cntrls = l0_cntrl_nodes + \
l1_cntrl_nodes + \
@@ -278,9 +278,9 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the dma controller to the network
io_controller.mandatoryQueue = MessageBuffer()
io_controller.responseFromDir = MessageBuffer(ordered = True)
io_controller.responseFromDir.slave = ruby_system.network.master
io_controller.responseFromDir.in_port = ruby_system.network.out_port
io_controller.requestToDir = MessageBuffer()
io_controller.requestToDir.master = ruby_system.network.slave
io_controller.requestToDir.out_port = ruby_system.network.in_port
all_cntrls = all_cntrls + [io_controller]
# Register configuration with filesystem

38
configs/ruby/MESI_Three_Level_HTM.py
View File

@@ -172,16 +172,16 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the L1 controllers and the network
l1_cntrl.requestToL2 = MessageBuffer()
l1_cntrl.requestToL2.master = ruby_system.network.slave
l1_cntrl.requestToL2.out_port = ruby_system.network.in_port
l1_cntrl.responseToL2 = MessageBuffer()
l1_cntrl.responseToL2.master = ruby_system.network.slave
l1_cntrl.responseToL2.out_port = ruby_system.network.in_port
l1_cntrl.unblockToL2 = MessageBuffer()
l1_cntrl.unblockToL2.master = ruby_system.network.slave
l1_cntrl.unblockToL2.out_port = ruby_system.network.in_port
l1_cntrl.requestFromL2 = MessageBuffer()
l1_cntrl.requestFromL2.slave = ruby_system.network.master
l1_cntrl.requestFromL2.in_port = ruby_system.network.out_port
l1_cntrl.responseFromL2 = MessageBuffer()
l1_cntrl.responseFromL2.slave = ruby_system.network.master
l1_cntrl.responseFromL2.in_port = ruby_system.network.out_port
for j in range(num_l2caches_per_cluster):
@@ -202,18 +202,18 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the L2 controllers and the network
l2_cntrl.DirRequestFromL2Cache = MessageBuffer()
l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave
l2_cntrl.DirRequestFromL2Cache.out_port = ruby_system.network.in_port
l2_cntrl.L1RequestFromL2Cache = MessageBuffer()
l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
l2_cntrl.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
l2_cntrl.responseFromL2Cache = MessageBuffer()
l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
l2_cntrl.responseFromL2Cache.out_port = ruby_system.network.in_port
l2_cntrl.unblockToL2Cache = MessageBuffer()
l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master
l2_cntrl.unblockToL2Cache.in_port = ruby_system.network.out_port
l2_cntrl.L1RequestToL2Cache = MessageBuffer()
l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master
l2_cntrl.L1RequestToL2Cache.in_port = ruby_system.network.out_port
l2_cntrl.responseToL2Cache = MessageBuffer()
l2_cntrl.responseToL2Cache.slave = ruby_system.network.master
l2_cntrl.responseToL2Cache.in_port = ruby_system.network.out_port
# Run each of the ruby memory controllers at a ratio of the frequency of
# the ruby system
@@ -229,11 +229,11 @@ def create_system(options, full_system, system, dma_ports, bootmem,
for dir_cntrl in dir_cntrl_nodes:
# Connect the directory controllers and the network
dir_cntrl.requestToDir = MessageBuffer()
dir_cntrl.requestToDir.slave = ruby_system.network.master
dir_cntrl.requestToDir.in_port = ruby_system.network.out_port
dir_cntrl.responseToDir = MessageBuffer()
dir_cntrl.responseToDir.slave = ruby_system.network.master
dir_cntrl.responseToDir.in_port = ruby_system.network.out_port
dir_cntrl.responseFromDir = MessageBuffer()
dir_cntrl.responseFromDir.master = ruby_system.network.slave
dir_cntrl.responseFromDir.out_port = ruby_system.network.in_port
dir_cntrl.requestToMemory = MessageBuffer()
dir_cntrl.responseFromMemory = MessageBuffer()
@@ -249,15 +249,15 @@ def create_system(options, full_system, system, dma_ports, bootmem,
ruby_system = ruby_system)
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
exec("ruby_system.dma_cntrl%d.dma_sequencer.in_ports = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
# Connect the dma controller to the network
dma_cntrl.mandatoryQueue = MessageBuffer()
dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
dma_cntrl.responseFromDir.slave = ruby_system.network.master
dma_cntrl.responseFromDir.in_port = ruby_system.network.out_port
dma_cntrl.requestToDir = MessageBuffer()
dma_cntrl.requestToDir.master = ruby_system.network.slave
dma_cntrl.requestToDir.out_port = ruby_system.network.in_port
all_cntrls = l0_cntrl_nodes + \
l1_cntrl_nodes + \
@@ -277,9 +277,9 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the dma controller to the network
io_controller.mandatoryQueue = MessageBuffer()
io_controller.responseFromDir = MessageBuffer(ordered = True)
io_controller.responseFromDir.slave = ruby_system.network.master
io_controller.responseFromDir.in_port = ruby_system.network.out_port
io_controller.requestToDir = MessageBuffer()
io_controller.requestToDir.master = ruby_system.network.slave
io_controller.requestToDir.out_port = ruby_system.network.in_port
all_cntrls = all_cntrls + [io_controller]
# Register configuration with filesystem

38
configs/ruby/MESI_Two_Level.py
View File

@@ -107,18 +107,18 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the L1 controllers and the network
l1_cntrl.mandatoryQueue = MessageBuffer()
l1_cntrl.requestFromL1Cache = MessageBuffer()
l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave
l1_cntrl.requestFromL1Cache.out_port = ruby_system.network.in_port
l1_cntrl.responseFromL1Cache = MessageBuffer()
l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave
l1_cntrl.responseFromL1Cache.out_port = ruby_system.network.in_port
l1_cntrl.unblockFromL1Cache = MessageBuffer()
l1_cntrl.unblockFromL1Cache.master = ruby_system.network.slave
l1_cntrl.unblockFromL1Cache.out_port = ruby_system.network.in_port
l1_cntrl.optionalQueue = MessageBuffer()
l1_cntrl.requestToL1Cache = MessageBuffer()
l1_cntrl.requestToL1Cache.slave = ruby_system.network.master
l1_cntrl.requestToL1Cache.in_port = ruby_system.network.out_port
l1_cntrl.responseToL1Cache = MessageBuffer()
l1_cntrl.responseToL1Cache.slave = ruby_system.network.master
l1_cntrl.responseToL1Cache.in_port = ruby_system.network.out_port
l2_index_start = block_size_bits + l2_bits
@@ -141,18 +141,18 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the L2 controllers and the network
l2_cntrl.DirRequestFromL2Cache = MessageBuffer()
l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave
l2_cntrl.DirRequestFromL2Cache.out_port = ruby_system.network.in_port
l2_cntrl.L1RequestFromL2Cache = MessageBuffer()
l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
l2_cntrl.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
l2_cntrl.responseFromL2Cache = MessageBuffer()
l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
l2_cntrl.responseFromL2Cache.out_port = ruby_system.network.in_port
l2_cntrl.unblockToL2Cache = MessageBuffer()
l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master
l2_cntrl.unblockToL2Cache.in_port = ruby_system.network.out_port
l2_cntrl.L1RequestToL2Cache = MessageBuffer()
l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master
l2_cntrl.L1RequestToL2Cache.in_port = ruby_system.network.out_port
l2_cntrl.responseToL2Cache = MessageBuffer()
l2_cntrl.responseToL2Cache.slave = ruby_system.network.master
l2_cntrl.responseToL2Cache.in_port = ruby_system.network.out_port
# Run each of the ruby memory controllers at a ratio of the frequency of
@@ -170,11 +170,11 @@ def create_system(options, full_system, system, dma_ports, bootmem,
for dir_cntrl in dir_cntrl_nodes:
# Connect the directory controllers and the network
dir_cntrl.requestToDir = MessageBuffer()
dir_cntrl.requestToDir.slave = ruby_system.network.master
dir_cntrl.requestToDir.in_port = ruby_system.network.out_port
dir_cntrl.responseToDir = MessageBuffer()
dir_cntrl.responseToDir.slave = ruby_system.network.master
dir_cntrl.responseToDir.in_port = ruby_system.network.out_port
dir_cntrl.responseFromDir = MessageBuffer()
dir_cntrl.responseFromDir.master = ruby_system.network.slave
dir_cntrl.responseFromDir.out_port = ruby_system.network.in_port
dir_cntrl.requestToMemory = MessageBuffer()
dir_cntrl.responseFromMemory = MessageBuffer()
@@ -182,7 +182,7 @@ def create_system(options, full_system, system, dma_ports, bootmem,
for i, dma_port in enumerate(dma_ports):
# Create the Ruby objects associated with the dma controller
dma_seq = DMASequencer(version = i, ruby_system = ruby_system,
slave = dma_port)
in_ports = dma_port)
dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq,
transitions_per_cycle = options.ports,
@@ -194,9 +194,9 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the dma controller to the network
dma_cntrl.mandatoryQueue = MessageBuffer()
dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
dma_cntrl.responseFromDir.slave = ruby_system.network.master
dma_cntrl.responseFromDir.in_port = ruby_system.network.out_port
dma_cntrl.requestToDir = MessageBuffer()
dma_cntrl.requestToDir.master = ruby_system.network.slave
dma_cntrl.requestToDir.out_port = ruby_system.network.in_port
all_cntrls = l1_cntrl_nodes + \
l2_cntrl_nodes + \
@@ -216,9 +216,9 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the dma controller to the network
io_controller.mandatoryQueue = MessageBuffer()
io_controller.responseFromDir = MessageBuffer(ordered = True)
io_controller.responseFromDir.slave = ruby_system.network.master
io_controller.responseFromDir.in_port = ruby_system.network.out_port
io_controller.requestToDir = MessageBuffer()
io_controller.requestToDir.master = ruby_system.network.slave
io_controller.requestToDir.out_port = ruby_system.network.in_port
all_cntrls = all_cntrls + [io_controller]

28
configs/ruby/MI_example.py
View File

@@ -95,13 +95,13 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the L1 controllers and the network
l1_cntrl.mandatoryQueue = MessageBuffer()
l1_cntrl.requestFromCache = MessageBuffer(ordered = True)
l1_cntrl.requestFromCache.master = ruby_system.network.slave
l1_cntrl.requestFromCache.out_port = ruby_system.network.in_port
l1_cntrl.responseFromCache = MessageBuffer(ordered = True)
l1_cntrl.responseFromCache.master = ruby_system.network.slave
l1_cntrl.responseFromCache.out_port = ruby_system.network.in_port
l1_cntrl.forwardToCache = MessageBuffer(ordered = True)
l1_cntrl.forwardToCache.slave = ruby_system.network.master
l1_cntrl.forwardToCache.in_port = ruby_system.network.out_port
l1_cntrl.responseToCache = MessageBuffer(ordered = True)
l1_cntrl.responseToCache.slave = ruby_system.network.master
l1_cntrl.responseToCache.in_port = ruby_system.network.out_port
phys_mem_size = sum([r.size() for r in system.mem_ranges])
assert(phys_mem_size % options.num_dirs == 0)
@@ -122,16 +122,16 @@ def create_system(options, full_system, system, dma_ports, bootmem,
for dir_cntrl in dir_cntrl_nodes:
# Connect the directory controllers and the network
dir_cntrl.requestToDir = MessageBuffer(ordered = True)
dir_cntrl.requestToDir.slave = ruby_system.network.master
dir_cntrl.requestToDir.in_port = ruby_system.network.out_port
dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True)
dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master
dir_cntrl.dmaRequestToDir.in_port = ruby_system.network.out_port
dir_cntrl.responseFromDir = MessageBuffer()
dir_cntrl.responseFromDir.master = ruby_system.network.slave
dir_cntrl.responseFromDir.out_port = ruby_system.network.in_port
dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True)
dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave
dir_cntrl.dmaResponseFromDir.out_port = ruby_system.network.in_port
dir_cntrl.forwardFromDir = MessageBuffer()
dir_cntrl.forwardFromDir.master = ruby_system.network.slave
dir_cntrl.forwardFromDir.out_port = ruby_system.network.in_port
dir_cntrl.requestToMemory = MessageBuffer()
dir_cntrl.responseFromMemory = MessageBuffer()
@@ -149,15 +149,15 @@ def create_system(options, full_system, system, dma_ports, bootmem,
ruby_system = ruby_system)
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
exec("ruby_system.dma_cntrl%d.dma_sequencer.in_ports = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
# Connect the directory controllers and the network
dma_cntrl.mandatoryQueue = MessageBuffer()
dma_cntrl.requestToDir = MessageBuffer()
dma_cntrl.requestToDir.master = ruby_system.network.slave
dma_cntrl.requestToDir.out_port = ruby_system.network.in_port
dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
dma_cntrl.responseFromDir.slave = ruby_system.network.master
dma_cntrl.responseFromDir.in_port = ruby_system.network.out_port
all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
@@ -173,9 +173,9 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the dma controller to the network
io_controller.mandatoryQueue = MessageBuffer()
io_controller.requestToDir = MessageBuffer()
io_controller.requestToDir.master = ruby_system.network.slave
io_controller.requestToDir.out_port = ruby_system.network.in_port
io_controller.responseFromDir = MessageBuffer(ordered = True)
io_controller.responseFromDir.slave = ruby_system.network.master
io_controller.responseFromDir.in_port = ruby_system.network.out_port
all_cntrls = all_cntrls + [io_controller]

20
configs/ruby/MOESI_AMD_Base.py
View File

@@ -259,19 +259,19 @@ def create_system(options, full_system, system, dma_devices, bootmem,
# Connect the Directory controller to the ruby network
dir_cntrl.requestFromCores = MessageBuffer(ordered = True)
dir_cntrl.requestFromCores.slave = ruby_system.network.master
dir_cntrl.requestFromCores.in_port = ruby_system.network.out_port
dir_cntrl.responseFromCores = MessageBuffer()
dir_cntrl.responseFromCores.slave = ruby_system.network.master
dir_cntrl.responseFromCores.in_port = ruby_system.network.out_port
dir_cntrl.unblockFromCores = MessageBuffer()
dir_cntrl.unblockFromCores.slave = ruby_system.network.master
dir_cntrl.unblockFromCores.in_port = ruby_system.network.out_port
dir_cntrl.probeToCore = MessageBuffer()
dir_cntrl.probeToCore.master = ruby_system.network.slave
dir_cntrl.probeToCore.out_port = ruby_system.network.in_port
dir_cntrl.responseToCore = MessageBuffer()
dir_cntrl.responseToCore.master = ruby_system.network.slave
dir_cntrl.responseToCore.out_port = ruby_system.network.in_port
dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
@@ -305,19 +305,19 @@ def create_system(options, full_system, system, dma_devices, bootmem,
# Connect the CP controllers and the network
cp_cntrl.requestFromCore = MessageBuffer()
cp_cntrl.requestFromCore.master = ruby_system.network.slave
cp_cntrl.requestFromCore.out_port = ruby_system.network.in_port
cp_cntrl.responseFromCore = MessageBuffer()
cp_cntrl.responseFromCore.master = ruby_system.network.slave
cp_cntrl.responseFromCore.out_port = ruby_system.network.in_port
cp_cntrl.unblockFromCore = MessageBuffer()
cp_cntrl.unblockFromCore.master = ruby_system.network.slave
cp_cntrl.unblockFromCore.out_port = ruby_system.network.in_port
cp_cntrl.probeToCore = MessageBuffer()
cp_cntrl.probeToCore.slave = ruby_system.network.master
cp_cntrl.probeToCore.in_port = ruby_system.network.out_port
cp_cntrl.responseToCore = MessageBuffer()
cp_cntrl.responseToCore.slave = ruby_system.network.master
cp_cntrl.responseToCore.in_port = ruby_system.network.out_port
cp_cntrl.mandatoryQueue = MessageBuffer()
cp_cntrl.triggerQueue = MessageBuffer(ordered = True)

42
configs/ruby/MOESI_CMP_directory.py
View File

@@ -117,13 +117,13 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the L1 controllers and the network
l1_cntrl.mandatoryQueue = MessageBuffer()
l1_cntrl.requestFromL1Cache = MessageBuffer()
l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave
l1_cntrl.requestFromL1Cache.out_port = ruby_system.network.in_port
l1_cntrl.responseFromL1Cache = MessageBuffer()
l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave
l1_cntrl.responseFromL1Cache.out_port = ruby_system.network.in_port
l1_cntrl.requestToL1Cache = MessageBuffer()
l1_cntrl.requestToL1Cache.slave = ruby_system.network.master
l1_cntrl.requestToL1Cache.in_port = ruby_system.network.out_port
l1_cntrl.responseToL1Cache = MessageBuffer()
l1_cntrl.responseToL1Cache.slave = ruby_system.network.master
l1_cntrl.responseToL1Cache.in_port = ruby_system.network.out_port
l1_cntrl.triggerQueue = MessageBuffer(ordered = True)
@@ -162,18 +162,18 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the L2 controllers and the network
l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer()
l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave
l2_cntrl.GlobalRequestFromL2Cache.out_port = ruby_system.network.in_port
l2_cntrl.L1RequestFromL2Cache = MessageBuffer()
l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
l2_cntrl.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
l2_cntrl.responseFromL2Cache = MessageBuffer()
l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
l2_cntrl.responseFromL2Cache.out_port = ruby_system.network.in_port
l2_cntrl.GlobalRequestToL2Cache = MessageBuffer()
l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master
l2_cntrl.GlobalRequestToL2Cache.in_port = ruby_system.network.out_port
l2_cntrl.L1RequestToL2Cache = MessageBuffer()
l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master
l2_cntrl.L1RequestToL2Cache.in_port = ruby_system.network.out_port
l2_cntrl.responseToL2Cache = MessageBuffer()
l2_cntrl.responseToL2Cache.slave = ruby_system.network.master
l2_cntrl.responseToL2Cache.in_port = ruby_system.network.out_port
l2_cntrl.triggerQueue = MessageBuffer(ordered = True)
# Run each of the ruby memory controllers at a ratio of the frequency of
@@ -192,13 +192,13 @@ def create_system(options, full_system, system, dma_ports, bootmem,
for dir_cntrl in dir_cntrl_nodes:
# Connect the directory controllers and the network
dir_cntrl.requestToDir = MessageBuffer()
dir_cntrl.requestToDir.slave = ruby_system.network.master
dir_cntrl.requestToDir.in_port = ruby_system.network.out_port
dir_cntrl.responseToDir = MessageBuffer()
dir_cntrl.responseToDir.slave = ruby_system.network.master
dir_cntrl.responseToDir.in_port = ruby_system.network.out_port
dir_cntrl.responseFromDir = MessageBuffer()
dir_cntrl.responseFromDir.master = ruby_system.network.slave
dir_cntrl.responseFromDir.out_port = ruby_system.network.in_port
dir_cntrl.forwardFromDir = MessageBuffer()
dir_cntrl.forwardFromDir.master = ruby_system.network.slave
dir_cntrl.forwardFromDir.out_port = ruby_system.network.in_port
dir_cntrl.requestToMemory = MessageBuffer()
dir_cntrl.responseFromMemory = MessageBuffer()
dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
@@ -210,7 +210,7 @@ def create_system(options, full_system, system, dma_ports, bootmem,
#
dma_seq = DMASequencer(version = i,
ruby_system = ruby_system,
slave = dma_port)
in_ports = dma_port)
dma_cntrl = DMA_Controller(version = i,
dma_sequencer = dma_seq,
@@ -223,11 +223,11 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the dma controller to the network
dma_cntrl.mandatoryQueue = MessageBuffer()
dma_cntrl.responseFromDir = MessageBuffer()
dma_cntrl.responseFromDir.slave = ruby_system.network.master
dma_cntrl.responseFromDir.in_port = ruby_system.network.out_port
dma_cntrl.reqToDir = MessageBuffer()
dma_cntrl.reqToDir.master = ruby_system.network.slave
dma_cntrl.reqToDir.out_port = ruby_system.network.in_port
dma_cntrl.respToDir = MessageBuffer()
dma_cntrl.respToDir.master = ruby_system.network.slave
dma_cntrl.respToDir.out_port = ruby_system.network.in_port
dma_cntrl.triggerQueue = MessageBuffer(ordered = True)
@@ -248,11 +248,11 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the dma controller to the network
io_controller.mandatoryQueue = MessageBuffer()
io_controller.responseFromDir = MessageBuffer()
io_controller.responseFromDir.slave = ruby_system.network.master
io_controller.responseFromDir.in_port = ruby_system.network.out_port
io_controller.reqToDir = MessageBuffer()
io_controller.reqToDir.master = ruby_system.network.slave
io_controller.reqToDir.out_port = ruby_system.network.in_port
io_controller.respToDir = MessageBuffer()
io_controller.respToDir.master = ruby_system.network.slave
io_controller.respToDir.out_port = ruby_system.network.in_port
io_controller.triggerQueue = MessageBuffer(ordered = True)
all_cntrls = all_cntrls + [io_controller]

52
configs/ruby/MOESI_CMP_token.py
View File

@@ -124,19 +124,19 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the L1 controllers and the network
l1_cntrl.requestFromL1Cache = MessageBuffer()
l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave
l1_cntrl.requestFromL1Cache.out_port = ruby_system.network.in_port
l1_cntrl.responseFromL1Cache = MessageBuffer()
l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave
l1_cntrl.responseFromL1Cache.out_port = ruby_system.network.in_port
l1_cntrl.persistentFromL1Cache = MessageBuffer(ordered = True)
l1_cntrl.persistentFromL1Cache.master = ruby_system.network.slave
l1_cntrl.persistentFromL1Cache.out_port = ruby_system.network.in_port
l1_cntrl.mandatoryQueue = MessageBuffer()
l1_cntrl.requestToL1Cache = MessageBuffer()
l1_cntrl.requestToL1Cache.slave = ruby_system.network.master
l1_cntrl.requestToL1Cache.in_port = ruby_system.network.out_port
l1_cntrl.responseToL1Cache = MessageBuffer()
l1_cntrl.responseToL1Cache.slave = ruby_system.network.master
l1_cntrl.responseToL1Cache.in_port = ruby_system.network.out_port
l1_cntrl.persistentToL1Cache = MessageBuffer(ordered = True)
l1_cntrl.persistentToL1Cache.slave = ruby_system.network.master
l1_cntrl.persistentToL1Cache.in_port = ruby_system.network.out_port
l2_index_start = block_size_bits + l2_bits
@@ -160,20 +160,20 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the L2 controllers and the network
l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer()
l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave
l2_cntrl.GlobalRequestFromL2Cache.out_port = ruby_system.network.in_port
l2_cntrl.L1RequestFromL2Cache = MessageBuffer()
l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
l2_cntrl.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
l2_cntrl.responseFromL2Cache = MessageBuffer()
l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
l2_cntrl.responseFromL2Cache.out_port = ruby_system.network.in_port
l2_cntrl.GlobalRequestToL2Cache = MessageBuffer()
l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master
l2_cntrl.GlobalRequestToL2Cache.in_port = ruby_system.network.out_port
l2_cntrl.L1RequestToL2Cache = MessageBuffer()
l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master
l2_cntrl.L1RequestToL2Cache.in_port = ruby_system.network.out_port
l2_cntrl.responseToL2Cache = MessageBuffer()
l2_cntrl.responseToL2Cache.slave = ruby_system.network.master
l2_cntrl.responseToL2Cache.in_port = ruby_system.network.out_port
l2_cntrl.persistentToL2Cache = MessageBuffer(ordered = True)
l2_cntrl.persistentToL2Cache.slave = ruby_system.network.master
l2_cntrl.persistentToL2Cache.in_port = ruby_system.network.out_port
# Run each of the ruby memory controllers at a ratio of the frequency of
@@ -192,22 +192,22 @@ def create_system(options, full_system, system, dma_ports, bootmem,
dir_cntrl.l2_select_num_bits = l2_bits
# Connect the directory controllers and the network
dir_cntrl.requestToDir = MessageBuffer()
dir_cntrl.requestToDir.slave = ruby_system.network.master
dir_cntrl.requestToDir.in_port = ruby_system.network.out_port
dir_cntrl.responseToDir = MessageBuffer()
dir_cntrl.responseToDir.slave = ruby_system.network.master
dir_cntrl.responseToDir.in_port = ruby_system.network.out_port
dir_cntrl.persistentToDir = MessageBuffer(ordered = True)
dir_cntrl.persistentToDir.slave = ruby_system.network.master
dir_cntrl.persistentToDir.in_port = ruby_system.network.out_port
dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True)
dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master
dir_cntrl.dmaRequestToDir.in_port = ruby_system.network.out_port
dir_cntrl.requestFromDir = MessageBuffer()
dir_cntrl.requestFromDir.master = ruby_system.network.slave
dir_cntrl.requestFromDir.out_port = ruby_system.network.in_port
dir_cntrl.responseFromDir = MessageBuffer()
dir_cntrl.responseFromDir.master = ruby_system.network.slave
dir_cntrl.responseFromDir.out_port = ruby_system.network.in_port
dir_cntrl.persistentFromDir = MessageBuffer(ordered = True)
dir_cntrl.persistentFromDir.master = ruby_system.network.slave
dir_cntrl.persistentFromDir.out_port = ruby_system.network.in_port
dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True)
dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave
dir_cntrl.dmaResponseFromDir.out_port = ruby_system.network.in_port
dir_cntrl.requestToMemory = MessageBuffer()
dir_cntrl.responseFromMemory = MessageBuffer()
@@ -218,7 +218,7 @@ def create_system(options, full_system, system, dma_ports, bootmem,
#
dma_seq = DMASequencer(version = i,
ruby_system = ruby_system,
slave = dma_port)
in_ports = dma_port)
dma_cntrl = DMA_Controller(version = i,
dma_sequencer = dma_seq,
@@ -231,9 +231,9 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the dma controller to the network
dma_cntrl.mandatoryQueue = MessageBuffer()
dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
dma_cntrl.responseFromDir.slave = ruby_system.network.master
dma_cntrl.responseFromDir.in_port = ruby_system.network.out_port
dma_cntrl.reqToDirectory = MessageBuffer()
dma_cntrl.reqToDirectory.master = ruby_system.network.slave
dma_cntrl.reqToDirectory.out_port = ruby_system.network.in_port
all_cntrls = l1_cntrl_nodes + \
l2_cntrl_nodes + \
@@ -252,9 +252,9 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the dma controller to the network
io_controller.mandatoryQueue = MessageBuffer()
io_controller.responseFromDir = MessageBuffer(ordered = True)
io_controller.responseFromDir.slave = ruby_system.network.master
io_controller.responseFromDir.in_port = ruby_system.network.out_port
io_controller.reqToDirectory = MessageBuffer()
io_controller.reqToDirectory.master = ruby_system.network.slave
io_controller.reqToDirectory.out_port = ruby_system.network.in_port
all_cntrls = all_cntrls + [io_controller]

34
configs/ruby/MOESI_hammer.py
View File

@@ -116,20 +116,20 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the L1 controller and the network
# Connect the buffers from the controller to network
l1_cntrl.requestFromCache = MessageBuffer()
l1_cntrl.requestFromCache.master = ruby_system.network.slave
l1_cntrl.requestFromCache.out_port = ruby_system.network.in_port
l1_cntrl.responseFromCache = MessageBuffer()
l1_cntrl.responseFromCache.master = ruby_system.network.slave
l1_cntrl.responseFromCache.out_port = ruby_system.network.in_port
l1_cntrl.unblockFromCache = MessageBuffer()
l1_cntrl.unblockFromCache.master = ruby_system.network.slave
l1_cntrl.unblockFromCache.out_port = ruby_system.network.in_port
l1_cntrl.triggerQueue = MessageBuffer()
# Connect the buffers from the network to the controller
l1_cntrl.mandatoryQueue = MessageBuffer()
l1_cntrl.forwardToCache = MessageBuffer()
l1_cntrl.forwardToCache.slave = ruby_system.network.master
l1_cntrl.forwardToCache.in_port = ruby_system.network.out_port
l1_cntrl.responseToCache = MessageBuffer()
l1_cntrl.responseToCache.slave = ruby_system.network.master
l1_cntrl.responseToCache.in_port = ruby_system.network.out_port
#
@@ -180,22 +180,22 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the directory controller to the network
dir_cntrl.forwardFromDir = MessageBuffer()
dir_cntrl.forwardFromDir.master = ruby_system.network.slave
dir_cntrl.forwardFromDir.out_port = ruby_system.network.in_port
dir_cntrl.responseFromDir = MessageBuffer()
dir_cntrl.responseFromDir.master = ruby_system.network.slave
dir_cntrl.responseFromDir.out_port = ruby_system.network.in_port
dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True)
dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave
dir_cntrl.dmaResponseFromDir.out_port = ruby_system.network.in_port
dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
dir_cntrl.unblockToDir = MessageBuffer()
dir_cntrl.unblockToDir.slave = ruby_system.network.master
dir_cntrl.unblockToDir.in_port = ruby_system.network.out_port
dir_cntrl.responseToDir = MessageBuffer()
dir_cntrl.responseToDir.slave = ruby_system.network.master
dir_cntrl.responseToDir.in_port = ruby_system.network.out_port
dir_cntrl.requestToDir = MessageBuffer()
dir_cntrl.requestToDir.slave = ruby_system.network.master
dir_cntrl.requestToDir.in_port = ruby_system.network.out_port
dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True)
dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master
dir_cntrl.dmaRequestToDir.in_port = ruby_system.network.out_port
dir_cntrl.requestToMemory = MessageBuffer()
dir_cntrl.responseFromMemory = MessageBuffer()
@@ -206,7 +206,7 @@ def create_system(options, full_system, system, dma_ports, bootmem,
#
dma_seq = DMASequencer(version = i,
ruby_system = ruby_system,
slave = dma_port)
in_ports = dma_port)
dma_cntrl = DMA_Controller(version = i,
dma_sequencer = dma_seq,
@@ -221,9 +221,9 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the dma controller to the network
dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
dma_cntrl.responseFromDir.slave = ruby_system.network.master
dma_cntrl.responseFromDir.in_port = ruby_system.network.out_port
dma_cntrl.requestToDir = MessageBuffer()
dma_cntrl.requestToDir.master = ruby_system.network.slave
dma_cntrl.requestToDir.out_port = ruby_system.network.in_port
dma_cntrl.mandatoryQueue = MessageBuffer()
all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
@@ -239,9 +239,9 @@ def create_system(options, full_system, system, dma_ports, bootmem,
# Connect the dma controller to the network
io_controller.responseFromDir = MessageBuffer(ordered = True)
io_controller.responseFromDir.slave = ruby_system.network.master
io_controller.responseFromDir.in_port = ruby_system.network.out_port
io_controller.requestToDir = MessageBuffer()
io_controller.requestToDir.master = ruby_system.network.slave
io_controller.requestToDir.out_port = ruby_system.network.in_port
io_controller.mandatoryQueue = MessageBuffer()
all_cntrls = all_cntrls + [io_controller]

8
configs/ruby/Ruby.py
View File

@@ -130,7 +130,7 @@ def setup_memory_controllers(system, ruby, dir_cntrls, options):
if len(system.mem_ranges) > 1:
crossbar = IOXBar()
crossbars.append(crossbar)
dir_cntrl.memory = crossbar.slave
dir_cntrl.memory = crossbar.cpu_side_ports
dir_ranges = []
for r in system.mem_ranges:
@@ -150,7 +150,7 @@ def setup_memory_controllers(system, ruby, dir_cntrls, options):
dir_ranges.append(dram_intf.range)
if crossbar != None:
mem_ctrl.port = crossbar.master
mem_ctrl.port = crossbar.mem_side_ports
else:
mem_ctrl.port = dir_cntrl.memory
@@ -223,14 +223,14 @@ def create_system(options, full_system, system, piobus = None, dma_ports = [],
# part (i.e. here).
sys_port_proxy = RubyPortProxy(ruby_system = ruby)
if piobus is not None:
sys_port_proxy.pio_master_port = piobus.slave
sys_port_proxy.pio_request_port = piobus.cpu_side_ports
# Give the system port proxy a SimObject parent without creating a
# full-fledged controller
system.sys_port_proxy = sys_port_proxy
# Connect the system port for loading of binaries etc
system.system_port = system.sys_port_proxy.slave
system.system_port = system.sys_port_proxy.in_ports
setup_memory_controllers(system, ruby, dir_cntrls, options)