e1db67c4bd
This commit contains the rest of the base 2 vs base 10 cache/memory size clarifications. It also changes the warning message to use warn(). With these changes, the warning message should now no longer show up during a fresh compilation of gem5. Change-Id: Ia63f841bdf045b76473437f41548fab27dc19631
805 lines
26 KiB
Python
805 lines
26 KiB
Python
# Copyright (c) 2021-2023 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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"""
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Definitions for CHI nodes and controller types. These are used by
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create_system in configs/ruby/CHI.py or may be used in custom configuration
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scripts. When used with create_system, the user may provide an additional
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configuration file as the --chi-config parameter to specialize the classes
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defined here.
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When using the CustomMesh topology, --chi-config must be provided with
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specialization of the NoC_Param classes defining the NoC dimensions and
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node to router binding. See configs/example/noc_config/2x4.py for an example.
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"""
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import math
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import m5
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from m5.objects import *
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class Versions:
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"""
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Helper class to obtain unique ids for a given controller class.
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These are passed as the 'version' parameter when creating the controller.
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"""
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_seqs = 0
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@classmethod
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def getSeqId(cls):
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val = cls._seqs
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cls._seqs += 1
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return val
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_version = {}
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@classmethod
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def getVersion(cls, tp):
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if tp not in cls._version:
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cls._version[tp] = 0
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val = cls._version[tp]
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cls._version[tp] = val + 1
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return val
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class NoC_Params:
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"""
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Default parameters for the interconnect. The value of data_width is
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also used to set the data_channel_size for all CHI controllers.
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(see configs/ruby/CHI.py)
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"""
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router_link_latency = 1
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node_link_latency = 1
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router_latency = 1
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router_buffer_size = 4
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cntrl_msg_size = 8
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data_width = 32
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cross_links = []
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cross_link_latency = 0
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class CHI_Node(SubSystem):
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"""
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Base class with common functions for setting up Cache or Memory
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controllers that are part of a CHI RNF, RNFI, HNF, or SNF nodes.
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Notice getNetworkSideControllers and getAllControllers must be implemented
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in the derived classes.
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"""
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class NoC_Params:
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"""
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NoC config. parameters and bindings required for CustomMesh topology.
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Maps 'num_nodes_per_router' CHI nodes to each router provided in
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'router_list'. This assumes len(router_list)*num_nodes_per_router
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equals the number of nodes
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If 'num_nodes_per_router' is left undefined, we circulate around
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'router_list' until all nodes are mapped.
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See 'distributeNodes' in configs/topologies/CustomMesh.py
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"""
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num_nodes_per_router = None
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router_list = None
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def __init__(self, ruby_system):
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super().__init__()
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self._ruby_system = ruby_system
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self._network = ruby_system.network
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def getNetworkSideControllers(self):
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"""
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Returns all ruby controllers that need to be connected to the
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network
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"""
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raise NotImplementedError()
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def getAllControllers(self):
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"""
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Returns all ruby controllers associated with this node
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"""
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raise NotImplementedError()
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def setDownstream(self, cntrls):
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"""
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Sets cntrls as the downstream list of all controllers in this node
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"""
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for c in self.getNetworkSideControllers():
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c.downstream_destinations = cntrls
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def connectController(self, cntrl):
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"""
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Creates and configures the messages buffers for the CHI input/output
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ports that connect to the network
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"""
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cntrl.reqOut = MessageBuffer()
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cntrl.rspOut = MessageBuffer()
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cntrl.snpOut = MessageBuffer()
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cntrl.datOut = MessageBuffer()
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cntrl.reqIn = MessageBuffer()
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cntrl.rspIn = MessageBuffer()
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cntrl.snpIn = MessageBuffer()
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cntrl.datIn = MessageBuffer()
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# All CHI ports are always connected to the network.
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# Controllers that are not part of the getNetworkSideControllers list
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# still communicate using internal routers, thus we need to wire-up the
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# ports
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cntrl.reqOut.out_port = self._network.in_port
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cntrl.rspOut.out_port = self._network.in_port
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cntrl.snpOut.out_port = self._network.in_port
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cntrl.datOut.out_port = self._network.in_port
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cntrl.reqIn.in_port = self._network.out_port
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cntrl.rspIn.in_port = self._network.out_port
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cntrl.snpIn.in_port = self._network.out_port
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cntrl.datIn.in_port = self._network.out_port
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class TriggerMessageBuffer(MessageBuffer):
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"""
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MessageBuffer for triggering internal controller events.
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These buffers should not be affected by the Ruby tester randomization
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and allow poping messages enqueued in the same cycle.
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"""
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randomization = "disabled"
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allow_zero_latency = True
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class OrderedTriggerMessageBuffer(TriggerMessageBuffer):
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ordered = True
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class MemCtrlMessageBuffer(MessageBuffer):
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"""
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MessageBuffer exchanging messages with the memory
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These buffers should also not be affected by the Ruby tester randomization.
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"""
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randomization = "disabled"
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ordered = True
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class CHI_Cache_Controller(Cache_Controller):
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"""
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Default parameters for a Cache controller
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The Cache_Controller can also be used as a DMA requester or as
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a pure directory if all cache allocation policies are disabled.
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"""
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def __init__(self, ruby_system):
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super().__init__(
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version=Versions.getVersion(Cache_Controller),
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ruby_system=ruby_system,
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mandatoryQueue=MessageBuffer(),
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prefetchQueue=MessageBuffer(),
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triggerQueue=TriggerMessageBuffer(),
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retryTriggerQueue=OrderedTriggerMessageBuffer(),
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replTriggerQueue=OrderedTriggerMessageBuffer(),
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reqRdy=TriggerMessageBuffer(),
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snpRdy=TriggerMessageBuffer(),
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)
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# Set somewhat large number since we really a lot on internal
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# triggers. To limit the controller performance, tweak other
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# params such as: input port buffer size, cache banks, and output
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# port latency
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self.transitions_per_cycle = 1024
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# This should be set to true in the data cache controller to enable
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# timeouts on unique lines when a store conditional fails
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self.sc_lock_enabled = False
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class CHI_L1Controller(CHI_Cache_Controller):
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"""
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Default parameters for a L1 Cache controller
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"""
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def __init__(self, ruby_system, sequencer, cache, prefetcher):
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super().__init__(ruby_system)
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self.sequencer = sequencer
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self.cache = cache
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self.prefetcher = prefetcher
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self.use_prefetcher = prefetcher != NULL
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self.send_evictions = True
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self.is_HN = False
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self.enable_DMT = False
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self.enable_DCT = False
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# Strict inclusive MOESI
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self.allow_SD = True
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self.alloc_on_seq_acc = True
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self.alloc_on_seq_line_write = False
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self.alloc_on_readshared = True
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self.alloc_on_readunique = True
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self.alloc_on_readonce = True
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self.alloc_on_writeback = True
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self.alloc_on_atomic = False
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self.dealloc_on_unique = False
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self.dealloc_on_shared = False
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self.dealloc_backinv_unique = True
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self.dealloc_backinv_shared = True
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# Some reasonable default TBE params
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self.number_of_TBEs = 16
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self.number_of_repl_TBEs = 16
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self.number_of_snoop_TBEs = 4
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self.number_of_DVM_TBEs = 16
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self.number_of_DVM_snoop_TBEs = 4
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self.unify_repl_TBEs = False
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class CHI_L2Controller(CHI_Cache_Controller):
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"""
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Default parameters for a L2 Cache controller
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"""
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def __init__(self, ruby_system, cache, prefetcher):
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super().__init__(ruby_system)
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self.sequencer = NULL
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self.cache = cache
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self.prefetcher = prefetcher
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self.use_prefetcher = prefetcher != NULL
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self.allow_SD = True
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self.is_HN = False
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self.enable_DMT = False
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self.enable_DCT = False
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self.send_evictions = False
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# Strict inclusive MOESI
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self.alloc_on_seq_acc = False
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self.alloc_on_seq_line_write = False
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self.alloc_on_readshared = True
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self.alloc_on_readunique = True
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self.alloc_on_readonce = True
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self.alloc_on_writeback = True
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self.alloc_on_atomic = False
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self.dealloc_on_unique = False
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self.dealloc_on_shared = False
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self.dealloc_backinv_unique = True
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self.dealloc_backinv_shared = True
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# Some reasonable default TBE params
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self.number_of_TBEs = 32
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self.number_of_repl_TBEs = 32
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self.number_of_snoop_TBEs = 16
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self.number_of_DVM_TBEs = 1 # should not receive any dvm
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self.number_of_DVM_snoop_TBEs = 1 # should not receive any dvm
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self.unify_repl_TBEs = False
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class CHI_HNFController(CHI_Cache_Controller):
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"""
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Default parameters for a coherent home node (HNF) cache controller
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"""
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def __init__(self, ruby_system, cache, prefetcher, addr_ranges):
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super().__init__(ruby_system)
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self.sequencer = NULL
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self.cache = cache
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self.prefetcher = prefetcher
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self.use_prefetcher = prefetcher != NULL
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self.addr_ranges = addr_ranges
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self.allow_SD = True
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self.is_HN = True
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self.enable_DMT = True
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self.enable_DCT = True
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self.send_evictions = False
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# MOESI / Mostly inclusive for shared / Exclusive for unique
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self.alloc_on_seq_acc = False
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self.alloc_on_seq_line_write = False
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self.alloc_on_readshared = True
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self.alloc_on_readunique = False
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self.alloc_on_readonce = True
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self.alloc_on_writeback = True
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self.alloc_on_atomic = True
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self.dealloc_on_unique = True
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self.dealloc_on_shared = False
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self.dealloc_backinv_unique = False
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self.dealloc_backinv_shared = False
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# Some reasonable default TBE params
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self.number_of_TBEs = 32
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self.number_of_repl_TBEs = 32
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self.number_of_snoop_TBEs = 1 # should not receive any snoop
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self.number_of_DVM_TBEs = 1 # should not receive any dvm
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self.number_of_DVM_snoop_TBEs = 1 # should not receive any dvm
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self.unify_repl_TBEs = False
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class CHI_MNController(MiscNode_Controller):
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"""
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Default parameters for a Misc Node
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"""
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def __init__(
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self, ruby_system, addr_range, l1d_caches, early_nonsync_comp
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):
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super().__init__(
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version=Versions.getVersion(MiscNode_Controller),
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ruby_system=ruby_system,
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mandatoryQueue=MessageBuffer(),
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triggerQueue=TriggerMessageBuffer(),
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retryTriggerQueue=TriggerMessageBuffer(),
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schedRspTriggerQueue=TriggerMessageBuffer(),
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reqRdy=TriggerMessageBuffer(),
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snpRdy=TriggerMessageBuffer(),
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)
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# Set somewhat large number since we really a lot on internal
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# triggers. To limit the controller performance, tweak other
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# params such as: input port buffer size, cache banks, and output
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# port latency
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self.transitions_per_cycle = 1024
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self.addr_ranges = [addr_range]
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# 16 total transaction buffer entries, but 1 is reserved for DVMNonSync
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self.number_of_DVM_TBEs = 16
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self.number_of_non_sync_TBEs = 1
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self.early_nonsync_comp = early_nonsync_comp
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# "upstream_destinations" = targets for DVM snoops
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self.upstream_destinations = l1d_caches
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class CHI_DMAController(CHI_Cache_Controller):
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"""
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Default parameters for a DMA controller
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"""
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def __init__(self, ruby_system, sequencer):
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super().__init__(ruby_system)
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self.sequencer = sequencer
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class DummyCache(RubyCache):
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dataAccessLatency = 0
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tagAccessLatency = 1
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size = "128"
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assoc = 1
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self.prefetcher = NULL
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self.use_prefetcher = False
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self.cache = DummyCache()
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self.sequencer.dcache = NULL
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# All allocations are false
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# Deallocations are true (don't really matter)
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self.allow_SD = False
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self.is_HN = False
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self.enable_DMT = False
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self.enable_DCT = False
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self.alloc_on_seq_acc = False
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self.alloc_on_seq_line_write = False
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self.alloc_on_readshared = False
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self.alloc_on_readunique = False
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self.alloc_on_readonce = False
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self.alloc_on_writeback = False
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self.alloc_on_atomic = False
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self.dealloc_on_unique = False
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self.dealloc_on_shared = False
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self.dealloc_backinv_unique = False
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self.dealloc_backinv_shared = False
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self.send_evictions = False
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self.number_of_TBEs = 16
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self.number_of_repl_TBEs = 1
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self.number_of_snoop_TBEs = 1 # should not receive any snoop
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self.number_of_DVM_TBEs = 1 # should not receive any dvm
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self.number_of_DVM_snoop_TBEs = 1 # should not receive any dvm
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self.unify_repl_TBEs = False
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class CPUSequencerWrapper:
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"""
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Other generic configuration scripts assume a matching number of sequencers
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and cpus. This wraps the instruction and data sequencer so they are
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compatible with the other scripts. This assumes all scripts are using
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connectCpuPorts/connectIOPorts to bind ports
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"""
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def __init__(self, iseq, dseq):
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# use this style due to __setattr__ override below
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self.__dict__["inst_seq"] = iseq
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self.__dict__["data_seq"] = dseq
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self.__dict__["support_data_reqs"] = True
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self.__dict__["support_inst_reqs"] = True
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# Compatibility with certain scripts that wire up ports
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# without connectCpuPorts
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self.__dict__["in_ports"] = dseq.in_ports
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def connectCpuPorts(self, cpu):
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assert isinstance(cpu, BaseCPU)
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cpu.icache_port = self.inst_seq.in_ports
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for p in cpu._cached_ports:
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if str(p) != "icache_port":
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exec(f"cpu.{p} = self.data_seq.in_ports")
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cpu.connectUncachedPorts(
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self.data_seq.in_ports, self.data_seq.interrupt_out_port
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)
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def connectIOPorts(self, piobus):
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self.data_seq.connectIOPorts(piobus)
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def __setattr__(self, name, value):
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setattr(self.inst_seq, name, value)
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setattr(self.data_seq, name, value)
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class CHI_RNF(CHI_Node):
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"""
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Defines a CHI request node.
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Notice all contollers and sequencers are set as children of the cpus, so
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this object acts more like a proxy for seting things up and has no topology
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significance unless the cpus are set as its children at the top level
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"""
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def __init__(
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self,
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cpus,
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ruby_system,
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l1Icache_type,
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l1Dcache_type,
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cache_line_size,
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l1Iprefetcher_type=None,
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l1Dprefetcher_type=None,
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):
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super().__init__(ruby_system)
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self._block_size_bits = int(math.log(cache_line_size, 2))
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# All sequencers and controllers
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self._seqs = []
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self._cntrls = []
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# Last level controllers in this node, i.e., the ones that will send
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# requests to the home nodes
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self._ll_cntrls = []
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self._cpus = cpus
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# First creates L1 caches and sequencers
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for cpu in self._cpus:
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cpu.inst_sequencer = RubySequencer(
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version=Versions.getSeqId(), ruby_system=ruby_system
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)
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cpu.data_sequencer = RubySequencer(
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version=Versions.getSeqId(), ruby_system=ruby_system
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)
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self._seqs.append(
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CPUSequencerWrapper(cpu.inst_sequencer, cpu.data_sequencer)
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)
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# caches
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l1i_cache = l1Icache_type(
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start_index_bit=self._block_size_bits, is_icache=True
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)
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l1d_cache = l1Dcache_type(
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start_index_bit=self._block_size_bits, is_icache=False
|
|
)
|
|
|
|
# prefetcher wrappers
|
|
if l1Iprefetcher_type != None:
|
|
l1i_pf = l1Iprefetcher_type()
|
|
else:
|
|
l1i_pf = NULL
|
|
|
|
if l1Dprefetcher_type != None:
|
|
l1d_pf = l1Dprefetcher_type()
|
|
else:
|
|
l1d_pf = NULL
|
|
|
|
# cache controllers
|
|
cpu.l1i = CHI_L1Controller(
|
|
ruby_system, cpu.inst_sequencer, l1i_cache, l1i_pf
|
|
)
|
|
|
|
cpu.l1d = CHI_L1Controller(
|
|
ruby_system, cpu.data_sequencer, l1d_cache, l1d_pf
|
|
)
|
|
|
|
cpu.inst_sequencer.dcache = NULL
|
|
cpu.data_sequencer.dcache = cpu.l1d.cache
|
|
|
|
cpu.l1d.sc_lock_enabled = True
|
|
|
|
cpu._ll_cntrls = [cpu.l1i, cpu.l1d]
|
|
for c in cpu._ll_cntrls:
|
|
self._cntrls.append(c)
|
|
self.connectController(c)
|
|
self._ll_cntrls.append(c)
|
|
|
|
def getSequencers(self):
|
|
return self._seqs
|
|
|
|
def getAllControllers(self):
|
|
return self._cntrls
|
|
|
|
def getNetworkSideControllers(self):
|
|
return self._cntrls
|
|
|
|
def setDownstream(self, cntrls):
|
|
for c in self._ll_cntrls:
|
|
c.downstream_destinations = cntrls
|
|
|
|
def getCpus(self):
|
|
return self._cpus
|
|
|
|
# Adds a private L2 for each cpu
|
|
def addPrivL2Cache(self, cache_type, pf_type=None):
|
|
self._ll_cntrls = []
|
|
for cpu in self._cpus:
|
|
l2_cache = cache_type(
|
|
start_index_bit=self._block_size_bits, is_icache=False
|
|
)
|
|
|
|
if pf_type != None:
|
|
l2_pf = pf_type()
|
|
else:
|
|
l2_pf = NULL
|
|
|
|
cpu.l2 = CHI_L2Controller(self._ruby_system, l2_cache, l2_pf)
|
|
|
|
self._cntrls.append(cpu.l2)
|
|
self.connectController(cpu.l2)
|
|
|
|
self._ll_cntrls.append(cpu.l2)
|
|
|
|
for c in cpu._ll_cntrls:
|
|
c.downstream_destinations = [cpu.l2]
|
|
cpu._ll_cntrls = [cpu.l2]
|
|
|
|
|
|
class CHI_HNF(CHI_Node):
|
|
"""
|
|
Encapsulates an HNF cache/directory controller.
|
|
Before the first controller is created, the class method
|
|
CHI_HNF.createAddrRanges must be called before creating any CHI_HNF object
|
|
to set-up the interleaved address ranges used by the HNFs
|
|
"""
|
|
|
|
class NoC_Params(CHI_Node.NoC_Params):
|
|
"""HNFs may also define the 'pairing' parameter to allow pairing"""
|
|
|
|
pairing = None
|
|
|
|
_addr_ranges = {}
|
|
|
|
@classmethod
|
|
def createAddrRanges(cls, sys_mem_ranges, cache_line_size, hnfs):
|
|
# Create the HNFs interleaved addr ranges
|
|
block_size_bits = int(math.log(cache_line_size, 2))
|
|
llc_bits = int(math.log(len(hnfs), 2))
|
|
numa_bit = block_size_bits + llc_bits - 1
|
|
for i, hnf in enumerate(hnfs):
|
|
ranges = []
|
|
for r in sys_mem_ranges:
|
|
addr_range = AddrRange(
|
|
r.start,
|
|
size=r.size(),
|
|
intlvHighBit=numa_bit,
|
|
intlvBits=llc_bits,
|
|
intlvMatch=i,
|
|
)
|
|
ranges.append(addr_range)
|
|
cls._addr_ranges[hnf] = (ranges, numa_bit)
|
|
|
|
@classmethod
|
|
def getAddrRanges(cls, hnf_idx):
|
|
assert len(cls._addr_ranges) != 0
|
|
return cls._addr_ranges[hnf_idx]
|
|
|
|
# The CHI controller can be a child of this object or another if
|
|
# 'parent' if specified
|
|
def __init__(self, hnf_idx, ruby_system, llcache_type, parent):
|
|
super().__init__(ruby_system)
|
|
|
|
addr_ranges, intlvHighBit = self.getAddrRanges(hnf_idx)
|
|
# All ranges should have the same interleaving
|
|
assert len(addr_ranges) >= 1
|
|
|
|
ll_cache = llcache_type(start_index_bit=intlvHighBit + 1)
|
|
self._cntrl = CHI_HNFController(
|
|
ruby_system, ll_cache, NULL, addr_ranges
|
|
)
|
|
|
|
if parent == None:
|
|
self.cntrl = self._cntrl
|
|
else:
|
|
parent.cntrl = self._cntrl
|
|
|
|
self.connectController(self._cntrl)
|
|
|
|
def getAllControllers(self):
|
|
return [self._cntrl]
|
|
|
|
def getNetworkSideControllers(self):
|
|
return [self._cntrl]
|
|
|
|
|
|
class CHI_MN(CHI_Node):
|
|
"""
|
|
Encapsulates a Misc Node controller.
|
|
"""
|
|
|
|
class NoC_Params(CHI_Node.NoC_Params):
|
|
"""HNFs may also define the 'pairing' parameter to allow pairing"""
|
|
|
|
pairing = None
|
|
|
|
# The CHI controller can be a child of this object or another if
|
|
# 'parent' if specified
|
|
def __init__(self, ruby_system, l1d_caches, early_nonsync_comp=False):
|
|
super().__init__(ruby_system)
|
|
|
|
# MiscNode has internal address range starting at 0
|
|
addr_range = AddrRange(0, size="1KiB")
|
|
|
|
self._cntrl = CHI_MNController(
|
|
ruby_system, addr_range, l1d_caches, early_nonsync_comp
|
|
)
|
|
|
|
self.cntrl = self._cntrl
|
|
|
|
self.connectController(self._cntrl)
|
|
|
|
def connectController(self, cntrl):
|
|
CHI_Node.connectController(self, cntrl)
|
|
|
|
def getAllControllers(self):
|
|
return [self._cntrl]
|
|
|
|
def getNetworkSideControllers(self):
|
|
return [self._cntrl]
|
|
|
|
|
|
class CHI_SNF_Base(CHI_Node):
|
|
"""
|
|
Creates CHI node controllers for the memory controllers
|
|
"""
|
|
|
|
# The CHI controller can be a child of this object or another if
|
|
# 'parent' if specified
|
|
def __init__(self, ruby_system, parent):
|
|
super().__init__(ruby_system)
|
|
|
|
self._cntrl = Memory_Controller(
|
|
version=Versions.getVersion(Memory_Controller),
|
|
ruby_system=ruby_system,
|
|
triggerQueue=TriggerMessageBuffer(),
|
|
responseFromMemory=MemCtrlMessageBuffer(),
|
|
requestToMemory=MemCtrlMessageBuffer(),
|
|
reqRdy=TriggerMessageBuffer(),
|
|
transitions_per_cycle=1024,
|
|
)
|
|
|
|
# The Memory_Controller implementation deallocates the TBE for
|
|
# write requests when they are queue up to memory. The size of this
|
|
# buffer must be limited to prevent unlimited outstanding writes.
|
|
self._cntrl.requestToMemory.buffer_size = (
|
|
int(self._cntrl.to_memory_controller_latency) + 1
|
|
)
|
|
|
|
self.connectController(self._cntrl)
|
|
|
|
if parent:
|
|
parent.cntrl = self._cntrl
|
|
else:
|
|
self.cntrl = self._cntrl
|
|
|
|
def getAllControllers(self):
|
|
return [self._cntrl]
|
|
|
|
def getNetworkSideControllers(self):
|
|
return [self._cntrl]
|
|
|
|
def getMemRange(self, mem_ctrl):
|
|
# TODO need some kind of transparent API for
|
|
# MemCtrl+DRAM vs SimpleMemory
|
|
if hasattr(mem_ctrl, "range"):
|
|
return mem_ctrl.range
|
|
else:
|
|
return mem_ctrl.dram.range
|
|
|
|
|
|
class CHI_SNF_BootMem(CHI_SNF_Base):
|
|
"""
|
|
Create the SNF for the boot memory
|
|
"""
|
|
|
|
def __init__(self, ruby_system, parent, bootmem):
|
|
super().__init__(ruby_system, parent)
|
|
self._cntrl.memory_out_port = bootmem.port
|
|
self._cntrl.addr_ranges = self.getMemRange(bootmem)
|
|
|
|
|
|
class CHI_SNF_MainMem(CHI_SNF_Base):
|
|
"""
|
|
Create the SNF for a list main memory controllers
|
|
"""
|
|
|
|
def __init__(self, ruby_system, parent, mem_ctrl=None):
|
|
super().__init__(ruby_system, parent)
|
|
if mem_ctrl:
|
|
self._cntrl.memory_out_port = mem_ctrl.port
|
|
self._cntrl.addr_ranges = self.getMemRange(mem_ctrl)
|
|
# else bind ports and range later
|
|
|
|
|
|
class CHI_RNI_Base(CHI_Node):
|
|
"""
|
|
Request node without cache / DMA
|
|
"""
|
|
|
|
# The CHI controller can be a child of this object or another if
|
|
# 'parent' if specified
|
|
def __init__(self, ruby_system, parent):
|
|
super().__init__(ruby_system)
|
|
|
|
self._sequencer = RubySequencer(
|
|
version=Versions.getSeqId(),
|
|
ruby_system=ruby_system,
|
|
clk_domain=ruby_system.clk_domain,
|
|
)
|
|
self._cntrl = CHI_DMAController(ruby_system, self._sequencer)
|
|
|
|
if parent:
|
|
parent.cntrl = self._cntrl
|
|
else:
|
|
self.cntrl = self._cntrl
|
|
|
|
self.connectController(self._cntrl)
|
|
|
|
def getAllControllers(self):
|
|
return [self._cntrl]
|
|
|
|
def getNetworkSideControllers(self):
|
|
return [self._cntrl]
|
|
|
|
|
|
class CHI_RNI_DMA(CHI_RNI_Base):
|
|
"""
|
|
DMA controller wiredup to a given dma port
|
|
"""
|
|
|
|
def __init__(self, ruby_system, dma_port, parent):
|
|
super().__init__(ruby_system, parent)
|
|
assert dma_port != None
|
|
self._sequencer.in_ports = dma_port
|
|
|
|
|
|
class CHI_RNI_IO(CHI_RNI_Base):
|
|
"""
|
|
DMA controller wiredup to ruby_system IO port
|
|
"""
|
|
|
|
def __init__(self, ruby_system, parent):
|
|
super().__init__(ruby_system, parent)
|
|
ruby_system._io_port = self._sequencer
|