Lukas Steiner
f223e6c500
Merge branch 'feat/hbm3_sid' into 'develop'
...
Feat/hbm3 sid
See merge request ems/astdm/modeling.dram/dram.sys.5!96
2025-01-28 09:04:16 +00:00
007c55e878
Use think delay as miminum END_REQ delay
...
When the controller accepts requests in the same clock cycle as it
handles them, undeterministic simulations can occur as the outcome
depends on if the new request is accepted before the controllerMethod
is called or not.
Therefore, a minimum delay of one clock cylce should be used to always
handle request only in the next clock cycle, removing the disambiguity.
2025-01-24 14:18:39 +01:00
a68a0c9ded
Restore brc HBM3 mapping
2025-01-16 15:39:04 +01:00
7a8633d36e
Implement stack ID for HBM3
2025-01-13 15:36:05 +01:00
Lukas Steiner
123574ab6d
Update README.md
2024-12-17 14:48:14 +00:00
703ee81d7e
Introduce SimulationTime config
...
Use SimulationTime to forcefully stop simulation at a specified point in
time.
2024-12-10 10:04:59 +01:00
007b273760
Add a DDR4 json example that defines everything in one single JSON
2024-11-18 14:05:52 +01:00
0ec6ea79ad
Migrate from clkMhz to tCK entry in memspecs
2024-02-23 12:04:22 +01:00
Lukas Steiner
027b6495e3
Update README.md
2024-01-31 09:33:00 +00:00
ea4e6fa33e
Update Git LFS to not track .stl files in config
2023-10-27 11:50:14 +02:00
c27ebb6c64
Fix gem5 integration issues
2023-08-31 09:34:35 +02:00
b30df49d67
Use tCCDMW for masked write in LPDDR4
2023-08-21 09:26:05 +02:00
Lukas Steiner
e389474139
Remove deprecated gem5 files.
2023-05-23 14:53:06 +02:00
156c558e32
Resize sample HBM3 memspec and address mapping to 8 Gib
2023-04-21 11:14:41 +02:00
85f944fe58
Rename RAACDR to RAADEC
2023-04-21 11:10:09 +02:00
ad4277c0ee
Enable DatabaseRecording by default again
2023-04-14 11:11:40 +02:00
b343ea821f
Refactor Configuration and add warnings when invalid values are provided
2023-04-13 11:21:37 +02:00
1f161b412f
Update documentation
2023-04-13 11:21:36 +02:00
a49afa40eb
Use key "addressmapping" instead of "CONGEN" in addressmapping configs
2023-04-13 11:21:36 +02:00
949cf944bc
Update tCCD_M timings in memspecs for DDR5
2023-04-11 14:27:26 +02:00
49954df6ee
Add tCCD_M DDR5 timings, MemSpecs still incomplete
2023-04-06 10:38:48 +02:00
Lukas Steiner
b086fa985d
Change names of LPDDR5 timings from tRCDRD/tRCDWR to tRCD_L/tRCD_S.
2023-03-30 15:06:17 +02:00
5d7171e537
Add LPDDR5X configurations and separate tRCD into tRCDRD and tRCDWR
2023-03-29 16:49:15 +02:00
Lukas Steiner
c4ca3d71d7
Reorganize config files, remove unused config.
2023-02-23 17:02:21 +01:00
