Add tCCD_M DDR5 timings, MemSpecs still incomplete

2023-04-06 10:38:48 +02:00
parent daecc19252
commit 49954df6ee
5 changed files with 73 additions and 11 deletions
--- a/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json
+++ b/configs/memspec/JEDEC_2x8x2Gbx4_DDR5-3200A.json
@@ -39,6 +39,8 @@
            "CCD_L_slr": 8,
            "CCD_L_WR_slr": 32,
            "CCD_L_WR2_slr": 16,
+            "CCD_M_slr": 8,
+            "CCD_M_WR_slr": 32,
            "CCD_S_slr": 8,
            "CCD_S_WR_slr": 8,
            "CCD_dlr": 0,
@@ -50,6 +52,7 @@
            "FAW_slr": 32,
            "FAW_dlr": 0,
            "WTR_L": 16,
+            "WTR_M": 16,
            "WTR_S": 4,
            "RFC1_slr": 312,
            "RFC2_slr": 208,