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Reorganize config files, remove unused config.

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This commit is contained in:
Lukas Steiner
2023-02-23 17:02:21 +01:00
parent 39b456d837
commit c4ca3d71d7
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266
configs/README.md Normal file
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# Configuration
The DRAMSys executable supports one argument, which is a JSON file that contains certain arguments and the name of nested configuration files for the desired simulation. Alternatively, the contents of nested configuration files can also be added directly to the top configuration file instead of the file name.
The JSON code below shows an example configuration:
```json
{
"simulation": {
"simulationid": "ddr3-example",
"simconfig": "example.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_brc.json",
"mcconfig":"fifoStrict.json",
"tracesetup": [
{
"clkMhz": 300,
"name": "example.stl"
},
{
"clkMhz": 2000,
"type": "generator",
"name": "gen0",
"numRequests": 2000,
"rwRatio": 0.85,
"addressDistribution": "random",
"seed": 123456,
"maxPendingReadRequests": 8,
"maxPendingWriteRequests": 8,
"minAddress": 16384,
"maxAddress": 32767
},
{
"clkMhz": 1000,
"type": "hammer",
"name": "ham0",
"numRequests": 4000,
"rowIncrement": 2097152
}
]
}
}
```
Field Descriptions:
- "simulationid": simulation file identifier
- "simconfig": configuration file for the DRAMSys simulator
- "memspec": memory device configuration file
- "addressmapping": address mapping configuration file
- "mcconfig": memory controller configuration file
- "tracesetup": The trace setup is only used in standalone mode. In library mode or gem5 mode the trace setup is ignored. Each device should be added as a json object inside the "tracesetup" array.
Each **trace setup** device configuration can be a **trace player** ("type": "player"), a **traffic generator** ("type": "generator") or a **row hammer generator** ("type": "hammer"). By not specifing the **type** parameter, the device will act as a **trace player**.
All device configurations must define a **clkMhz** (operation frequency of the **traffic initiator**) and a **name** (in case of a trace player this specifies the **trace file** to play; in case of a generator this field is only for identification purposes).
The **maxPendingReadRequests** and **maxPendingWriteRequests** parameters define the maximum number of outstanding read/write requests. The current implementation delays all memory accesses if one limit is reached. The default value (0) disables the limit.
A **traffic generator** can be configured to generate **numRequests** requests in total, of which the **rwRatio** field defines the probability of one request being a read request. The length of a request (in bytes) can be specified with the **dataLength** parameter. The **seed** parameter can be used to produce identical results for all simulations. **minAddress** and **maxAddress** specify the address range, by default the whole address range is used. The parameter **addressDistribution** can either be set to **random** or **sequential**. In case of **sequential** the additional **addressIncrement** field must be specified, defining the address increment after each request.
The **row hammer generator** is a special traffic generator that mimics a row hammer attack. It generates **numRequests** alternating read requests to two different addresses. The first address is 0x0, the second address is specified by the **rowIncrement** parameter and should decode to a different row in the same bank. Since only one outstanding request is allowed, the controller cannot perform any reordering, forcing a row switch (precharge and activate) for each access. That way the number of activations on the target rows are maximized.
Most configuration fields reference other JSON files which contain more specialized chunks of the configuration like a memory specification, an address mapping and a memory controller configuration.
## Trace Files
A **trace file** is a prerecorded file containing memory transactions. Each memory transaction has a time stamp that tells the simulator when it shall happen, a transaction type (*read* or *write*) and a hexadecimal memory address. The optional length parameter (in bytes) allows sending transactions with a custom length that does not match the length of a single DRAM burst access. In this case a length converter has to be added. Write transactions also have to specify a data field when storage is enabled in DRAMSys.
There are two different kinds of trace files. They differ in their timing behavior and are distinguished by their file extension.
### STL Traces (.stl)
The time stamp corresponds to the time the request is to be issued and it is given in cycles of the bus master device. Example: The device is an FPGA with a frequency of 200 MHz (clock period of 5 ns). If the time stamp is 10 the request is to be issued when time is 50 ns.
Syntax example:
```
# Comment lines begin with #
# cycle: [(length)] command hex-address [hex-data]
31: read 0x400140
33: read 0x400160
56: write 0x7fff8000 0x123456789abcdef...
81: (128) read 0x400180
```
### Relative STL Traces (.rstl)
The time stamp corresponds to the time the request is to be issued relative to the end of the previous transaction. This results in a simulation in which the trace player is able to react to possible delays due to DRAM bottlenecks.
Syntax example:
```
# Comment lines begin with #
# cycle: [(length)] command hex-address [hex-data]
31: read 0x400140
2: (512) read 0x400160
23: write 0x7fff8000 0x123456789abcdef...
10: read 0x400180
```
### Elastic Traces
More information about elastic traces can be found in the [gem5 readme](../src/gem5/README.md).
## Trace Player
A trace player is equivalent to a bus master device (processor, FPGA, etc.). It reads an input trace file and translates each line into a new memory request. By adding a new device element into the trace setup section one can specify a new trace player, its operating frequency and its trace file.
## Configuration File Sections
The main configuration file is divided into self-contained sections. Each of these sections refers to sub-configuration files. Below, the sub-configurations are listed and explained.
### Simulator Configuration
The content of [ddr3.json](simconfig/example.json) is presented below as an example.
```json
{
"simconfig": {
"SimulationName": "example",
"Debug": false,
"DatabaseRecording": true,
"PowerAnalysis": false,
"EnableWindowing": false,
"WindowSize": 1000,
"SimulationProgressBar": true,
"CheckTLM2Protocol": false,
"UseMalloc": false,
"AddressOffset": 0,
"StoreMode": "NoStorage"
}
}
```
- *SimulationName* (string)
- Give the name of the simulation for distinguishing from other simulations.
- *Debug* (boolean)
- true: enables debug output on console (only supported by a debug build)
- false: disables debug output
- *DatabaseRecording* (boolean)
- true: enables output database recording for the Trace Analyzer tool
- false: disables output database recording
- *PowerAnalysis* (boolean)
- true: enables live power analysis with DRAMPower
- false: disables power analysis
- *EnableWindowing* (boolean)
- true: enables temporal windowing
- false: disables temporal windowing
- *WindowSize* (unsigned int)
- Size of the window in clock cycles used to evaluate average bandwidth and average power consumption
- *SimulationProgressBar* (boolean)
- true: enables the simulation progress bar
- false: disables the simulation progress bar
- *CheckTLM2Protocol* (boolean)
- true: enables the TLM-2.0 Protocol Checking
- false: disables the TLM-2.0 Protocol Checking
- *UseMalloc* (boolean)
- false: model storage using mmap() (DEFAULT)
- true: allocate memory for modeling storage using malloc()
- *AddressOffset* (unsigned int)
- Address offset of the DRAM subsystem (required for the gem5 coupling).
- *StoreMode* (string)
- "NoStorage": no storage
- "Store": store data without error model
### Memory Specification
A file with memory specifications. Timings and currents come from data sheets and measurements and usually do not change.
The fields inside "mempowerspec" can be written directly as a **double** type, "memoryId" and "memoryType" are **string**, all other fields are **unsigned int**.
### Address Mapping
DRAMSys uses the **ConGen** [7] format for address mappings. It provides bit-wise granularity. It also provides the possibility to XOR address bits in order to map page misses to different banks and reduce latencies.
Used fields:
- "XOR": Defines an XOR connection of a "FIRST" and a "SECOND" bit
- "BYTE_BIT": Address bits that are connected to the byte bits in ascending order
- "COLUMN_BIT": Address bits that are connected to the column bits in ascending order
- "ROW_BIT": Address bits that are connected to the row bits in ascending order
- "BANK_BIT": Address bits that are connected to the bank bits in ascending order
- "BANKGROUP_BIT": Address bits that are connected to the bank group bits in ascending order
- "RANK_BIT": Address bits that are connected to the rank bits in ascending order
- "CHANNEL_BIT": Address bits that are connected to the channel bits in ascending order
```json
{
"CONGEN": {
"XOR": [
{
"FIRST": 13,
"SECOND": 16
}
],
"BYTE_BIT": [0,1,2],
"COLUMN_BIT": [3,4,5,6,7,8,9,10,11,12],
"BANK_BIT": [13,14,15],
"ROW_BIT": [16,17,18,19,20,21,22,23,24,25,26,27,28,29]
}
}
```
### Memory Controller
An example follows.
```json
{
"mcconfig": {
"PagePolicy": "Open",
"Scheduler": "Fifo",
"SchedulerBuffer": "ReadWrite",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "AllBank",
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",
"Arbiter": "Fifo",
"MaxActiveTransactions": 128,
"RefreshManagement": true
}
}
```
- *PagePolicy* (string)
- "Open": no auto-precharge is performed after read or write commands
- "OpenAdaptive": auto-precharge after read or write commands is only performed if further requests for the targeted bank are stored in the scheduler and all the requests are row misses
- "Closed": auto-precharge is performed after each read or write command
- "ClosedAdaptive": auto-precharge after read or write commands is performed if all further requests for the targeted bank stored in the scheduler are row misses or if there are no further requests stored
- *Scheduler* (string)
- all policies are applied locally to one bank, not globally to the whole channel
- "Fifo": first in, first out policy
- "FrFcfs": first-ready - first-come, first-served policy (row hits are preferred to row misses)
- "FrFcfsGrp": first-ready - first-come, first-served policy with additional grouping of read and write requests
- *SchedulerBuffer* (string)
- "Bankwise": requests are stored in bankwise buffers
- "ReadWrite": read and write requests are stored in different buffers
- "Shared": all requests are stored in one shared buffer
- *RequestBufferSize* (unsigned int)
- depth of a single scheduler buffer entity, total buffer depth depends on the selected scheduler buffer policy
- *CmdMux* (string)
- "Oldest": from all commands that are ready to be issued in the current clock cycle the one that belongs to the oldest transaction has the highest priority; commands from refresh managers have a higher priority than all other commands, commands from power down managers have a lower priority than all other commands
- "Strict": based on "Oldest", in addition, read and write commands are strictly issued in the order their corresponding requests arrived at the channel controller (can only be used in combination with the "Fifo" scheduler)
- *RespQueue* (string)
- "Fifo": the original request order is not restored for outgoing responses
- "Reorder": the original request order is restored for outgoing responses (only within the channel)
- *RefreshPolicy* (string)
- "NoRefresh": refresh is disabled
- "AllBank": all-bank refresh commands are issued (per rank)
- "PerBank": per-bank refresh commands are issued (only available in combination with LPDDR4, Wide I/O 2, GDDR5/5X/6 or HBM2)
- "SameBank": same-bank refresh commands are issued (only available in combination with DDR5)
- *RefreshMaxPostponed* (unsigned int)
- maximum number of refresh commands that can be postponed (with per-bank refresh the number is internally multiplied with the number of banks, with same-bank refresh the number is internally multiplied with the number of banks per bank group)
- *RefreshMaxPulledin* (unsigned int)
- maximum number of refresh commands that can be pulled in (with per-bank refresh the number is internally multiplied with the number of banks, with same-bank refresh the number is internally multiplied with the number of banks per bank group)
- *PowerDownPolicy* (string)
- "NoPowerDown": power down disabled
- "Staggered": staggered power down policy [5]
- *Arbiter* (string)
- "Simple": simple forwarding of transactions to the right channel or initiator
- "Fifo": transactions can be buffered internally to achieve a higher throughput especially in multi-initiator-multi-channel configurations
- "Reorder": based on "Fifo", in addition, the original request order is restored for outgoing responses (separately for each initiator and globally to all channels)
- *MaxActiveTransactions* (unsigned int)
- maximum number of active transactions per initiator (only applies to "Fifo" and "Reorder" arbiter policy)
- *RefreshManagement* (boolean)
- enable the sending of refresh management commands when the number of activates to one bank exceeds a certain management threshold (only supported in DDR5 and LPDDR5)

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configs/addressmapping/am_ddr3_4x4Gbx16_dimm_p2KB_brc.json Normal file
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{
"CONGEN": {
"BANK_BIT": [
28,
29,
30
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27
]
}
}

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configs/addressmapping/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.json Normal file
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{
"CONGEN": {
"BANK_BIT": [
13,
14,
15
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

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configs/addressmapping/am_ddr3_8x1Gbx8_dimm_p1KB_brc.json Normal file
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{
"CONGEN": {
"BANK_BIT": [
27,
28,
29
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

42
configs/addressmapping/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json Normal file
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@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
13,
14,
15
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

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configs/addressmapping/am_ddr3_8x2Gbx8_dimm_p1KB_brc.json Normal file
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{
"CONGEN": {
"BANK_BIT": [
28,
29,
30
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27
]
}
}

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configs/addressmapping/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.json Normal file
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{
"CONGEN": {
"BANK_BIT": [
13,
14,
15
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

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configs/addressmapping/am_ddr3_x16_brc.json Normal file
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@@ -0,0 +1,41 @@
{
"CONGEN": {
"BANK_BIT": [
26,
27,
28
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25
]
}
}

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configs/addressmapping/am_ddr3_x16_rbc.json Normal file
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@@ -0,0 +1,41 @@
{
"CONGEN": {
"BANK_BIT": [
13,
14,
15
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28
]
}
}

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configs/addressmapping/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json Normal file
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{
"CONGEN": {
"BANKGROUP_BIT":[
28,
29
],
"BANK_BIT": [
30,
31
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27
]
}
}

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configs/addressmapping/am_ddr5_2x2x8x4Gbx4_dimm_p1KB_rbc.json Normal file
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@@ -0,0 +1,54 @@
{
"CONGEN": {
"BYTE_BIT": [
0,
1
],
"COLUMN_BIT": [
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"BANKGROUP_BIT": [
13,
14,
15
],
"BANK_BIT": [
16,
17
],
"ROW_BIT": [
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
32,
33
],
"CHANNEL_BIT": [
34
],
"RANK_BIT": [
35
]
}
}

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configs/addressmapping/am_ddr5_2x4x1Gbx8_dimm_p1KB_rbc.json Normal file
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@@ -0,0 +1,49 @@
{
"CONGEN": {
"BYTE_BIT": [
0,
1
],
"COLUMN_BIT": [
2,
3,
4,
5,
6,
7,
8,
9,
10,
11
],
"BANKGROUP_BIT": [
12,
13,
14
],
"BANK_BIT": [
15
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31
],
"CHANNEL_BIT": [
32
]
}
}

50
configs/addressmapping/am_ddr5_2x8x2Gbx4_dimm_p1KB_rbc.json Normal file
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@@ -0,0 +1,50 @@
{
"CONGEN": {
"BYTE_BIT": [
0,
1
],
"COLUMN_BIT": [
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"BANKGROUP_BIT": [
13,
14,
15
],
"BANK_BIT": [
16
],
"ROW_BIT": [
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
32
],
"CHANNEL_BIT": [
33
]
}
}

55
configs/addressmapping/am_ddr5_2x8x8x2Gbx4_dimm_p1KB_rbc.json Normal file
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@@ -0,0 +1,55 @@
{
"CONGEN": {
"BYTE_BIT": [
0,
1
],
"COLUMN_BIT": [
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"BANKGROUP_BIT": [
13,
14,
15
],
"BANK_BIT": [
16
],
"ROW_BIT": [
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
32
],
"RANK_BIT": [
33,
34,
35
],
"CHANNEL_BIT": [
36
]
}
}

46
configs/addressmapping/am_hbm2_8Gb_pc_brc.json Normal file
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@@ -0,0 +1,46 @@
{
"CONGEN": {
"PSEUDOCHANNEL_BIT":[
29
],
"BANKGROUP_BIT":[
27,
28
],
"BANK_BIT": [
25,
26
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9
],
"ROW_BIT": [
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24
]
}
}

45
configs/addressmapping/am_hbm3_8Gb_pc_brc.json Normal file
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@@ -0,0 +1,45 @@
{
"CONGEN": {
"PSEUDOCHANNEL_BIT":[
28
],
"BANKGROUP_BIT":[
26,
27
],
"BANK_BIT": [
24,
25
],
"BYTE_BIT": [
0,
1
],
"COLUMN_BIT": [
2,
3,
4,
5,
6,
7,
8
],
"ROW_BIT": [
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23
]
}
}

43
configs/addressmapping/am_lpddr4_1Gbx16_baroco.json Normal file
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@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
28,
29,
30
],
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27
]
}
}

43
configs/addressmapping/am_lpddr4_1Gbx16_robaco.json Normal file
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@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12,
13
],
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

43
configs/addressmapping/am_lpddr4_1Gbx16_rocoba.json Normal file
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@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
5,
6,
7
],
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
8,
9,
10,
11,
12,
13
],
"ROW_BIT": [
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

42
configs/addressmapping/am_lpddr4_512Mbx16_baroco.json Normal file
View File

@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
27,
28,
29
],
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

42
configs/addressmapping/am_lpddr4_512Mbx16_robaco.json Normal file
View File

@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12,
13
],
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

42
configs/addressmapping/am_lpddr4_512Mbx16_rocoba.json Normal file
View File

@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
5,
6,
7
],
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
8,
9,
10,
11,
12,
13
],
"ROW_BIT": [
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

42
configs/addressmapping/am_lpddr4_8Gbx16_brc.json Normal file
View File

@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
27,
28,
29
],
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

43
configs/addressmapping/am_lpddr5_1Gbx16_16B_robaco.json Normal file
View File

@@ -0,0 +1,43 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10
],
"BANK_BIT": [
11,
12,
13,
14
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

43
configs/addressmapping/am_lpddr5_1Gbx16_16B_rocoba.json Normal file
View File

@@ -0,0 +1,43 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
9,
10,
11,
12,
13,
14
],
"BANK_BIT": [
5,
6,
7,
8
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

43
configs/addressmapping/am_lpddr5_1Gbx16_8B_robaco.json Normal file
View File

@@ -0,0 +1,43 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11
],
"BANK_BIT": [
12,
13,
14
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

43
configs/addressmapping/am_lpddr5_1Gbx16_8B_rocoba.json Normal file
View File

@@ -0,0 +1,43 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
9,
10,
11,
12,
13,
14
],
"BANK_BIT": [
6,
7,
8
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

45
configs/addressmapping/am_lpddr5_1Gbx16_BG_robacobg.json Normal file
View File

@@ -0,0 +1,45 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
7,
8,
9,
10,
11,
12
],
"BANKGROUP_BIT": [
5,
6
],
"BANK_BIT": [
13,
14
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

45
configs/addressmapping/am_lpddr5_1Gbx16_BG_rocobabg.json Normal file
View File

@@ -0,0 +1,45 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
9,
10,
11,
12,
13,
14
],
"BANKGROUP_BIT": [
5,
6
],
"BANK_BIT": [
7,
8
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

42
configs/addressmapping/am_lpddr5_512Mbx16_16B_robaco.json Normal file
View File

@@ -0,0 +1,42 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10
],
"BANK_BIT": [
11,
12,
13,
14
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

42
configs/addressmapping/am_lpddr5_512Mbx16_16B_rocoba.json Normal file
View File

@@ -0,0 +1,42 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
9,
10,
11,
12,
13,
14
],
"BANK_BIT": [
5,
6,
7,
8
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

42
configs/addressmapping/am_lpddr5_512Mbx16_8B_robaco.json Normal file
View File

@@ -0,0 +1,42 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11
],
"BANK_BIT": [
12,
13,
14
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

42
configs/addressmapping/am_lpddr5_512Mbx16_8B_rocoba.json Normal file
View File

@@ -0,0 +1,42 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
9,
10,
11,
12,
13,
14
],
"BANK_BIT": [
6,
7,
8
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

44
configs/addressmapping/am_lpddr5_512Mbx16_BG_robacobg.json Normal file
View File

@@ -0,0 +1,44 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
7,
8,
9,
10,
11,
12
],
"BANKGROUP_BIT": [
5,
6
],
"BANK_BIT": [
13,
14
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

44
configs/addressmapping/am_lpddr5_512Mbx16_BG_rocobabg.json Normal file
View File

@@ -0,0 +1,44 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
9,
10,
11,
12,
13,
14
],
"BANKGROUP_BIT": [
5,
6
],
"BANK_BIT": [
7,
8
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

46
configs/addressmapping/am_ranktest.json Normal file
View File

@@ -0,0 +1,46 @@
{
"CONGEN": {
"RANK_BIT":[
30,
31
],
"BANK_BIT": [
27,
28,
29
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

43
configs/addressmapping/am_stt-mram_8x2Gbx8_dimm_p1KB_rbc.json Normal file
View File

@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
13,
14,
15
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

44
configs/addressmapping/am_wideio2_4x64_4x2Gb_brc.json Normal file
View File

@@ -0,0 +1,44 @@
{
"CONGEN": {
"BANK_BIT": [
25,
26,
27
],
"BYTE_BIT": [
0,
1,
2
],
"CHANNEL_BIT": [
28,
29
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11
],
"ROW_BIT": [
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24
]
}
}

44
configs/addressmapping/am_wideio2_4x64_4x2Gb_rbc.json Normal file
View File

@@ -0,0 +1,44 @@
{
"CONGEN": {
"BANK_BIT": [
12,
13,
14
],
"BYTE_BIT": [
0,
1,
2
],
"CHANNEL_BIT": [
28,
29
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27
]
}
}

43
configs/addressmapping/am_wideio_4x1Gb_brc.json Normal file
View File

@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
25,
26
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
27,
28
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24
]
}
}

43
configs/addressmapping/am_wideio_4x1Gb_rbc.json Normal file
View File

@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
27,
28
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

41
configs/addressmapping/am_wideio_4x256Mb_brc.json Normal file
View File

@@ -0,0 +1,41 @@
{
"CONGEN": {
"BANK_BIT": [
23,
24
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
25,
26
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22
]
}
}

41
configs/addressmapping/am_wideio_4x256Mb_rbc.json Normal file
View File

@@ -0,0 +1,41 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
25,
26
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24
]
}
}

44
configs/addressmapping/am_wideio_4x2Gb_brc.json Normal file
View File

@@ -0,0 +1,44 @@
{
"CONGEN": {
"BANK_BIT": [
26,
27
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
28,
29
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25
]
}
}

44
configs/addressmapping/am_wideio_4x2Gb_rbc.json Normal file
View File

@@ -0,0 +1,44 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
28,
29
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27
]
}
}

45
configs/addressmapping/am_wideio_4x4Gb_brc.json Normal file
View File

@@ -0,0 +1,45 @@
{
"CONGEN": {
"BANK_BIT": [
27,
28
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
29,
30
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10,
11
],
"ROW_BIT": [
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

45
configs/addressmapping/am_wideio_4x4Gb_rbc.json Normal file
View File

@@ -0,0 +1,45 @@
{
"CONGEN": {
"BANK_BIT": [
12,
13
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
29,
30
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10,
11
],
"ROW_BIT": [
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28
]
}
}

42
configs/addressmapping/am_wideio_4x512Mb_brc.json Normal file
View File

@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
24,
25
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
26,
27
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23
]
}
}

42
configs/addressmapping/am_wideio_4x512Mb_rbc.json Normal file
View File

@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
26,
27
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25
]
}
}

41
configs/addressmapping/am_wideio_thermal.json Normal file
View File

@@ -0,0 +1,41 @@
{
"CONGEN": {
"BANK_BIT": [
4,
5
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
25,
26
],
"COLUMN_BIT": [
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24
]
}
}

15
configs/ddr3-example.json Normal file
View File

@@ -0,0 +1,15 @@
{
"simulation": {
"addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"simconfig": "example.json",
"simulationid": "ddr3-example",
"tracesetup": [
{
"clkMhz": 800,
"name": "example.stl"
}
]
}
}

9
configs/ddr3-gem5-se.json Normal file
View File

@@ -0,0 +1,9 @@
{
"simulation": {
"addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_brc.json",
"mcconfig": "fifoStrict.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"simconfig": "gem5_se.json",
"simulationid": "ddr3-gem5-se"
}
}

15
configs/ddr4-example.json Normal file
View File

@@ -0,0 +1,15 @@
{
"simulation": {
"addressmapping": "am_ddr4_8x4Gbx8_dimm_p1KB_brc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_4Gb_DDR4-1866_8bit_A.json",
"simconfig": "example.json",
"simulationid": "ddr4-example",
"tracesetup": [
{
"clkMhz": 200,
"name": "example.stl"
}
]
}
}

15
configs/ddr5-example.json Normal file
View File

@@ -0,0 +1,15 @@
{
"simulation": {
"addressmapping": "am_ddr5_2x8x2Gbx4_dimm_p1KB_rbc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_2x8x2Gbx4_DDR5-3200A.json",
"simconfig": "example.json",
"simulationid": "ddr5-example",
"tracesetup": [
{
"clkMhz": 2000,
"name": "example.stl"
}
]
}
}

33
configs/ddr5-generator-example.json Normal file
View File

@@ -0,0 +1,33 @@
{
"simulation": {
"addressmapping": "am_ddr5_2x8x2Gbx4_dimm_p1KB_rbc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_2x8x2Gbx4_DDR5-3200A.json",
"simconfig": "example.json",
"simulationid": "ddr5-example",
"tracesetup": [
{
"clkMhz": 2000,
"type": "generator",
"name": "gen0",
"numRequests": 2000,
"rwRatio": 0.85,
"addressDistribution": "sequential",
"addressIncrement": 256,
"maxPendingReadRequests": 8,
"maxPendingWriteRequests": 8
},
{
"clkMhz": 2000,
"type": "generator",
"name": "gen1",
"numRequests": 2000,
"rwRatio": 0.85,
"addressDistribution": "random",
"seed": 123456,
"maxPendingReadRequests": 8,
"maxPendingWriteRequests": 8
}
]
}
}

29
configs/ddr5-rfm.json Normal file
View File

@@ -0,0 +1,29 @@
{
"simulation": {
"addressmapping": "am_ddr5_2x2x8x4Gbx4_dimm_p1KB_rbc.json",
"mcconfig": "fr_fcfs_rfm.json",
"memspec": "JEDEC_2x2x8x4Gbx4_DDR5-3200A.json",
"simconfig": "example.json",
"simulationid": "ddr5-example",
"tracesetup": [
{
"clkMhz": 2000,
"type": "generator",
"name": "gen0",
"numRequests": 126000,
"rwRatio": 0.85,
"addressDistribution": "random",
"seed": 123456,
"maxPendingReadRequests": 24,
"maxPendingWriteRequests": 24
},
{
"clkMhz": 4000,
"type": "hammer",
"name": "ham0",
"numRequests": 4000,
"rowIncrement": 2097152
}
]
}
}

448
configs/gem5/gem5_etrace/config.ini Normal file
View File

@@ -0,0 +1,448 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler membus physmem tlm voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
kernel_extras=
load_addr_mask=18446744073709551615
load_offset=0
mem_mode=timing
mem_ranges=0:536870911:0:0:0:0
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=TraceCPU
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
checker=Null
clk_domain=system.clk_domain
cpu_id=0
dataTraceFile=../../DRAMSys/gem5/gem5_etrace/system.cpu.traceListener.data.gz
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
enableEarlyExit=false
eventq_index=0
freqMultiplier=1.0
function_trace=false
function_trace_start=0
instTraceFile=../../DRAMSys/gem5/gem5_etrace/system.cpu.traceListener.inst.gz
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_gating_on_idle=false
power_model=
profile=0
progressMsgInterval=0
progress_interval=0
pwr_gating_latency=300
simpoint_start_insts=
sizeLoadBuffer=16
sizeROB=40
sizeStoreBuffer=16
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=replacement_policy tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
prefetch_on_access=false
prefetcher=Null
replacement_policy=system.cpu.dcache.replacement_policy
response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
warmup_percentage=0
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.membus.slave[2]
[system.cpu.dcache.replacement_policy]
type=LRURP
eventq_index=0
[system.cpu.dcache.tags]
type=BaseSetAssoc
assoc=2
block_size=64
clk_domain=system.clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
replacement_policy=system.cpu.dcache.replacement_policy
sequential_access=false
size=32768
tag_latency=2
warmup_percentage=0
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
sys=system
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
sys=system
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
[system.cpu.icache]
type=Cache
children=replacement_policy tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
prefetch_on_access=false
prefetcher=Null
replacement_policy=system.cpu.icache.replacement_policy
response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
warmup_percentage=0
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.membus.slave[1]
[system.cpu.icache.replacement_policy]
type=LRURP
eventq_index=0
[system.cpu.icache.tags]
type=BaseSetAssoc
assoc=2
block_size=64
clk_domain=system.clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
replacement_policy=system.cpu.icache.replacement_policy
sequential_access=false
size=32768
tag_latency=2
warmup_percentage=0
[system.cpu.interrupts]
type=ArmInterrupts
eventq_index=0
[system.cpu.isa]
type=ArmISA
decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
impdef_nop=false
midr=1091551472
pmu=Null
system=system
vecRegRenameMode=Full
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
sys=system
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
sys=system
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu_clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.cpu_voltage_domain
[system.cpu_voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
point_of_unification=true
power_model=
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.tlm.port
slave=system.system_port system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
range=0:134217727:0:0:0:0
[system.tlm]
type=ExternalSlave
addr_ranges=0:536870911:0:0:0:0
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
port_data=transactor
port_type=tlm_slave
power_model=
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0

BIN
configs/gem5/gem5_etrace/system.cpu.traceListener.data.gz LFS Normal file
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BIN
configs/gem5/gem5_etrace/system.cpu.traceListener.inst.gz LFS Normal file
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553
configs/gem5/gem5_se/hello-ARM/config.ini Normal file
View File

@@ -0,0 +1,553 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler external_memory l2 membus physmem tol2bus voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=false
kernel_extras=
load_addr_mask=18446744073709551615
load_offset=0
mem_mode=timing
mem_ranges=0:536870911:0:0:0:0
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_gating_on_idle=false
power_model=
profile=0
progress_interval=0
pwr_gating_latency=300
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=replacement_policy tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
prefetch_on_access=false
prefetcher=Null
replacement_policy=system.cpu.dcache.replacement_policy
response_latency=2
sequential_access=false
size=65536
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
warmup_percentage=0
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.tol2bus.slave[1]
[system.cpu.dcache.replacement_policy]
type=LRURP
eventq_index=0
[system.cpu.dcache.tags]
type=BaseSetAssoc
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
replacement_policy=system.cpu.dcache.replacement_policy
sequential_access=false
size=65536
tag_latency=2
warmup_percentage=0
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
sys=system
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
sys=system
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
port=system.tol2bus.slave[3]
[system.cpu.icache]
type=Cache
children=replacement_policy tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
prefetch_on_access=false
prefetcher=Null
replacement_policy=system.cpu.icache.replacement_policy
response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
warmup_percentage=0
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.tol2bus.slave[0]
[system.cpu.icache.replacement_policy]
type=LRURP
eventq_index=0
[system.cpu.icache.tags]
type=BaseSetAssoc
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
replacement_policy=system.cpu.icache.replacement_policy
sequential_access=false
size=32768
tag_latency=2
warmup_percentage=0
[system.cpu.interrupts]
type=ArmInterrupts
eventq_index=0
[system.cpu.isa]
type=ArmISA
decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
impdef_nop=false
midr=1091551472
pmu=Null
system=system
vecRegRenameMode=Full
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
sys=system
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
sys=system
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
port=system.tol2bus.slave[2]
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=Process
cmd=../../DRAMSys/gem5/gem5_se/hello-ARM/hello
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=../../DRAMSys/gem5/gem5_se/hello-ARM/hello
gid=100
input=cin
kvmInSE=false
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=0
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.cpu_voltage_domain
[system.cpu_voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.external_memory]
type=ExternalSlave
addr_ranges=0:536870911:0:0:0:0
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
port_data=transactor
port_type=tlm_slave
power_model=
port=system.membus.master[0]
[system.l2]
type=Cache
children=replacement_policy tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
prefetch_on_access=false
prefetcher=Null
replacement_policy=system.l2.replacement_policy
response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.l2.tags
tgts_per_mshr=12
warmup_percentage=0
write_buffers=8
writeback_clean=false
cpu_side=system.tol2bus.master[0]
mem_side=system.membus.slave[1]
[system.l2.replacement_policy]
type=LRURP
eventq_index=0
[system.l2.tags]
type=BaseSetAssoc
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
replacement_policy=system.l2.replacement_policy
sequential_access=false
size=2097152
tag_latency=20
warmup_percentage=0
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
point_of_unification=true
power_model=
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.external_memory.port
slave=system.system_port system.l2.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
range=0:134217727:0:0:0:0
[system.tol2bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
point_of_unification=true
power_model=
response_latency=1
snoop_filter=system.tol2bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.l2.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.tol2bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0

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282
configs/gem5/gem5_se/hello-X86/config.ini Normal file
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[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler external_memory membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=false
kernel_extras=
kvm_vm=Null
load_addr_mask=18446744073709551615
load_offset=0
mem_mode=timing
mem_ranges=0:536870911:0:0:0:0
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=apic_clk_domain dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_gating_on_idle=false
power_model=
profile=0
progress_interval=0
pwr_gating_latency=300
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.apic_clk_domain]
type=DerivedClockDomain
clk_divider=16
clk_domain=system.cpu_clk_domain
eventq_index=0
[system.cpu.dtb]
type=X86TLB
children=walker
eventq_index=0
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
num_squash_per_cycle=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
system=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
clk_domain=system.cpu.apic_clk_domain
default_p_state=UNDEFINED
eventq_index=0
int_latency=1000
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=2305843009213693952
pio_latency=100000
power_model=
system=system
int_master=system.membus.slave[5]
int_slave=system.membus.master[1]
pio=system.membus.master[0]
[system.cpu.isa]
type=X86ISA
eventq_index=0
[system.cpu.itb]
type=X86TLB
children=walker
eventq_index=0
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
num_squash_per_cycle=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
system=system
port=system.membus.slave[3]
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=Process
cmd=../../DRAMSys/gem5/gem5_se/hello-X86/hello
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=../../DRAMSys/gem5/gem5_se/hello-X86/hello
gid=100
input=cin
kvmInSE=false
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=0
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.cpu_voltage_domain
[system.cpu_voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.external_memory]
type=ExternalSlave
addr_ranges=0:536870911:0:0:0:0
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
port_data=transactor
port_type=tlm_slave
power_model=
port=system.membus.master[2]
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
point_of_unification=true
power_model=
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.external_memory.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
range=0:134217727:0:0:0:0
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0

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15
configs/hbm2-example.json Normal file
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{
"simulation": {
"addressmapping": "am_hbm2_8Gb_pc_brc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "HBM2.json",
"simconfig": "example.json",
"simulationid": "hbm2-example",
"tracesetup": [
{
"clkMhz": 1000,
"name": "example.stl"
}
]
}
}

15
configs/hbm3-example.json Normal file
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@@ -0,0 +1,15 @@
{
"simulation": {
"addressmapping": "am_hbm3_8Gb_pc_brc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "HBM3.json",
"simconfig": "example.json",
"simulationid": "hbm3-example",
"tracesetup": [
{
"clkMhz": 1000,
"name": "example.stl"
}
]
}
}

15
configs/lpddr4-example.json Normal file
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@@ -0,0 +1,15 @@
{
"simulation": {
"addressmapping": "am_lpddr4_8Gbx16_brc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_8Gb_LPDDR4-3200_16bit.json",
"simconfig": "example.json",
"simulationid": "lpddr4-example",
"tracesetup": [
{
"clkMhz": 200,
"name": "example.stl"
}
]
}
}

15
configs/lpddr5-example.json Normal file
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@@ -0,0 +1,15 @@
{
"simulation": {
"addressmapping": "am_lpddr5_1Gbx16_BG_rocobabg.json",
"mcconfig": "fr_fcfs_refp2b.json",
"memspec": "JEDEC_1Gbx16_BG_LPDDR5-6400.json",
"simconfig": "example.json",
"simulationid": "lpddr5-example",
"tracesetup": [
{
"clkMhz": 200,
"name": "example.stl"
}
]
}
}

16
configs/mcconfig/fifo.json Normal file
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@@ -0,0 +1,16 @@
{
"mcconfig": {
"PagePolicy": "Open",
"Scheduler": "Fifo",
"SchedulerBuffer": "Bankwise",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "AllBank",
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",
"Arbiter": "Simple",
"MaxActiveTransactions": 128
}
}

16
configs/mcconfig/fifoStrict.json Normal file
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@@ -0,0 +1,16 @@
{
"mcconfig": {
"PagePolicy": "Open",
"Scheduler": "Fifo",
"SchedulerBuffer": "Bankwise",
"RequestBufferSize": 8,
"CmdMux": "Strict",
"RespQueue": "Fifo",
"RefreshPolicy": "AllBank",
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",
"Arbiter": "Simple",
"MaxActiveTransactions": 128
}
}

17
configs/mcconfig/fr_fcfs.json Normal file
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@@ -0,0 +1,17 @@
{
"mcconfig": {
"PagePolicy": "Open",
"Scheduler": "FrFcfs",
"SchedulerBuffer": "Bankwise",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "AllBank",
"RefreshMaxPostponed": 0,
"RefreshMaxPulledin": 0,
"PowerDownPolicy": "NoPowerDown",
"Arbiter": "Simple",
"MaxActiveTransactions": 128,
"RefreshManagement": false
}
}

16
configs/mcconfig/fr_fcfs_grp.json Normal file
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@@ -0,0 +1,16 @@
{
"mcconfig": {
"PagePolicy": "Open",
"Scheduler": "FrFcfsGrp",
"SchedulerBuffer": "Bankwise",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "AllBank",
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",
"Arbiter": "Simple",
"MaxActiveTransactions": 128
}
}

16
configs/mcconfig/fr_fcfs_noref.json Normal file
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@@ -0,0 +1,16 @@
{
"mcconfig": {
"PagePolicy": "Open",
"Scheduler": "FrFcfs",
"SchedulerBuffer": "Bankwise",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "NoRefresh",
"RefreshMaxPostponed": 0,
"RefreshMaxPulledin": 0,
"PowerDownPolicy": "NoPowerDown",
"Arbiter": "Simple",
"MaxActiveTransactions": 128
}
}

17
configs/mcconfig/fr_fcfs_refp2b.json Normal file
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@@ -0,0 +1,17 @@
{
"mcconfig": {
"PagePolicy": "Open",
"Scheduler": "FrFcfs",
"SchedulerBuffer": "Bankwise",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Per2Bank",
"RefreshMaxPostponed": 0,
"RefreshMaxPulledin": 0,
"PowerDownPolicy": "NoPowerDown",
"Arbiter": "Simple",
"MaxActiveTransactions": 128,
"RefreshManagement": false
}
}

17
configs/mcconfig/fr_fcfs_rfm.json Normal file
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@@ -0,0 +1,17 @@
{
"mcconfig": {
"PagePolicy": "Closed",
"Scheduler": "FrFcfs",
"SchedulerBuffer": "Bankwise",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "SameBank",
"RefreshMaxPostponed": 4,
"RefreshMaxPulledin": 0,
"PowerDownPolicy": "NoPowerDown",
"Arbiter": "Simple",
"MaxActiveTransactions": 128,
"RefreshManagement": true
}
}

48
configs/memspec/HBM2.json Normal file
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@@ -0,0 +1,48 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 4,
"dataRate": 2,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 128,
"nbrOfPseudoChannels": 2,
"nbrOfRows": 32768,
"width": 64,
"nbrOfDevices": 1,
"nbrOfChannels": 1
},
"memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder",
"memoryType": "HBM2",
"memtimingspec": {
"CCDL": 3,
"CCDS": 2,
"CKE": 8,
"DQSCK": 1,
"FAW": 16,
"PL": 0,
"RAS": 28,
"RC": 42,
"RCDRD": 12,
"RCDWR": 6,
"REFI": 3900,
"REFISB": 244,
"RFC": 220,
"RFCSB": 96,
"RL": 17,
"RP": 14,
"RRDL": 6,
"RRDS": 4,
"RREFD": 8,
"RTP": 5,
"RTW": 18,
"WL": 7,
"WR": 14,
"WTRL": 9,
"WTRS": 4,
"XP": 8,
"XS": 216,
"clkMhz": 1000
}
}
}

56
configs/memspec/HBM3.json Normal file
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@@ -0,0 +1,56 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 8,
"dataRate": 4,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 128,
"nbrOfPseudoChannels": 2,
"nbrOfRows": 32768,
"width": 32,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"RAAIMT" : 16,
"RAAMMT" : 96,
"RAACDR" : 16
},
"memoryId": "",
"memoryType": "HBM3",
"memtimingspec": {
"CCDL": 4,
"CCDS": 2,
"CKE": 8,
"DQSCK": 1,
"FAW": 16,
"PL": 0,
"PPD": 2,
"RAS": 28,
"RC": 42,
"RCDRD": 12,
"RCDWR": 6,
"REFI": 3900,
"REFIPB": 122,
"RFC": 260,
"RFCPB": 96,
"RL": 17,
"RP": 14,
"RRDL": 6,
"RRDS": 4,
"RREFD": 8,
"RTP": 5,
"RTW": 18,
"WL": 12,
"WR": 23,
"WTRL": 9,
"WTRS": 4,
"XP": 8,
"XS": 260,
"clkMhz": 1600
},
"memtimingspec_comments": {
"Annahme": "8-high, 8Gb/die",
"RFCPB": "TBD?"
}
}
}

60
configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-0533.json Normal file
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@@ -0,0 +1,60 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_16B_LPDDR5-0533",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 3,
"PPD": 2,
"RPab": 3,
"RPpb": 3,
"RAS": 6,
"RCab": 9,
"RCpb": 8,
"FAW": 3,
"RRD": 2,
"RL": 6,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 0,
"RPRE": 0,
"RPST": 0,
"WL": 4,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 5,
"WTR_L": 4,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 520,
"REFIpb": 65,
"RFCab": 38,
"RFCpb": 19,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 1,
"pbR2pbR": 12,
"clkMhz": 133
}
}
}

60
configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-1067.json Normal file
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@@ -0,0 +1,60 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_16B_LPDDR5-1067",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 5,
"PPD": 2,
"RPab": 6,
"RPpb": 5,
"RAS": 12,
"RCab": 17,
"RCpb": 16,
"FAW": 6,
"RRD": 2,
"RL": 8,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 0,
"RPRE": 0,
"RPST": 0,
"WL": 4,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 10,
"WTR_L": 4,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 1041,
"REFIpb": 130,
"RFCab": 75,
"RFCpb": 38,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 2,
"pbR2pbR": 24,
"clkMhz": 267
}
}
}

60
configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-1600.json Normal file
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{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_16B_LPDDR5-1600",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 8,
"PPD": 2,
"RPab": 9,
"RPpb": 8,
"RAS": 17,
"RCab": 26,
"RCpb": 24,
"FAW": 8,
"RRD": 2,
"RL": 10,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 0,
"RPRE": 0,
"RPST": 0,
"WL": 6,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 14,
"WTR_L": 5,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 1562,
"REFIpb": 195,
"RFCab": 112,
"RFCpb": 56,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 3,
"pbR2pbR": 36,
"clkMhz": 400
}
}
}

60
configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-2133.json Normal file
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{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_16B_LPDDR5-2133",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 10,
"PPD": 2,
"RPab": 12,
"RPpb": 10,
"RAS": 23,
"RCab": 34,
"RCpb": 32,
"FAW": 11,
"RRD": 3,
"RL": 12,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 0,
"RPRE": 0,
"RPST": 0,
"WL": 8,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 19,
"WTR_L": 7,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 2083,
"REFIpb": 260,
"RFCab": 150,
"RFCpb": 75,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 4,
"pbR2pbR": 48,
"clkMhz": 533
}
}
}

60
configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-2750.json Normal file
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{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_16B_LPDDR5-2750",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 13,
"PPD": 2,
"RPab": 15,
"RPpb": 13,
"RAS": 29,
"RCab": 44,
"RCpb": 42,
"FAW": 14,
"RRD": 4,
"RL": 16,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 8,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 24,
"WTR_L": 9,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 2688,
"REFIpb": 335,
"RFCab": 193,
"RFCpb": 97,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 6,
"pbR2pbR": 62,
"clkMhz": 688
}
}
}

60
configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-3200.json Normal file
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{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_16B_LPDDR5-3200",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 15,
"PPD": 2,
"RPab": 17,
"RPpb": 15,
"RAS": 34,
"RCab": 51,
"RCpb": 48,
"FAW": 16,
"RRD": 4,
"RL": 18,
"WCK2CK": 0,
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"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 10,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 28,
"WTR_L": 10,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 3124,
"REFIpb": 390,
"RFCab": 224,
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"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
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"BL_n_S_16": 4,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 6,
"pbR2pbR": 72,
"clkMhz": 800
}
}
}

60
configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-0533.json Normal file
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{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-0533",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 3,
"PPD": 2,
"RPab": 3,
"RPpb": 3,
"RAS": 6,
"RCab": 9,
"RCpb": 8,
"FAW": 6,
"RRD": 2,
"RL": 6,
"WCK2CK": 0,
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"WL": 4,
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"WR": 5,
"WTR_L": 4,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 520,
"REFIpb": 65,
"RFCab": 38,
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"RTRS": 1,
"BL_n_min_16": 8,
"BL_n_max_16": 8,
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"BL_n_min_32": 8,
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"BL_n_S_32": 8,
"pbR2act": 2,
"pbR2pbR": 12,
"clkMhz": 133
}
}
}

60
configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-1067.json Normal file
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{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-1067",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 5,
"PPD": 2,
"RPab": 6,
"RPpb": 5,
"RAS": 12,
"RCab": 17,
"RCpb": 16,
"FAW": 11,
"RRD": 3,
"RL": 8,
"WCK2CK": 0,
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"WL": 4,
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"WR": 10,
"WTR_L": 4,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 1041,
"REFIpb": 130,
"RFCab": 75,
"RFCpb": 38,
"RTRS": 1,
"BL_n_min_16": 8,
"BL_n_max_16": 8,
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"BL_n_min_32": 8,
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"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 3,
"pbR2pbR": 24,
"clkMhz": 267
}
}
}

60
configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-1600.json Normal file
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{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-1600",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 8,
"PPD": 2,
"RPab": 9,
"RPpb": 8,
"RAS": 17,
"RCab": 26,
"RCpb": 24,
"FAW": 16,
"RRD": 4,
"RL": 10,
"WCK2CK": 0,
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"WL": 6,
"WCK2DQI": 0,
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"WR": 14,
"WTR_L": 5,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 1562,
"REFIpb": 195,
"RFCab": 112,
"RFCpb": 56,
"RTRS": 1,
"BL_n_min_16": 8,
"BL_n_max_16": 8,
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"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 4,
"pbR2pbR": 36,
"clkMhz": 400
}
}
}

60
configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-2133.json Normal file
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{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-2133",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 10,
"PPD": 2,
"RPab": 12,
"RPpb": 10,
"RAS": 23,
"RCab": 34,
"RCpb": 32,
"FAW": 22,
"RRD": 6,
"RL": 12,
"WCK2CK": 0,
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"RPST": 0,
"WL": 8,
"WCK2DQI": 0,
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"WR": 19,
"WTR_L": 7,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 2083,
"REFIpb": 260,
"RFCab": 150,
"RFCpb": 75,
"RTRS": 1,
"BL_n_min_16": 8,
"BL_n_max_16": 8,
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"BL_n_S_16": 8,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 6,
"pbR2pbR": 48,
"clkMhz": 533
}
}
}

60
configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-2750.json Normal file
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{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-2750",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 13,
"PPD": 2,
"RPab": 15,
"RPpb": 13,
"RAS": 29,
"RCab": 44,
"RCpb": 42,
"FAW": 28,
"RRD": 7,
"RL": 16,
"WCK2CK": 0,
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"RPRE": 0,
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"WL": 8,
"WCK2DQI": 0,
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"WR": 24,
"WTR_L": 9,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 2688,
"REFIpb": 335,
"RFCab": 193,
"RFCpb": 97,
"RTRS": 1,
"BL_n_min_16": 8,
"BL_n_max_16": 8,
"BL_n_L_16": 8,
"BL_n_S_16": 8,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 7,
"pbR2pbR": 62,
"clkMhz": 688
}
}
}

60
configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-3200.json Normal file
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{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-3200",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 15,
"PPD": 2,
"RPab": 17,
"RPpb": 15,
"RAS": 34,
"RCab": 51,
"RCpb": 48,
"FAW": 32,
"RRD": 8,
"RL": 18,
"WCK2CK": 0,
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"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 10,
"WCK2DQI": 0,
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"WPST": 0,
"WR": 28,
"WTR_L": 10,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 3124,
"REFIpb": 390,
"RFCab": 224,
"RFCpb": 112,
"RTRS": 1,
"BL_n_min_16": 8,
"BL_n_max_16": 8,
"BL_n_L_16": 8,
"BL_n_S_16": 8,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 8,
"pbR2pbR": 72,
"clkMhz": 800
}
}
}

60
configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-3733.json Normal file
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@@ -0,0 +1,60 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 8,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-3733",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 9,
"PPD": 2,
"RPab": 10,
"RPpb": 9,
"RAS": 20,
"RCab": 30,
"RCpb": 28,
"FAW": 19,
"RRD": 5,
"RL": 10,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 6,
"WCK2DQI": 0,
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"WR": 16,
"WTR_L": 6,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 1816,
"REFIpb": 226,
"RFCab": 131,
"RFCpb": 66,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 4,
"BL_n_max_32": 4,
"BL_n_L_32": 4,
"BL_n_S_32": 4,
"pbR2act": 5,
"pbR2pbR": 42,
"clkMhz": 467
}
}
}

60
configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-4267.json Normal file
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@@ -0,0 +1,60 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 8,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-4267",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 10,
"PPD": 2,
"RPab": 12,
"RPpb": 10,
"RAS": 23,
"RCab": 34,
"RCpb": 32,
"FAW": 22,
"RRD": 6,
"RL": 12,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 6,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 19,
"WTR_L": 7,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 2083,
"REFIpb": 260,
"RFCab": 150,
"RFCpb": 75,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 4,
"BL_n_max_32": 4,
"BL_n_L_32": 4,
"BL_n_S_32": 4,
"pbR2act": 6,
"pbR2pbR": 48,
"clkMhz": 533
}
}
}

60
configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-4800.json Normal file
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@@ -0,0 +1,60 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 8,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-4800",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 11,
"PPD": 2,
"RPab": 13,
"RPpb": 11,
"RAS": 26,
"RCab": 38,
"RCpb": 36,
"FAW": 24,
"RRD": 6,
"RL": 13,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 3,
"RPRE": 0,
"RPST": 0,
"WL": 7,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 21,
"WTR_L": 8,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 2343,
"REFIpb": 292,
"RFCab": 168,
"RFCpb": 84,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 4,
"BL_n_max_32": 4,
"BL_n_L_32": 4,
"BL_n_S_32": 4,
"pbR2act": 6,
"pbR2pbR": 54,
"clkMhz": 600
}
}
}

60
configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-5500.json Normal file
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{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 8,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-5500",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 13,
"PPD": 2,
"RPab": 15,
"RPpb": 13,
"RAS": 29,
"RCab": 44,
"RCpb": 42,
"FAW": 28,
"RRD": 7,
"RL": 15,
"WCK2CK": 0,
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"RBTP": 4,
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"RPST": 0,
"WL": 8,
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"WR": 24,
"WTR_L": 9,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 2688,
"REFIpb": 335,
"RFCab": 193,
"RFCpb": 97,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
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"BL_n_min_32": 4,
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"BL_n_L_32": 4,
"BL_n_S_32": 4,
"pbR2act": 7,
"pbR2pbR": 62,
"clkMhz": 688
}
}
}

60
configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-6000.json Normal file
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@@ -0,0 +1,60 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 8,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-6000",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 14,
"PPD": 2,
"RPab": 16,
"RPpb": 14,
"RAS": 32,
"RCab": 48,
"RCpb": 46,
"FAW": 31,
"RRD": 8,
"RL": 16,
"WCK2CK": 0,
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"RBTP": 4,
"RPRE": 0,
"RPST": 0,
"WL": 9,
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"WPRE": 0,
"WPST": 0,
"WR": 26,
"WTR_L": 10,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 2930,
"REFIpb": 366,
"RFCab": 211,
"RFCpb": 106,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 4,
"BL_n_max_32": 4,
"BL_n_L_32": 4,
"BL_n_S_32": 4,
"pbR2act": 8,
"pbR2pbR": 68,
"clkMhz": 750
}
}
}

60
configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-6400.json Normal file
View File

@@ -0,0 +1,60 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 8,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-6400",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 15,
"PPD": 2,
"RPab": 17,
"RPpb": 15,
"RAS": 34,
"RCab": 51,
"RCpb": 48,
"FAW": 32,
"RRD": 8,
"RL": 17,
"WCK2CK": 0,
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"RBTP": 4,
"RPRE": 0,
"RPST": 0,
"WL": 9,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 28,
"WTR_L": 10,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 3124,
"REFIpb": 390,
"RFCab": 224,
"RFCpb": 112,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 4,
"BL_n_max_32": 4,
"BL_n_L_32": 4,
"BL_n_S_32": 4,
"pbR2act": 8,
"pbR2pbR": 72,
"clkMhz": 800
}
}
}

60
configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-3733.json Normal file
View File

@@ -0,0 +1,60 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 8,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_BG_LPDDR5-3733",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 9,
"PPD": 2,
"RPab": 10,
"RPpb": 9,
"RAS": 20,
"RCab": 30,
"RCpb": 28,
"FAW": 10,
"RRD": 3,
"RL": 10,
"WCK2CK": 0,
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"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 6,
"WCK2DQI": 0,
"WPRE": 0,
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"WR": 16,
"WTR_L": 6,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 1816,
"REFIpb": 226,
"RFCab": 131,
"RFCpb": 66,
"RTRS": 1,
"BL_n_min_16": 2,
"BL_n_max_16": 4,
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"BL_n_S_16": 2,
"BL_n_min_32": 6,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 2,
"pbR2act": 4,
"pbR2pbR": 42,
"clkMhz": 467
}
}
}

60
configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-4267.json Normal file
View File

@@ -0,0 +1,60 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 8,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_BG_LPDDR5-4267",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 10,
"PPD": 2,
"RPab": 12,
"RPpb": 10,
"RAS": 23,
"RCab": 34,
"RCpb": 32,
"FAW": 11,
"RRD": 3,
"RL": 12,
"WCK2CK": 0,
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"WL": 6,
"WCK2DQI": 0,
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"WR": 19,
"WTR_L": 7,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 2083,
"REFIpb": 260,
"RFCab": 150,
"RFCpb": 75,
"RTRS": 1,
"BL_n_min_16": 2,
"BL_n_max_16": 4,
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"BL_n_S_16": 2,
"BL_n_min_32": 6,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 2,
"pbR2act": 4,
"pbR2pbR": 48,
"clkMhz": 533
}
}
}

60
configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-4800.json Normal file
View File

@@ -0,0 +1,60 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 8,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_BG_LPDDR5-4800",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 11,
"PPD": 2,
"RPab": 13,
"RPpb": 11,
"RAS": 26,
"RCab": 38,
"RCpb": 36,
"FAW": 12,
"RRD": 3,
"RL": 13,
"WCK2CK": 0,
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"WL": 7,
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"WR": 21,
"WTR_L": 8,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 2343,
"REFIpb": 292,
"RFCab": 168,
"RFCpb": 84,
"RTRS": 1,
"BL_n_min_16": 2,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 2,
"BL_n_min_32": 6,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 2,
"pbR2act": 5,
"pbR2pbR": 54,
"clkMhz": 600
}
}
}

60
configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-5500.json Normal file
View File

@@ -0,0 +1,60 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 8,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfDevices": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_BG_LPDDR5-5500",
"memoryType": "LPDDR5",
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"RCD": 13,
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"FAW": 14,
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"WTR_S": 5,
"CCDMW": 16,
"REFI": 2688,
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"RFCab": 193,
"RFCpb": 97,
"RTRS": 1,
"BL_n_min_16": 2,
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"BL_n_max_32": 8,
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"BL_n_S_32": 2,
"pbR2act": 6,
"pbR2pbR": 62,
"clkMhz": 688
}
}
}

60
configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-6000.json Normal file
View File

@@ -0,0 +1,60 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 8,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
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"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_BG_LPDDR5-6000",
"memoryType": "LPDDR5",
"memtimingspec": {
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"PPD": 2,
"RPab": 16,
"RPpb": 14,
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"FAW": 16,
"RRD": 4,
"RL": 16,
"WCK2CK": 0,
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"CCDMW": 16,
"REFI": 2930,
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"RFCab": 211,
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"RTRS": 1,
"BL_n_min_16": 2,
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"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 2,
"pbR2act": 6,
"pbR2pbR": 68,
"clkMhz": 750
}
}
}

60
configs/memspec/JEDEC_1Gbx16_BG_LPDDR5-6400.json Normal file
View File

@@ -0,0 +1,60 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 8,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
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"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_BG_LPDDR5-6400",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 15,
"PPD": 2,
"RPab": 17,
"RPpb": 15,
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"RCab": 51,
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"FAW": 16,
"RRD": 4,
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"WCK2CK": 0,
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"WR": 28,
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"WTR_S": 5,
"CCDMW": 16,
"REFI": 3124,
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"RFCab": 224,
"RFCpb": 112,
"RTRS": 1,
"BL_n_min_16": 2,
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"BL_n_L_16": 4,
"BL_n_S_16": 2,
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"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 2,
"pbR2act": 6,
"pbR2pbR": 72,
"clkMhz": 800
}
}
}

Some files were not shown because too many files have changed in this diff Show More