diff --git a/README.md b/README.md index f73f0c25..1fcd24b0 100644 --- a/README.md +++ b/README.md @@ -25,7 +25,7 @@ If you decide to use DRAMSys in your research please cite the papers [2] [3]. To - Open, closed and adaptive page policies [8] - All-bank, same-bank, per-bank and per-2-bank refresh - Staggered power down [5] -- Coupling to **DRAMPower** [4] and **3D-ICE** [8] for power and thermal simulation +- Coupling to **DRAMPower** [4] and for power simulation - **Trace Analyzer** for visual and metric-based result analysis ## Video @@ -33,12 +33,6 @@ The linked video shows the background of DRAMSys and some examples of how simula [![DRAMSys Video](https://img.youtube.com/vi/xdfaGv7MPVo/0.jpg)](https://www.youtube.com/watch?v=xdfaGv7MPVo) -## Architecture and Functionality - -A UML diagram of the software architecture is presented below; different component implementations are left out for simplicity. More information about the architecture and functionality can be found in the papers [1] [2] [3] and in the introduction video on [Youtube](https://www.youtube.com/watch?v=8EkC3mYWpQY). - -UML - ## Trace Analyzer Consulting and Custom-Tailored Modifications To provide better analysis capabilities for DRAM subsystem design space exploration than the usual performance-related outputs to the console, DRAMSys offers the Trace Analyzer. @@ -54,11 +48,10 @@ If you are interested in the Trace Analyzer, if you need support with the setup ## Basic Setup Start using DRAMSys by cloning the repository. -Use the `--recursive` flag to initialize all submodules within the repository, namely **DRAMPower**, **SystemC**, **nlohmann JSON** and **SQLite Amalgamation**. ### Dependencies -DRAMSys requires a **C++17** compiler. The build process is based on **CMake** (minimum version **3.10**). Furthermore, the simulator is based on **SystemC**. SystemC is included as a submodule and will be build automatically with the project. If you want to use an external SystemC version, export the environment variables `SYSTEMC_HOME` (SystemC root directory) and `SYSTEMC_TARGET_ARCH` (e.g., linux64). +DRAMSys requires a **C++17** compiler. The build process is based on **CMake** (minimum version **3.13**). Furthermore, the simulator is based on **SystemC**. SystemC is included as a submodule and will be build automatically with the project. If you want to use an external SystemC version, export the environment variables `SYSTEMC_HOME` (SystemC root directory) and `SYSTEMC_TARGET_ARCH` (e.g., linux64). ### Building DRAMSys @@ -68,19 +61,11 @@ To build the standalone simulator for running memory trace files or a traffic ge $ cd DRAMSys $ mkdir build $ cd build -$ cmake ../DRAMSys/ +$ cmake .. $ make ``` -If you plan to integrate DRAMSys into your own SystemC TLM-2.0 project you can build the DRAMSys library only: - -```bash -$ cd DRAMSys -$ mkdir build -$ cd build -$ cmake ../DRAMSys/library/ -$ make -``` +To include **DRAMPower** in your build enable the CMake option `DRAMSYS_WITH_DRAMPOWER`. If you plan to integrate DRAMSys into your own SystemC TLM-2.0 project you can build the DRAMSys library only by disabling the CMake option `DRAMSYS_BUILD_CLI`. To build DRAMSys on Windows 10 we recommend to use the **Windows Subsystem for Linux (WSL)**. @@ -91,478 +76,26 @@ Information on how to couple DRAMSys with **gem5** can be found [here](DRAMSys/g From the build directory use the commands below to execute the DRAMSys standalone. ```bash -$ cd simulator +$ cd bin $ ./DRAMSys ``` -The default base config file is *ddr3-example.json* located in *DRAMSys/library/resources/simulations*, the default resource folder for all nested config files is *DRAMSys/library/resources*. +The default configuration file is *ddr4-example.json* located in *configs/*, the default folder for all nested configuration files is *configs/*. -To run DRAMSys with a specific base config file: +To run DRAMSys with a specific configuration file: ```bash -$ ./DRAMSys ../../DRAMSys/library/resources/simulations/ddr3-example.json +$ ./DRAMSys ../../configs/lpddr4-example.json ``` -To run DRAMSys with a specific base config file and a resource folder somewhere else to the standard: +To run DRAMSys with a specific configuration file and configuration folder: ```bash -$ ./DRAMSys ../../DRAMSys/tests/example_ddr3/simulations/ddr3-example.json ../../DRAMSys/tests/example_ddr3/ +$ ./DRAMSys ../../tests/tests_regression/DDR3/ddr3-example.json ../../tests/tests_regression/DDR3/ ``` -### DRAMSys Configuration +More information on the configuration can be found [here](configs/README.md). -The DRAMSys executable supports one argument, which is a JSON file that contains certain arguments and the name of nested configuration files for the desired simulation. Alternatively, the contents of nested configuration files can also be added directly to the top configuration file instead of the file name. - -The JSON code below shows an example configuration: - -```json -{ - "simulation": { - "simulationid": "ddr3-example", - "simconfig": "ddr3.json", - "thermalconfig": "config.json", - "memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json", - "addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_brc.json", - "mcconfig":"fifoStrict.json", - "tracesetup": [ - { - "clkMhz": 300, - "name": "ddr3_example.stl" - }, - { - "clkMhz": 2000, - "type": "generator", - "name": "gen0", - "numRequests": 2000, - "rwRatio": 0.85, - "addressDistribution": "random", - "seed": 123456, - "maxPendingReadRequests": 8, - "maxPendingWriteRequests": 8, - "minAddress": 16384, - "maxAddress": 32767 - }, - { - "clkMhz": 1000, - "type": "hammer", - "name": "ham0", - "numRequests": 4000, - "rowIncrement": 2097152 - } - ] - } -} -``` -Field Descriptions: -- "simulationid": simulation file identifier -- "simconfig": configuration file for the DRAMSys simulator -- "thermalconfig": thermal simulation configuration file -- "memspec": memory device configuration file -- "addressmapping": address mapping configuration file -- "mcconfig": memory controller configuration file -- "tracesetup": The trace setup is only used in standalone mode. In library mode or gem5 mode the trace setup is ignored. Each device should be added as a json object inside the "tracesetup" array. - -Each **trace setup** device configuration can be a **trace player** ("type": "player"), a **traffic generator** ("type": "generator") or a **row hammer generator** ("type": "hammer"). By not specifing the **type** parameter, the device will act as a **trace player**. -All device configurations must define a **clkMhz** (operation frequency of the **traffic initiator**) and a **name** (in case of a trace player this specifies the **trace file** to play; in case of a generator this field is only for identification purposes). -The **maxPendingReadRequests** and **maxPendingWriteRequests** parameters define the maximum number of outstanding read/write requests. The current implementation delays all memory accesses if one limit is reached. The default value (0) disables the limit. - -A **traffic generator** can be configured to generate **numRequests** requests in total, of which the **rwRatio** field defines the probability of one request being a read request. The length of a request (in bytes) can be specified with the **dataLength** parameter. The **seed** parameter can be used to produce identical results for all simulations. **minAddress** and **maxAddress** specify the address range, by default the whole address range is used. The parameter **addressDistribution** can either be set to **random** or **sequential**. In case of **sequential** the additional **addressIncrement** field must be specified, defining the address increment after each request. - -The **row hammer generator** is a special traffic generator that mimics a row hammer attack. It generates **numRequests** alternating read requests to two different addresses. The first address is 0x0, the second address is specified by the **rowIncrement** parameter and should decode to a different row in the same bank. Since only one outstanding request is allowed, the controller cannot perform any reordering, forcing a row switch (precharge and activate) for each access. That way the number of activations on the target rows are maximized. - -Most configuration fields reference other JSON files which contain more specialized chunks of the configuration like a memory specification, an address mapping and a memory controller configuration. - - -#### Trace Files - -A **trace file** is a prerecorded file containing memory transactions. Each memory transaction has a time stamp that tells the simulator when it shall happen, a transaction type (*read* or *write*) and a hexadecimal memory address. The optional length parameter (in bytes) allows sending transactions with a custom length that does not match the length of a single DRAM burst access. In this case a length converter has to be added. Write transactions also have to specify a data field when storage is enabled in DRAMSys. - -There are two different kinds of trace files. They differ in their timing behavior and are distinguished by their file extension. - -##### STL Traces (.stl) - -The time stamp corresponds to the time the request is to be issued and it is given in cycles of the bus master device. Example: The device is an FPGA with a frequency of 200 MHz (clock period of 5 ns). If the time stamp is 10 the request is to be issued when time is 50 ns. - -Syntax example: - -``` -# Comment lines begin with # -# cycle: [(length)] command hex-address [hex-data] -31: read 0x400140 -33: read 0x400160 -56: write 0x7fff8000 0x123456789abcdef... -81: (128) read 0x400180 -``` - -##### Relative STL Traces (.rstl) - -The time stamp corresponds to the time the request is to be issued relative to the end of the previous transaction. This results in a simulation in which the trace player is able to react to possible delays due to DRAM bottlenecks. - -Syntax example: - -``` -# Comment lines begin with # -# cycle: [(length)] command hex-address [hex-data] -31: read 0x400140 -2: (512) read 0x400160 -23: write 0x7fff8000 0x123456789abcdef... -10: read 0x400180 -``` - -##### Elastic Traces - -More information about elastic traces can be found in the [gem5 readme](DRAMSys/gem5/README.md). - -#### Trace Player - -A trace player is equivalent to a bus master device (processor, FPGA, etc.). It reads an input trace file and translates each line into a new memory request. By adding a new device element into the trace setup section one can specify a new trace player, its operating frequency and its trace file. - -#### Configuration File Sections - -The main configuration file is divided into self-contained sections. Each of these sections refers to sub-configuration files. Below, the sub-configurations are listed and explained. - -##### Simulator Configuration - -The content of [ddr3.json](DRAMSys/library/resources/configs/simulator/ddr3.json) is presented below as an example. - -```json -{ - "simconfig": { - "SimulationName": "ddr3", - "Debug": false, - "DatabaseRecording": true, - "PowerAnalysis": false, - "EnableWindowing": false, - "WindowSize": 1000, - "ThermalSimulation": false, - "SimulationProgressBar": true, - "CheckTLM2Protocol": false, - "ECCControllerMode": "Disabled", - "UseMalloc": false, - "AddressOffset": 0, - "ErrorChipSeed": 42, - "ErrorCSVFile": "", - "StoreMode": "NoStorage" - } -} -``` - - - *SimulationName* (string) - - Give the name of the simulation for distinguishing from other simulations. - - *Debug* (boolean) - - true: enables debug output on console (only supported by a debug build) - - false: disables debug output - - *DatabaseRecording* (boolean) - - true: enables output database recording for the Trace Analyzer tool - - false: disables output database recording - - *PowerAnalysis* (boolean) - - true: enables live power analysis with DRAMPower - - false: disables power analysis - - *EnableWindowing* (boolean) - - true: enables temporal windowing - - false: disables temporal windowing - - *WindowSize* (unsigned int) - - Size of the window in clock cycles used to evaluate average bandwidth and average power consumption - - *ThermalSimulation* (boolean) - - true: enables thermal simulation ([more information](#dramsys-with-thermal-simulation)) - - false: static temperature during simulation - - *SimulationProgressBar* (boolean) - - true: enables the simulation progress bar - - false: disables the simulation progress bar - - *CheckTLM2Protocol* (boolean) - - true: enables the TLM-2.0 Protocol Checking - - false: disables the TLM-2.0 Protocol Checking - - *ECCControllerMode* (string) - - "Disabled": No ECC controller is used - - "Hamming": Enables an ECC Controller with classic SECDED implementation using Hamming Code - - *UseMalloc* (boolean) - - false: model storage using mmap() (DEFAULT) - - true: allocate memory for modeling storage using malloc() - - *AddressOffset* (unsigned int) - - Address offset of the DRAM subsystem (required for the gem5 coupling). - - *ErrorChipSeed* (unsigned int) - - Seed to initialize the random error generator. - - *ErrorCSVFile* (string) - - CSV file with error injection information. - - *StoreMode* (string) - - "NoStorage": no storage - - "Store": store data without error model - - "ErrorModel": store data with error model [6] - -##### Thermal Simulation - -The thermal simulation configuration can be found [here](#thermal-simulation-configuration). - - -##### Memory Specification - -A file with memory specifications. Timings and currents come from data sheets and measurements and usually do not change. -The fields inside "mempowerspec" can be written directly as a **double** type, "memoryId" and "memoryType" are **string**, all other fields are **unsigned int**. - -##### Address Mapping - -DRAMSys uses the **ConGen** [7] format for address mappings. It provides bit-wise granularity. It also provides the possibility to XOR address bits in order to map page misses to different banks and reduce latencies. - -Used fields: -- "XOR": Defines an XOR connection of a "FIRST" and a "SECOND" bit -- "BYTE_BIT": Address bits that are connected to the byte bits in ascending order -- "COLUMN_BIT": Address bits that are connected to the column bits in ascending order -- "ROW_BIT": Address bits that are connected to the row bits in ascending order -- "BANK_BIT": Address bits that are connected to the bank bits in ascending order -- "BANKGROUP_BIT": Address bits that are connected to the bank group bits in ascending order -- "RANK_BIT": Address bits that are connected to the rank bits in ascending order -- "CHANNEL_BIT": Address bits that are connected to the channel bits in ascending order - -```json -{ - "CONGEN": { - "XOR": [ - { - "FIRST": 13, - "SECOND": 16 - } - ], - "BYTE_BIT": [0,1,2], - "COLUMN_BIT": [3,4,5,6,7,8,9,10,11,12], - "BANK_BIT": [13,14,15], - "ROW_BIT": [16,17,18,19,20,21,22,23,24,25,26,27,28,29] - } -} - -``` - -##### Memory Controller - -An example follows. - -```json -{ - "mcconfig": { - "PagePolicy": "Open", - "Scheduler": "Fifo", - "SchedulerBuffer": "ReadWrite", - "RequestBufferSize": 8, - "CmdMux": "Oldest", - "RespQueue": "Fifo", - "RefreshPolicy": "AllBank", - "RefreshMaxPostponed": 8, - "RefreshMaxPulledin": 8, - "PowerDownPolicy": "NoPowerDown", - "Arbiter": "Fifo", - "MaxActiveTransactions": 128, - "RefreshManagement": true - } -} -``` - - - *PagePolicy* (string) - - "Open": no auto-precharge is performed after read or write commands - - "OpenAdaptive": auto-precharge after read or write commands is only performed if further requests for the targeted bank are stored in the scheduler and all the requests are row misses - - "Closed": auto-precharge is performed after each read or write command - - "ClosedAdaptive": auto-precharge after read or write commands is performed if all further requests for the targeted bank stored in the scheduler are row misses or if there are no further requests stored - - *Scheduler* (string) - - all policies are applied locally to one bank, not globally to the whole channel - - "Fifo": first in, first out policy - - "FrFcfs": first-ready - first-come, first-served policy (row hits are preferred to row misses) - - "FrFcfsGrp": first-ready - first-come, first-served policy with additional grouping of read and write requests - - *SchedulerBuffer* (string) - - "Bankwise": requests are stored in bankwise buffers - - "ReadWrite": read and write requests are stored in different buffers - - "Shared": all requests are stored in one shared buffer - - *RequestBufferSize* (unsigned int) - - depth of a single scheduler buffer entity, total buffer depth depends on the selected scheduler buffer policy - - *CmdMux* (string) - - "Oldest": from all commands that are ready to be issued in the current clock cycle the one that belongs to the oldest transaction has the highest priority; commands from refresh managers have a higher priority than all other commands, commands from power down managers have a lower priority than all other commands - - "Strict": based on "Oldest", in addition, read and write commands are strictly issued in the order their corresponding requests arrived at the channel controller (can only be used in combination with the "Fifo" scheduler) - - *RespQueue* (string) - - "Fifo": the original request order is not restored for outgoing responses - - "Reorder": the original request order is restored for outgoing responses (only within the channel) - - *RefreshPolicy* (string) - - "NoRefresh": refresh is disabled - - "AllBank": all-bank refresh commands are issued (per rank) - - "PerBank": per-bank refresh commands are issued (only available in combination with LPDDR4, Wide I/O 2, GDDR5/5X/6 or HBM2) - - "SameBank": same-bank refresh commands are issued (only available in combination with DDR5) - - *RefreshMaxPostponed* (unsigned int) - - maximum number of refresh commands that can be postponed (with per-bank refresh the number is internally multiplied with the number of banks, with same-bank refresh the number is internally multiplied with the number of banks per bank group) - - *RefreshMaxPulledin* (unsigned int) - - maximum number of refresh commands that can be pulled in (with per-bank refresh the number is internally multiplied with the number of banks, with same-bank refresh the number is internally multiplied with the number of banks per bank group) - - *PowerDownPolicy* (string) - - "NoPowerDown": power down disabled - - "Staggered": staggered power down policy [5] - - *Arbiter* (string) - - "Simple": simple forwarding of transactions to the right channel or initiator - - "Fifo": transactions can be buffered internally to achieve a higher throughput especially in multi-initiator-multi-channel configurations - - "Reorder": based on "Fifo", in addition, the original request order is restored for outgoing responses (separately for each initiator and globally to all channels) - - *MaxActiveTransactions* (unsigned int) - - maximum number of active transactions per initiator (only applies to "Fifo" and "Reorder" arbiter policy) -- *RefreshManagement* (boolean) - - enable the sending of refresh management commands when the number of activates to one bank exceeds a certain management threshold (only supported in DDR5 and LPDDR5) - -## DRAMSys with Thermal Simulation - -The thermal simulation is performed by a **3D-ICE** [8] server accessed through the network. Therefore users interested in thermal simulation during their DRAMSys simulations need to make sure they have a 3D-ICE server up and running before starting. For more information about 3D-ICE visit the [official website](https://www.epfl.ch/labs/esl/open-source-software-projects/3d-ice/). An example video that visualizes the results of a thermal simulation is provided on [Youtube](https://www.youtube.com/watch?v=Eacsq71hHtY). - -#### Installing 3D-ICE - -Install SuperLU dependencies: - -```bash -$ sudo apt-get install build-essential git bison flex libblas-dev -``` - -Download and install SuperLU: - -```bash -$ wget http://crd.lbl.gov/~xiaoye/SuperLU/superlu_4.3.tar.gz -$ tar xvfz superlu_4.3.tar.gz -$ cd SuperLU_4.3/ -$ cp MAKE_INC/make.linux make.inc -``` - -Make sure the *SuperLUroot* variable in *make.inc* is properly set. For example, if you downloaded it to your home folder set as follows: - -```bash -SuperLUroot = $(HOME)/SuperLU_4.3 -``` - -Compile the library: - -```bash -$ make superlulib -``` - -Download and install bison-2.4.1: - -```bash -$ wget http://ftp.gnu.org/gnu/bison/bison-2.4.1.tar.gz -$ tar xvzf bison-2.4.1.tar.gz -$ cd bison-2.4.1 -$ ./configure --program-suffix=-2.4.1 -$ make -$ sudo make install -``` - -[Download](https://www.epfl.ch/labs/esl/open-source-software-projects/3d-ice/3d-ice-download/) the lastest version of 3D-ICE. Make sure you got version 2.2.6 or greater. - -Unzip the archive and go to the 3D-ICE directory: - -```bash -$ unzip 3d-ice-latest.zip -$ cd 3d-ice-latest/3d-ice-2.2.6 -``` - -Open the makefile.def and set the following variables properly, e.g.: - -```bash -SLU_MAIN = $(HOME)/SuperLU_$(SLU_VERSION) -YACC = bison-2.4.1 - -SYSTEMC_VERSION = 2.3.4 -SYSTEMC_ARCH = linux64 -SYSTEMC_MAIN = $(HOME)/systemc-$(SYSTEMC_VERSION) -SYSTEMC_INCLUDE = $(SYSTEMC_MAIN)/include -SYSTEMC_LIB = $(SYSTEMC_MAIN)/lib-$(SYSTEMC_ARCH) -``` - -In case you are using the SystemC submodule and DRAMSys is located in your home directory the variables should be set as follows: - -```bash -SYSTEMC_INCLUDE = $(HOME)/DRAMSys/DRAMSys/library/src/common/third_party/systemc/src -SYSTEMC_LIB = $(HOME)/DRAMSys/build/library/src/common/third_party/systemc/src -``` - -Compile 3D-ICE with SystemC TLM-2.0 support: - -```bash -$ make SYSTEMC_WRAPPER=y -``` - -Export the environment variable `LIBTHREED_ICE_HOME`: - -```bash -$ export LIBTHREED_ICE_HOME=${HOME}/3d-ice-latest/3d-ice-2.2.6 -``` - -#### Running DRAMSys with Thermal Simulation - -In order to run DRAMSys with thermal simulation you have to rerun CMake and rebuild the project. The example input trace file can be generated with a Perl script: - - ```bash -$ cd DRAMSys/DRAMSys/library/resources/traces -$ ./generateErrorTest.pl > test_error.stl - ``` - -Before starting DRAMSys it is necessary to run the 3D-ICE server passing to it two arguments: a suitable configuration file and a socket port number. And then wait until the server is ready to receive requests. - -```bash -$ cd DRAMSys/DRAMSys/library/resources/configs/thermalsim -$ ~/3d-ice-latest/3d-ice-2.2.6/bin/3D-ICE-Server stack.stk 11880 -Preparing stk data ... done ! -Preparing thermal data ... done ! -Creating socket ... done ! -Waiting for client ... -``` - -In another terminal or terminal tab start DRAMSys with the special thermal simulation config: - -```bash -$ cd DRAMSys/build/simulator/ -$ ./DRAMSys ../../DRAMSys/library/resources/simulations/wideio-thermal.json -``` - -#### Thermal Simulation Configuration - -The content of [config.json](DRAMSys/library/resources/configs/thermalsim/config.json) is presented below as an example. - -```json -{ - "thermalsimconfig": { - "TemperatureScale": "Celsius", - "StaticTemperatureDefaultValue": 89, - "ThermalSimPeriod": 100, - "ThermalSimUnit": "us", - "PowerInfoFile": "powerInfo.json", - "IceServerIp": "127.0.0.1", - "IceServerPort": 11880, - "SimPeriodAdjustFactor": 10, - "NPowStableCyclesToIncreasePeriod": 5, - "GenerateTemperatureMap": true, - "GeneratePowerMap": true - } -} -``` - - - *TemperatureScale* (string) - - "Celsius" - - "Fahrenheit" - - "Kelvin" - - *StaticTemperatureDefaultValue* (int) - - Temperature value for simulations with static temperature - - *ThermalSimPeriod* (double) - - Period of the thermal simulation - - *ThermalSimUnit* (string) - - "s": seconds - - "ms": millisecond - - "us": microseconds - - "ns": nanoseconds - - "ps": picoseconds - - "fs": femtoseconds - - *PowerInfoFile* (string) - - File containing power related information: devices identifiers, initial power values and power thresholds. - - *IceServerIp* (string) - - 3D-ICE server IP address - - *IceServerPort* (unsigned int) - - 3D-ICE server port - - *SimPeriodAdjustFactor* (unsigned int) - - When substantial changes in power occur (i.e., changes that exceed the thresholds), then the simulation period will be divided by this number causing the thermal simulation to be executed more often. - - *NPowStableCyclesToIncreasePeriod* (unsigned int) - - Wait this number of thermal simulation cycles with power stability (i.e., changes that do not exceed the thresholds) to start increasing the simulation period back to its configured value. - - *GenerateTemperatureMap* (boolean) - - true: generate temperature map files during thermal simulation - - false: do not generate temperature map files during thermal simulation - - *GeneratePowerMap* (boolean) - - true: generate power map files during thermal simulation - - false: do not generate power map files during thermal simulation ## Acknowledgements diff --git a/configs/README.md b/configs/README.md new file mode 100644 index 00000000..6ed1fbef --- /dev/null +++ b/configs/README.md @@ -0,0 +1,266 @@ +# Configuration + +The DRAMSys executable supports one argument, which is a JSON file that contains certain arguments and the name of nested configuration files for the desired simulation. Alternatively, the contents of nested configuration files can also be added directly to the top configuration file instead of the file name. + +The JSON code below shows an example configuration: + +```json +{ + "simulation": { + "simulationid": "ddr3-example", + "simconfig": "example.json", + "memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json", + "addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_brc.json", + "mcconfig":"fifoStrict.json", + "tracesetup": [ + { + "clkMhz": 300, + "name": "example.stl" + }, + { + "clkMhz": 2000, + "type": "generator", + "name": "gen0", + "numRequests": 2000, + "rwRatio": 0.85, + "addressDistribution": "random", + "seed": 123456, + "maxPendingReadRequests": 8, + "maxPendingWriteRequests": 8, + "minAddress": 16384, + "maxAddress": 32767 + }, + { + "clkMhz": 1000, + "type": "hammer", + "name": "ham0", + "numRequests": 4000, + "rowIncrement": 2097152 + } + ] + } +} +``` +Field Descriptions: +- "simulationid": simulation file identifier +- "simconfig": configuration file for the DRAMSys simulator +- "memspec": memory device configuration file +- "addressmapping": address mapping configuration file +- "mcconfig": memory controller configuration file +- "tracesetup": The trace setup is only used in standalone mode. In library mode or gem5 mode the trace setup is ignored. Each device should be added as a json object inside the "tracesetup" array. + +Each **trace setup** device configuration can be a **trace player** ("type": "player"), a **traffic generator** ("type": "generator") or a **row hammer generator** ("type": "hammer"). By not specifing the **type** parameter, the device will act as a **trace player**. +All device configurations must define a **clkMhz** (operation frequency of the **traffic initiator**) and a **name** (in case of a trace player this specifies the **trace file** to play; in case of a generator this field is only for identification purposes). +The **maxPendingReadRequests** and **maxPendingWriteRequests** parameters define the maximum number of outstanding read/write requests. The current implementation delays all memory accesses if one limit is reached. The default value (0) disables the limit. + +A **traffic generator** can be configured to generate **numRequests** requests in total, of which the **rwRatio** field defines the probability of one request being a read request. The length of a request (in bytes) can be specified with the **dataLength** parameter. The **seed** parameter can be used to produce identical results for all simulations. **minAddress** and **maxAddress** specify the address range, by default the whole address range is used. The parameter **addressDistribution** can either be set to **random** or **sequential**. In case of **sequential** the additional **addressIncrement** field must be specified, defining the address increment after each request. + +The **row hammer generator** is a special traffic generator that mimics a row hammer attack. It generates **numRequests** alternating read requests to two different addresses. The first address is 0x0, the second address is specified by the **rowIncrement** parameter and should decode to a different row in the same bank. Since only one outstanding request is allowed, the controller cannot perform any reordering, forcing a row switch (precharge and activate) for each access. That way the number of activations on the target rows are maximized. + +Most configuration fields reference other JSON files which contain more specialized chunks of the configuration like a memory specification, an address mapping and a memory controller configuration. + + +## Trace Files + +A **trace file** is a prerecorded file containing memory transactions. Each memory transaction has a time stamp that tells the simulator when it shall happen, a transaction type (*read* or *write*) and a hexadecimal memory address. The optional length parameter (in bytes) allows sending transactions with a custom length that does not match the length of a single DRAM burst access. In this case a length converter has to be added. Write transactions also have to specify a data field when storage is enabled in DRAMSys. + +There are two different kinds of trace files. They differ in their timing behavior and are distinguished by their file extension. + +### STL Traces (.stl) + +The time stamp corresponds to the time the request is to be issued and it is given in cycles of the bus master device. Example: The device is an FPGA with a frequency of 200 MHz (clock period of 5 ns). If the time stamp is 10 the request is to be issued when time is 50 ns. + +Syntax example: + +``` +# Comment lines begin with # +# cycle: [(length)] command hex-address [hex-data] +31: read 0x400140 +33: read 0x400160 +56: write 0x7fff8000 0x123456789abcdef... +81: (128) read 0x400180 +``` + +### Relative STL Traces (.rstl) + +The time stamp corresponds to the time the request is to be issued relative to the end of the previous transaction. This results in a simulation in which the trace player is able to react to possible delays due to DRAM bottlenecks. + +Syntax example: + +``` +# Comment lines begin with # +# cycle: [(length)] command hex-address [hex-data] +31: read 0x400140 +2: (512) read 0x400160 +23: write 0x7fff8000 0x123456789abcdef... +10: read 0x400180 +``` + +### Elastic Traces + +More information about elastic traces can be found in the [gem5 readme](../src/gem5/README.md). + +## Trace Player + +A trace player is equivalent to a bus master device (processor, FPGA, etc.). It reads an input trace file and translates each line into a new memory request. By adding a new device element into the trace setup section one can specify a new trace player, its operating frequency and its trace file. + +## Configuration File Sections + +The main configuration file is divided into self-contained sections. Each of these sections refers to sub-configuration files. Below, the sub-configurations are listed and explained. + +### Simulator Configuration + +The content of [ddr3.json](simconfig/example.json) is presented below as an example. + +```json +{ + "simconfig": { + "SimulationName": "example", + "Debug": false, + "DatabaseRecording": true, + "PowerAnalysis": false, + "EnableWindowing": false, + "WindowSize": 1000, + "SimulationProgressBar": true, + "CheckTLM2Protocol": false, + "UseMalloc": false, + "AddressOffset": 0, + "StoreMode": "NoStorage" + } +} +``` + +- *SimulationName* (string) + - Give the name of the simulation for distinguishing from other simulations. +- *Debug* (boolean) + - true: enables debug output on console (only supported by a debug build) + - false: disables debug output +- *DatabaseRecording* (boolean) + - true: enables output database recording for the Trace Analyzer tool + - false: disables output database recording +- *PowerAnalysis* (boolean) + - true: enables live power analysis with DRAMPower + - false: disables power analysis +- *EnableWindowing* (boolean) + - true: enables temporal windowing + - false: disables temporal windowing +- *WindowSize* (unsigned int) + - Size of the window in clock cycles used to evaluate average bandwidth and average power consumption +- *SimulationProgressBar* (boolean) + - true: enables the simulation progress bar + - false: disables the simulation progress bar +- *CheckTLM2Protocol* (boolean) + - true: enables the TLM-2.0 Protocol Checking + - false: disables the TLM-2.0 Protocol Checking +- *UseMalloc* (boolean) + - false: model storage using mmap() (DEFAULT) + - true: allocate memory for modeling storage using malloc() +- *AddressOffset* (unsigned int) + - Address offset of the DRAM subsystem (required for the gem5 coupling). +- *StoreMode* (string) + - "NoStorage": no storage + - "Store": store data without error model + +### Memory Specification + +A file with memory specifications. Timings and currents come from data sheets and measurements and usually do not change. +The fields inside "mempowerspec" can be written directly as a **double** type, "memoryId" and "memoryType" are **string**, all other fields are **unsigned int**. + +### Address Mapping + +DRAMSys uses the **ConGen** [7] format for address mappings. It provides bit-wise granularity. It also provides the possibility to XOR address bits in order to map page misses to different banks and reduce latencies. + +Used fields: +- "XOR": Defines an XOR connection of a "FIRST" and a "SECOND" bit +- "BYTE_BIT": Address bits that are connected to the byte bits in ascending order +- "COLUMN_BIT": Address bits that are connected to the column bits in ascending order +- "ROW_BIT": Address bits that are connected to the row bits in ascending order +- "BANK_BIT": Address bits that are connected to the bank bits in ascending order +- "BANKGROUP_BIT": Address bits that are connected to the bank group bits in ascending order +- "RANK_BIT": Address bits that are connected to the rank bits in ascending order +- "CHANNEL_BIT": Address bits that are connected to the channel bits in ascending order + +```json +{ + "CONGEN": { + "XOR": [ + { + "FIRST": 13, + "SECOND": 16 + } + ], + "BYTE_BIT": [0,1,2], + "COLUMN_BIT": [3,4,5,6,7,8,9,10,11,12], + "BANK_BIT": [13,14,15], + "ROW_BIT": [16,17,18,19,20,21,22,23,24,25,26,27,28,29] + } +} + +``` + +### Memory Controller + +An example follows. + +```json +{ + "mcconfig": { + "PagePolicy": "Open", + "Scheduler": "Fifo", + "SchedulerBuffer": "ReadWrite", + "RequestBufferSize": 8, + "CmdMux": "Oldest", + "RespQueue": "Fifo", + "RefreshPolicy": "AllBank", + "RefreshMaxPostponed": 8, + "RefreshMaxPulledin": 8, + "PowerDownPolicy": "NoPowerDown", + "Arbiter": "Fifo", + "MaxActiveTransactions": 128, + "RefreshManagement": true + } +} +``` + +- *PagePolicy* (string) + - "Open": no auto-precharge is performed after read or write commands + - "OpenAdaptive": auto-precharge after read or write commands is only performed if further requests for the targeted bank are stored in the scheduler and all the requests are row misses + - "Closed": auto-precharge is performed after each read or write command + - "ClosedAdaptive": auto-precharge after read or write commands is performed if all further requests for the targeted bank stored in the scheduler are row misses or if there are no further requests stored +- *Scheduler* (string) + - all policies are applied locally to one bank, not globally to the whole channel + - "Fifo": first in, first out policy + - "FrFcfs": first-ready - first-come, first-served policy (row hits are preferred to row misses) + - "FrFcfsGrp": first-ready - first-come, first-served policy with additional grouping of read and write requests +- *SchedulerBuffer* (string) + - "Bankwise": requests are stored in bankwise buffers + - "ReadWrite": read and write requests are stored in different buffers + - "Shared": all requests are stored in one shared buffer +- *RequestBufferSize* (unsigned int) + - depth of a single scheduler buffer entity, total buffer depth depends on the selected scheduler buffer policy +- *CmdMux* (string) + - "Oldest": from all commands that are ready to be issued in the current clock cycle the one that belongs to the oldest transaction has the highest priority; commands from refresh managers have a higher priority than all other commands, commands from power down managers have a lower priority than all other commands + - "Strict": based on "Oldest", in addition, read and write commands are strictly issued in the order their corresponding requests arrived at the channel controller (can only be used in combination with the "Fifo" scheduler) +- *RespQueue* (string) + - "Fifo": the original request order is not restored for outgoing responses + - "Reorder": the original request order is restored for outgoing responses (only within the channel) +- *RefreshPolicy* (string) + - "NoRefresh": refresh is disabled + - "AllBank": all-bank refresh commands are issued (per rank) + - "PerBank": per-bank refresh commands are issued (only available in combination with LPDDR4, Wide I/O 2, GDDR5/5X/6 or HBM2) + - "SameBank": same-bank refresh commands are issued (only available in combination with DDR5) +- *RefreshMaxPostponed* (unsigned int) + - maximum number of refresh commands that can be postponed (with per-bank refresh the number is internally multiplied with the number of banks, with same-bank refresh the number is internally multiplied with the number of banks per bank group) +- *RefreshMaxPulledin* (unsigned int) + - maximum number of refresh commands that can be pulled in (with per-bank refresh the number is internally multiplied with the number of banks, with same-bank refresh the number is internally multiplied with the number of banks per bank group) +- *PowerDownPolicy* (string) + - "NoPowerDown": power down disabled + - "Staggered": staggered power down policy [5] +- *Arbiter* (string) + - "Simple": simple forwarding of transactions to the right channel or initiator + - "Fifo": transactions can be buffered internally to achieve a higher throughput especially in multi-initiator-multi-channel configurations + - "Reorder": based on "Fifo", in addition, the original request order is restored for outgoing responses (separately for each initiator and globally to all channels) +- *MaxActiveTransactions* (unsigned int) + - maximum number of active transactions per initiator (only applies to "Fifo" and "Reorder" arbiter policy) +- *RefreshManagement* (boolean) + - enable the sending of refresh management commands when the number of activates to one bank exceeds a certain management threshold (only supported in DDR5 and LPDDR5) diff --git a/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.json b/configs/addressmapping/am_ddr3_4x4Gbx16_dimm_p2KB_brc.json similarity index 100% rename from resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.json rename to configs/addressmapping/am_ddr3_4x4Gbx16_dimm_p2KB_brc.json diff --git a/resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.json b/configs/addressmapping/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.json similarity index 100% rename from resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.json rename to configs/addressmapping/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.json diff --git a/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.json b/configs/addressmapping/am_ddr3_8x1Gbx8_dimm_p1KB_brc.json similarity index 100% rename from resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.json rename to configs/addressmapping/am_ddr3_8x1Gbx8_dimm_p1KB_brc.json diff --git a/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json b/configs/addressmapping/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json similarity index 100% rename from resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json rename to configs/addressmapping/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json diff --git a/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.json b/configs/addressmapping/am_ddr3_8x2Gbx8_dimm_p1KB_brc.json similarity index 100% rename from resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.json rename to configs/addressmapping/am_ddr3_8x2Gbx8_dimm_p1KB_brc.json diff --git a/resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.json b/configs/addressmapping/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.json similarity index 100% rename from resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.json rename to configs/addressmapping/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.json diff --git a/resources/configs/amconfigs/am_ddr3_x16_brc.json b/configs/addressmapping/am_ddr3_x16_brc.json similarity index 100% rename from resources/configs/amconfigs/am_ddr3_x16_brc.json rename to configs/addressmapping/am_ddr3_x16_brc.json diff --git a/resources/configs/amconfigs/am_ddr3_x16_rbc.json b/configs/addressmapping/am_ddr3_x16_rbc.json similarity index 100% rename from resources/configs/amconfigs/am_ddr3_x16_rbc.json rename to configs/addressmapping/am_ddr3_x16_rbc.json diff --git a/resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json b/configs/addressmapping/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json similarity index 100% rename from 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rename to configs/addressmapping/am_ddr5_2x8x2Gbx4_dimm_p1KB_rbc.json diff --git a/resources/configs/amconfigs/am_ddr5_2x8x8x2Gbx4_dimm_p1KB_rbc.json b/configs/addressmapping/am_ddr5_2x8x8x2Gbx4_dimm_p1KB_rbc.json similarity index 100% rename from resources/configs/amconfigs/am_ddr5_2x8x8x2Gbx4_dimm_p1KB_rbc.json rename to configs/addressmapping/am_ddr5_2x8x8x2Gbx4_dimm_p1KB_rbc.json diff --git a/resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.json b/configs/addressmapping/am_hbm2_8Gb_pc_brc.json similarity index 100% rename from resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.json rename to configs/addressmapping/am_hbm2_8Gb_pc_brc.json diff --git a/resources/configs/amconfigs/am_hbm3_8Gb_pc_brc.json b/configs/addressmapping/am_hbm3_8Gb_pc_brc.json similarity index 100% rename from resources/configs/amconfigs/am_hbm3_8Gb_pc_brc.json rename to configs/addressmapping/am_hbm3_8Gb_pc_brc.json diff --git a/resources/configs/amconfigs/am_lpddr4_1Gbx16_baroco.json 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from resources/configs/amconfigs/am_stt-mram_8x2Gbx8_dimm_p1KB_rbc.json rename to configs/addressmapping/am_stt-mram_8x2Gbx8_dimm_p1KB_rbc.json diff --git a/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.json b/configs/addressmapping/am_wideio2_4x64_4x2Gb_brc.json similarity index 100% rename from resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.json rename to configs/addressmapping/am_wideio2_4x64_4x2Gb_brc.json diff --git a/resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.json b/configs/addressmapping/am_wideio2_4x64_4x2Gb_rbc.json similarity index 100% rename from resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.json rename to configs/addressmapping/am_wideio2_4x64_4x2Gb_rbc.json diff --git a/resources/configs/amconfigs/am_wideio_4x1Gb_brc.json b/configs/addressmapping/am_wideio_4x1Gb_brc.json similarity index 100% rename from resources/configs/amconfigs/am_wideio_4x1Gb_brc.json rename to configs/addressmapping/am_wideio_4x1Gb_brc.json diff --git a/resources/configs/amconfigs/am_wideio_4x1Gb_rbc.json b/configs/addressmapping/am_wideio_4x1Gb_rbc.json similarity index 100% rename from resources/configs/amconfigs/am_wideio_4x1Gb_rbc.json rename to configs/addressmapping/am_wideio_4x1Gb_rbc.json diff --git a/resources/configs/amconfigs/am_wideio_4x256Mb_brc.json b/configs/addressmapping/am_wideio_4x256Mb_brc.json similarity index 100% rename from resources/configs/amconfigs/am_wideio_4x256Mb_brc.json rename to configs/addressmapping/am_wideio_4x256Mb_brc.json diff --git a/resources/configs/amconfigs/am_wideio_4x256Mb_rbc.json b/configs/addressmapping/am_wideio_4x256Mb_rbc.json similarity index 100% rename from resources/configs/amconfigs/am_wideio_4x256Mb_rbc.json rename to configs/addressmapping/am_wideio_4x256Mb_rbc.json diff --git a/resources/configs/amconfigs/am_wideio_4x2Gb_brc.json b/configs/addressmapping/am_wideio_4x2Gb_brc.json similarity index 100% rename from resources/configs/amconfigs/am_wideio_4x2Gb_brc.json rename to configs/addressmapping/am_wideio_4x2Gb_brc.json diff --git a/resources/configs/amconfigs/am_wideio_4x2Gb_rbc.json b/configs/addressmapping/am_wideio_4x2Gb_rbc.json similarity index 100% rename from resources/configs/amconfigs/am_wideio_4x2Gb_rbc.json rename to configs/addressmapping/am_wideio_4x2Gb_rbc.json diff --git a/resources/configs/amconfigs/am_wideio_4x4Gb_brc.json b/configs/addressmapping/am_wideio_4x4Gb_brc.json similarity index 100% rename from resources/configs/amconfigs/am_wideio_4x4Gb_brc.json rename to configs/addressmapping/am_wideio_4x4Gb_brc.json diff --git a/resources/configs/amconfigs/am_wideio_4x4Gb_rbc.json b/configs/addressmapping/am_wideio_4x4Gb_rbc.json similarity index 100% rename from resources/configs/amconfigs/am_wideio_4x4Gb_rbc.json rename to configs/addressmapping/am_wideio_4x4Gb_rbc.json diff --git a/resources/configs/amconfigs/am_wideio_4x512Mb_brc.json b/configs/addressmapping/am_wideio_4x512Mb_brc.json similarity index 100% rename from resources/configs/amconfigs/am_wideio_4x512Mb_brc.json rename to configs/addressmapping/am_wideio_4x512Mb_brc.json diff --git a/resources/configs/amconfigs/am_wideio_4x512Mb_rbc.json b/configs/addressmapping/am_wideio_4x512Mb_rbc.json similarity index 100% rename from resources/configs/amconfigs/am_wideio_4x512Mb_rbc.json rename to configs/addressmapping/am_wideio_4x512Mb_rbc.json diff --git a/resources/configs/amconfigs/am_wideio_thermal.json b/configs/addressmapping/am_wideio_thermal.json similarity index 100% rename from resources/configs/amconfigs/am_wideio_thermal.json rename to configs/addressmapping/am_wideio_thermal.json diff --git a/resources/simulations/ddr3-example.json b/configs/ddr3-example.json similarity index 90% rename from resources/simulations/ddr3-example.json rename to configs/ddr3-example.json index faa86fc9..4a947a58 100644 --- a/resources/simulations/ddr3-example.json +++ b/configs/ddr3-example.json @@ -5,7 +5,6 @@ "memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json", "simconfig": "example.json", "simulationid": "ddr3-example", - "thermalconfig": "config.json", "tracesetup": [ { "clkMhz": 800, diff --git a/resources/simulations/ddr3-gem5-se.json b/configs/ddr3-gem5-se.json similarity index 74% rename from resources/simulations/ddr3-gem5-se.json rename to configs/ddr3-gem5-se.json index 29d989e0..a340dc39 100644 --- a/resources/simulations/ddr3-gem5-se.json +++ b/configs/ddr3-gem5-se.json @@ -4,7 +4,6 @@ "mcconfig": "fifoStrict.json", "memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json", "simconfig": "gem5_se.json", - "simulationid": "ddr3-gem5-se", - "thermalconfig": "config.json" + "simulationid": "ddr3-gem5-se" } } diff --git a/resources/simulations/ddr4-example.json b/configs/ddr4-example.json similarity index 90% rename from resources/simulations/ddr4-example.json rename to configs/ddr4-example.json index 3e722fd8..645ca907 100644 --- a/resources/simulations/ddr4-example.json +++ b/configs/ddr4-example.json @@ -5,7 +5,6 @@ "memspec": "JEDEC_4Gb_DDR4-1866_8bit_A.json", "simconfig": "example.json", "simulationid": "ddr4-example", - "thermalconfig": "config.json", "tracesetup": [ { "clkMhz": 200, diff --git a/resources/simulations/ddr5-example.json b/configs/ddr5-example.json similarity index 90% rename from resources/simulations/ddr5-example.json rename to configs/ddr5-example.json index 04691d6c..d66dae74 100644 --- a/resources/simulations/ddr5-example.json +++ b/configs/ddr5-example.json @@ -5,7 +5,6 @@ "memspec": "JEDEC_2x8x2Gbx4_DDR5-3200A.json", "simconfig": "example.json", "simulationid": "ddr5-example", - "thermalconfig": "config.json", "tracesetup": [ { "clkMhz": 2000, diff --git a/resources/simulations/ddr5-generator-example.json b/configs/ddr5-generator-example.json similarity index 96% rename from resources/simulations/ddr5-generator-example.json rename to configs/ddr5-generator-example.json index 25ad5e20..d3a74944 100644 --- a/resources/simulations/ddr5-generator-example.json +++ b/configs/ddr5-generator-example.json @@ -5,7 +5,6 @@ "memspec": "JEDEC_2x8x2Gbx4_DDR5-3200A.json", "simconfig": "example.json", "simulationid": "ddr5-example", - "thermalconfig": "config.json", "tracesetup": [ { "clkMhz": 2000, diff --git a/resources/simulations/ddr5-rfm.json b/configs/ddr5-rfm.json similarity index 95% rename from resources/simulations/ddr5-rfm.json rename to configs/ddr5-rfm.json index c96737a1..c8bb8160 100644 --- a/resources/simulations/ddr5-rfm.json +++ b/configs/ddr5-rfm.json @@ -5,7 +5,6 @@ "memspec": "JEDEC_2x2x8x4Gbx4_DDR5-3200A.json", "simconfig": "example.json", "simulationid": "ddr5-example", - "thermalconfig": "config.json", "tracesetup": [ { "clkMhz": 2000, diff --git a/resources/gem5/gem5_etrace/config.ini b/configs/gem5/gem5_etrace/config.ini similarity index 100% rename from resources/gem5/gem5_etrace/config.ini rename to configs/gem5/gem5_etrace/config.ini diff --git a/resources/gem5/gem5_etrace/system.cpu.traceListener.data.gz b/configs/gem5/gem5_etrace/system.cpu.traceListener.data.gz similarity index 100% rename from resources/gem5/gem5_etrace/system.cpu.traceListener.data.gz rename to configs/gem5/gem5_etrace/system.cpu.traceListener.data.gz diff --git a/resources/gem5/gem5_etrace/system.cpu.traceListener.inst.gz b/configs/gem5/gem5_etrace/system.cpu.traceListener.inst.gz similarity index 100% rename from resources/gem5/gem5_etrace/system.cpu.traceListener.inst.gz rename to configs/gem5/gem5_etrace/system.cpu.traceListener.inst.gz diff --git a/resources/gem5/gem5_se/hello-ARM/config.ini b/configs/gem5/gem5_se/hello-ARM/config.ini similarity index 100% rename from resources/gem5/gem5_se/hello-ARM/config.ini rename to configs/gem5/gem5_se/hello-ARM/config.ini diff --git a/resources/gem5/gem5_se/hello-ARM/hello b/configs/gem5/gem5_se/hello-ARM/hello similarity index 100% rename from resources/gem5/gem5_se/hello-ARM/hello rename to configs/gem5/gem5_se/hello-ARM/hello diff --git a/resources/gem5/gem5_se/hello-X86/config.ini b/configs/gem5/gem5_se/hello-X86/config.ini similarity index 100% rename from resources/gem5/gem5_se/hello-X86/config.ini rename to configs/gem5/gem5_se/hello-X86/config.ini diff --git a/resources/gem5/gem5_se/hello-X86/hello b/configs/gem5/gem5_se/hello-X86/hello similarity index 100% rename from resources/gem5/gem5_se/hello-X86/hello rename to configs/gem5/gem5_se/hello-X86/hello diff --git a/resources/simulations/hbm2-example.json b/configs/hbm2-example.json similarity index 90% rename from resources/simulations/hbm2-example.json rename to configs/hbm2-example.json index 58d44caa..7b48bc60 100644 --- a/resources/simulations/hbm2-example.json +++ b/configs/hbm2-example.json @@ -5,7 +5,6 @@ "memspec": "HBM2.json", "simconfig": "example.json", "simulationid": "hbm2-example", - "thermalconfig": "config.json", "tracesetup": [ { "clkMhz": 1000, diff --git a/resources/simulations/hbm3-example.json b/configs/hbm3-example.json similarity index 90% rename from resources/simulations/hbm3-example.json rename to configs/hbm3-example.json index 89bfadbf..4d3505b8 100644 --- a/resources/simulations/hbm3-example.json +++ b/configs/hbm3-example.json @@ -5,7 +5,6 @@ "memspec": "HBM3.json", "simconfig": "example.json", "simulationid": "hbm3-example", - "thermalconfig": "config.json", "tracesetup": [ { "clkMhz": 1000, diff --git a/resources/simulations/lpddr4-example.json b/configs/lpddr4-example.json similarity index 90% rename from resources/simulations/lpddr4-example.json rename to configs/lpddr4-example.json index 5a999651..39ba60fd 100644 --- a/resources/simulations/lpddr4-example.json +++ b/configs/lpddr4-example.json @@ -5,7 +5,6 @@ "memspec": "JEDEC_8Gb_LPDDR4-3200_16bit.json", "simconfig": "example.json", "simulationid": "lpddr4-example", - "thermalconfig": "config.json", "tracesetup": [ { "clkMhz": 200, diff --git a/resources/simulations/lpddr5-example.json b/configs/lpddr5-example.json similarity index 90% rename from resources/simulations/lpddr5-example.json rename to configs/lpddr5-example.json index 271df1f5..26179bec 100644 --- a/resources/simulations/lpddr5-example.json +++ b/configs/lpddr5-example.json @@ -5,7 +5,6 @@ "memspec": "JEDEC_1Gbx16_BG_LPDDR5-6400.json", "simconfig": "example.json", "simulationid": "lpddr5-example", - "thermalconfig": "config.json", "tracesetup": [ { "clkMhz": 200, diff --git a/resources/configs/mcconfigs/fifo.json b/configs/mcconfig/fifo.json similarity index 100% rename from resources/configs/mcconfigs/fifo.json rename to configs/mcconfig/fifo.json diff --git a/resources/configs/mcconfigs/fifoStrict.json b/configs/mcconfig/fifoStrict.json similarity index 100% rename from resources/configs/mcconfigs/fifoStrict.json rename to configs/mcconfig/fifoStrict.json diff --git a/resources/configs/mcconfigs/fr_fcfs.json b/configs/mcconfig/fr_fcfs.json similarity index 100% rename from resources/configs/mcconfigs/fr_fcfs.json rename to configs/mcconfig/fr_fcfs.json diff --git a/resources/configs/mcconfigs/fr_fcfs_grp.json b/configs/mcconfig/fr_fcfs_grp.json similarity index 100% rename from resources/configs/mcconfigs/fr_fcfs_grp.json rename to configs/mcconfig/fr_fcfs_grp.json diff --git a/resources/configs/mcconfigs/fr_fcfs_noref.json b/configs/mcconfig/fr_fcfs_noref.json similarity index 100% rename from resources/configs/mcconfigs/fr_fcfs_noref.json rename to configs/mcconfig/fr_fcfs_noref.json diff --git a/resources/configs/mcconfigs/fr_fcfs_refp2b.json b/configs/mcconfig/fr_fcfs_refp2b.json similarity index 100% rename from resources/configs/mcconfigs/fr_fcfs_refp2b.json rename to configs/mcconfig/fr_fcfs_refp2b.json diff --git a/resources/configs/mcconfigs/fr_fcfs_rfm.json b/configs/mcconfig/fr_fcfs_rfm.json similarity index 100% rename from resources/configs/mcconfigs/fr_fcfs_rfm.json rename to configs/mcconfig/fr_fcfs_rfm.json diff --git a/resources/configs/memspecs/HBM2.json b/configs/memspec/HBM2.json similarity index 100% rename from resources/configs/memspecs/HBM2.json rename to configs/memspec/HBM2.json diff --git a/resources/configs/memspecs/HBM3.json b/configs/memspec/HBM3.json similarity index 100% rename from resources/configs/memspecs/HBM3.json rename to configs/memspec/HBM3.json diff --git a/resources/configs/memspecs/JEDEC_1Gbx16_16B_LPDDR5-0533.json b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-0533.json similarity index 100% rename from resources/configs/memspecs/JEDEC_1Gbx16_16B_LPDDR5-0533.json rename to configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-0533.json diff --git a/resources/configs/memspecs/JEDEC_1Gbx16_16B_LPDDR5-1067.json b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-1067.json similarity index 100% rename from resources/configs/memspecs/JEDEC_1Gbx16_16B_LPDDR5-1067.json rename to configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-1067.json diff --git a/resources/configs/memspecs/JEDEC_1Gbx16_16B_LPDDR5-1600.json b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-1600.json similarity index 100% rename from resources/configs/memspecs/JEDEC_1Gbx16_16B_LPDDR5-1600.json rename to configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-1600.json diff --git a/resources/configs/memspecs/JEDEC_1Gbx16_16B_LPDDR5-2133.json b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-2133.json similarity index 100% rename from resources/configs/memspecs/JEDEC_1Gbx16_16B_LPDDR5-2133.json rename to configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-2133.json diff --git a/resources/configs/memspecs/JEDEC_1Gbx16_16B_LPDDR5-2750.json b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-2750.json similarity index 100% rename from resources/configs/memspecs/JEDEC_1Gbx16_16B_LPDDR5-2750.json rename to configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-2750.json diff --git a/resources/configs/memspecs/JEDEC_1Gbx16_16B_LPDDR5-3200.json b/configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-3200.json similarity index 100% rename from resources/configs/memspecs/JEDEC_1Gbx16_16B_LPDDR5-3200.json rename to configs/memspec/JEDEC_1Gbx16_16B_LPDDR5-3200.json diff --git a/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-0533.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-0533.json similarity index 100% rename from resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-0533.json rename to configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-0533.json diff --git a/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-1067.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-1067.json similarity index 100% rename from resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-1067.json rename to configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-1067.json diff --git a/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-1600.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-1600.json similarity index 100% rename from resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-1600.json rename to configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-1600.json diff --git a/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-2133.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-2133.json similarity index 100% rename from resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-2133.json rename to configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-2133.json diff --git a/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-2750.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-2750.json similarity index 100% rename from resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-2750.json rename to configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-2750.json diff --git a/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-3200.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-3200.json similarity index 100% rename from resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-3200.json rename to configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-3200.json diff --git a/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-3733.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-3733.json similarity index 100% rename from resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-3733.json rename to configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-3733.json diff --git a/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-4267.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-4267.json similarity index 100% rename from resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-4267.json rename to configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-4267.json diff --git a/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-4800.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-4800.json similarity index 100% rename from resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-4800.json rename to configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-4800.json diff --git a/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-5500.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-5500.json similarity index 100% rename from resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-5500.json rename to configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-5500.json diff --git a/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-6000.json b/configs/memspec/JEDEC_1Gbx16_8B_LPDDR5-6000.json similarity index 100% rename from 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diff --git a/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json b/configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G.json similarity index 100% rename from resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json rename to configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G.json diff --git a/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json b/configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G_2s.json similarity index 100% rename from resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json rename to configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G_2s.json diff --git a/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json b/configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G_3s.json similarity index 100% rename from resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json rename to configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G_3s.json diff --git a/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json b/configs/memspec/MICRON_1Gb_DDR3-1066_8bit_G_mu.json similarity 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100% rename from resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json rename to configs/memspec/MICRON_2Gb_LPDDR-333_16bit_A.json diff --git a/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json b/configs/memspec/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json similarity index 100% rename from resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json rename to configs/memspec/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json diff --git a/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json b/configs/memspec/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json similarity index 100% rename from resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json rename to configs/memspec/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json diff --git a/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json b/configs/memspec/MICRON_4Gb_DDR4-1866_8bit_A.json similarity index 100% rename from resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json rename to configs/memspec/MICRON_4Gb_DDR4-1866_8bit_A.json diff --git a/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json b/configs/memspec/MICRON_4Gb_DDR4-2400_8bit_A.json similarity index 100% rename from resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json rename to configs/memspec/MICRON_4Gb_DDR4-2400_8bit_A.json diff --git a/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json b/configs/memspec/MICRON_4Gb_LPDDR3-1333_32bit_A.json similarity index 100% rename from resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json rename to configs/memspec/MICRON_4Gb_LPDDR3-1333_32bit_A.json diff --git a/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json b/configs/memspec/MICRON_4Gb_LPDDR3-1600_32bit_A.json similarity index 100% rename from resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json rename to configs/memspec/MICRON_4Gb_LPDDR3-1600_32bit_A.json diff --git a/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json b/configs/memspec/MICRON_6Gb_LPDDR4-3200_32bit_A.json similarity index 100% rename from resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json rename to configs/memspec/MICRON_6Gb_LPDDR4-3200_32bit_A.json diff --git a/resources/configs/memspecs/README.md b/configs/memspec/README.md similarity index 100% rename from resources/configs/memspecs/README.md rename to configs/memspec/README.md diff --git a/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json b/configs/memspec/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json similarity index 100% rename from resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json rename to configs/memspec/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json diff --git a/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json b/configs/memspec/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json similarity index 100% rename from resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json rename to configs/memspec/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json diff --git a/resources/configs/memspecs/STT-MRAM-1.2x.json b/configs/memspec/STT-MRAM-1.2x.json similarity index 100% rename from resources/configs/memspecs/STT-MRAM-1.2x.json rename to configs/memspec/STT-MRAM-1.2x.json diff --git a/resources/configs/memspecs/STT-MRAM-1.5x.json b/configs/memspec/STT-MRAM-1.5x.json similarity index 100% rename from resources/configs/memspecs/STT-MRAM-1.5x.json rename to configs/memspec/STT-MRAM-1.5x.json diff --git a/resources/configs/memspecs/STT-MRAM-2.0x.json b/configs/memspec/STT-MRAM-2.0x.json similarity index 100% rename from resources/configs/memspecs/STT-MRAM-2.0x.json rename to configs/memspec/STT-MRAM-2.0x.json diff --git a/resources/configs/memspecs/memspec_ranktest.json b/configs/memspec/memspec_ranktest.json similarity index 100% rename from resources/configs/memspecs/memspec_ranktest.json rename to configs/memspec/memspec_ranktest.json diff --git a/resources/simulations/ranktest.json b/configs/ranktest.json similarity index 90% rename from resources/simulations/ranktest.json rename to configs/ranktest.json index b4f4776d..fbd2c08c 100644 --- a/resources/simulations/ranktest.json +++ b/configs/ranktest.json @@ -5,7 +5,6 @@ "memspec": "memspec_ranktest.json", "simconfig": "example.json", "simulationid": "ranktest", - "thermalconfig": "config.json", "tracesetup": [ { "clkMhz": 200, diff --git a/resources/configs/simulator/example.json b/configs/simconfig/example.json similarity index 74% rename from resources/configs/simulator/example.json rename to configs/simconfig/example.json index b57e9d14..6b65d7d0 100644 --- a/resources/configs/simulator/example.json +++ b/configs/simconfig/example.json @@ -4,15 +4,11 @@ "CheckTLM2Protocol": false, "DatabaseRecording": true, "Debug": false, - "ECCControllerMode": "Disabled", "EnableWindowing": false, - "ErrorCSVFile": "", - "ErrorChipSeed": 42, "PowerAnalysis": false, "SimulationName": "example", "SimulationProgressBar": true, "StoreMode": "NoStorage", - "ThermalSimulation": false, "UseMalloc": false, "WindowSize": 1000 } diff --git a/resources/configs/simulator/gem5_se.json b/configs/simconfig/gem5_se.json similarity index 66% rename from resources/configs/simulator/gem5_se.json rename to configs/simconfig/gem5_se.json index c0b12f97..36f846ee 100644 --- a/resources/configs/simulator/gem5_se.json +++ b/configs/simconfig/gem5_se.json @@ -4,15 +4,11 @@ "CheckTLM2Protocol": false, "DatabaseRecording": true, "Debug": false, - "ECCControllerMode": "Disabled", "EnableWindowing": true, - "ErrorCSVFile": "", - "ErrorChipSeed": 42, "PowerAnalysis": true, - "SimulationName": "ddr3", + "SimulationName": "gem5_se", "SimulationProgressBar": true, "StoreMode": "Store", - "ThermalSimulation": false, "UseMalloc": false, "WindowSize": 1000 } diff --git a/resources/simulations/stt-mram-example.json b/configs/stt-mram-example.json similarity index 90% rename from resources/simulations/stt-mram-example.json rename to configs/stt-mram-example.json index 2edfd1a6..83403d0c 100644 --- a/resources/simulations/stt-mram-example.json +++ b/configs/stt-mram-example.json @@ -5,7 +5,6 @@ "memspec": "STT-MRAM-1.2x.json", "simconfig": "example.json", "simulationid": "stt-mram-example", - "thermalconfig": "config.json", "tracesetup": [ { "clkMhz": 800, diff --git a/resources/traces/example.stl b/configs/traces/example.stl similarity index 100% rename from resources/traces/example.stl rename to configs/traces/example.stl diff --git a/resources/traces/pct.stl b/configs/traces/pct.stl similarity index 100% rename from resources/traces/pct.stl rename to configs/traces/pct.stl diff --git a/resources/traces/ranktest.stl b/configs/traces/ranktest.stl similarity index 100% rename from resources/traces/ranktest.stl rename to configs/traces/ranktest.stl diff --git a/resources/simulations/wideio-thermal.json b/configs/wideio-thermal.json similarity index 90% rename from resources/simulations/wideio-thermal.json rename to configs/wideio-thermal.json index 1e9a1c0b..d0f488fa 100644 --- a/resources/simulations/wideio-thermal.json +++ b/configs/wideio-thermal.json @@ -5,7 +5,6 @@ "memspec": "JEDEC_256Mb_WIDEIO-200_128bit.json", "simconfig": "wideio_thermal.json", "simulationid": "wideio-example", - "thermalconfig": "config.json", "tracesetup": [ { "clkMhz": 1000, diff --git a/resources/.gitignore b/resources/.gitignore deleted file mode 100644 index 0d20b648..00000000 --- a/resources/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*.pyc diff --git a/resources/configs/simulator/ecc.json b/resources/configs/simulator/ecc.json deleted file mode 100644 index e148c3aa..00000000 --- a/resources/configs/simulator/ecc.json +++ /dev/null @@ -1,19 +0,0 @@ -{ - "simconfig": { - "AddressOffset": 0, - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Hamming", - "EnableWindowing": true, - "ErrorCSVFile": "", - "ErrorChipSeed": 42, - "PowerAnalysis": true, - "SimulationName": "ddr3", - "SimulationProgressBar": true, - "StoreMode": "ErrorModel", - "ThermalSimulation": false, - "UseMalloc": false, - "WindowSize": 1000 - } -} diff --git a/resources/configs/simulator/wideio.json b/resources/configs/simulator/wideio.json deleted file mode 100644 index 0c285f79..00000000 --- a/resources/configs/simulator/wideio.json +++ /dev/null @@ -1,18 +0,0 @@ -{ - "simconfig": { - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Disabled", - "EnableWindowing": true, - "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv", - "ErrorChipSeed": 42, - "PowerAnalysis": true, - "SimulationName": "wideio", - "SimulationProgressBar": true, - "StoreMode": "NoStorage", - "ThermalSimulation": false, - "UseMalloc": false, - "WindowSize": 1000 - } -} diff --git a/resources/configs/simulator/wideio_ecc.json b/resources/configs/simulator/wideio_ecc.json deleted file mode 100644 index 80acc3be..00000000 --- a/resources/configs/simulator/wideio_ecc.json +++ /dev/null @@ -1,18 +0,0 @@ -{ - "simconfig": { - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Hamming", - "EnableWindowing": true, - "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv", - "ErrorChipSeed": 42, - "PowerAnalysis": true, - "SimulationName": "wideio_ecc", - "SimulationProgressBar": true, - "StoreMode": "ErrorModel", - "ThermalSimulation": false, - "UseMalloc": false, - "WindowSize": 1000 - } -} diff --git a/resources/configs/simulator/wideio_thermal.json b/resources/configs/simulator/wideio_thermal.json deleted file mode 100644 index 6ce8c0a4..00000000 --- a/resources/configs/simulator/wideio_thermal.json +++ /dev/null @@ -1,18 +0,0 @@ -{ - "simconfig": { - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Disabled", - "EnableWindowing": true, - "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv", - "ErrorChipSeed": 42, - "PowerAnalysis": true, - "SimulationName": "wideio", - "SimulationProgressBar": true, - "StoreMode": "Store", - "ThermalSimulation": true, - "UseMalloc": false, - "WindowSize": 1000 - } -} diff --git a/resources/configs/thermalsim/config.json b/resources/configs/thermalsim/config.json deleted file mode 100644 index b88ed84c..00000000 --- a/resources/configs/thermalsim/config.json +++ /dev/null @@ -1,15 +0,0 @@ -{ - "thermalsimconfig": { - "TemperatureScale": "Celsius", - "StaticTemperatureDefaultValue": 89, - "ThermalSimPeriod":100, - "ThermalSimUnit":"us", - "PowerInfoFile": "powerInfo.json", - "IceServerIp": "127.0.0.1", - "IceServerPort": 11880, - "SimPeriodAdjustFactor" : 10, - "NPowStableCyclesToIncreasePeriod": 5, - "GenerateTemperatureMap": true, - "GeneratePowerMap": true - } -} diff --git a/resources/configs/thermalsim/core.flp b/resources/configs/thermalsim/core.flp deleted file mode 100644 index e85e6801..00000000 --- a/resources/configs/thermalsim/core.flp +++ /dev/null @@ -1,45 +0,0 @@ -CPUs : - - position 0, 0 ; - dimension 2750, 4300 ; - -GPU : - - position 3350, 0 ; - dimension 2750, 4000 ; - -BASEBAND1 : - - position 4250, 4000 ; - dimension 1850, 3300 ; - -BASEBAND2 : - - position 3350, 7300 ; - dimension 2750, 3300 ; - -LLCACHE : - - position 0, 4300 ; - dimension 1900, 3000 ; - -DRAMCTRL1 : - - position 1900, 4300 ; - dimension 850, 3000 ; - -DRAMCTRL2 : - - position 3350, 4000 ; - dimension 900, 3300 ; - -TSVS : - - position 2750, 2300 ; - dimension 600, 6000 ; - -ACELLERATORS : - - position 0, 7300 ; - dimension 2750, 3300 ; - diff --git a/resources/configs/thermalsim/mem.flp b/resources/configs/thermalsim/mem.flp deleted file mode 100644 index 29d02254..00000000 --- a/resources/configs/thermalsim/mem.flp +++ /dev/null @@ -1,16 +0,0 @@ -channel0 : - position 150, 100 ; - dimension 2600, 5200 ; - -channel1 : - position 3350, 100 ; - dimension 2600, 5200 ; - -channel2 : - position 150, 5300 ; - dimension 2600, 5200 ; - -channel3 : - position 3350, 5300 ; - dimension 2600, 5200 ; - diff --git a/resources/configs/thermalsim/powerInfo.json b/resources/configs/thermalsim/powerInfo.json deleted file mode 100644 index 524f690f..00000000 --- a/resources/configs/thermalsim/powerInfo.json +++ /dev/null @@ -1,20 +0,0 @@ -{ - "powerInfo": { - "dram_die_channel0": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel1": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel2": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel3": { - "init_pow": 0, - "threshold": 1.0 - } - } -} diff --git a/resources/configs/thermalsim/stack.stk b/resources/configs/thermalsim/stack.stk deleted file mode 100644 index ec74f020..00000000 --- a/resources/configs/thermalsim/stack.stk +++ /dev/null @@ -1,49 +0,0 @@ -material SILICON : - thermal conductivity 1.30e-4 ; - volumetric heat capacity 1.628e-12 ; - -material BEOL : - thermal conductivity 2.25e-6 ; - volumetric heat capacity 2.175e-12 ; - -material COPPER : - thermal conductivity 4.01e-04 ; - volumetric heat capacity 3.37e-12 ; - -top heat sink : - //sink height 1e03, area 100e06, material COPPER ; - //spreader height 0.5e03, area 70e06, material SILICON ; - heat transfer coefficient 1.3e-09 ; - temperature 318.15 ; -dimensions : - chip length 6100, width 10600 ; - cell length 100, width 100 ; - - -layer PCB : - height 10 ; - material BEOL ; - -die DRAM : - layer 58.5 SILICON ; - source 2 SILICON ; - layer 1.5 BEOL ; - layer 58.5 SILICON ; - - -stack: - die DRAM_DIE DRAM floorplan "./mem.flp" ; - layer CONN_TO_PCB PCB ; - -solver: - transient step 0.01, slot 0.05 ; - initial temperature 300.0 ; - -output: - Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); - Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); - Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); - Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); - Tmap (DRAM_DIE, "output1.txt", slot) ; - Pmap (DRAM_DIE, "output2.txt", slot) ; - diff --git a/resources/error/wideio.csv b/resources/error/wideio.csv deleted file mode 100644 index 22e0d502..00000000 --- a/resources/error/wideio.csv +++ /dev/null @@ -1,24 +0,0 @@ -75 64 0 0 0 0 -80 64 0 0 0 0 -85 64 0 0 0 0 -89 64 0 0 0 0 -75 127 0 0 0 0 -80 127 0 0 0 0 -85 127 0 0 0 0 -89 127 2 0.03 2 0.06 -75 145 0 0 0 0 -80 145 0 0 0 0 -85 145 0 0 1 0.03 -89 145 13 0.195 3 0.09 -75 164 0 0 0 0 -80 164 0 0 0 0 -85 164 8 0.12 2 0.06 -89 164 24 0.36 4 0.12 -75 182 0 0 0 0 -80 182 0 0 1 0.03 -85 182 16 0.24 2 0.06 -89 182 41 0.615 8 0.24 -75 200 0 0 0 0 -80 200 5 0.075 3 0.09 -85 200 24 0.36 4 0.12 -89 200 67 1.005 15 0.45 diff --git a/resources/scripts/address_scrambler.pl b/resources/scripts/address_scrambler.pl deleted file mode 100644 index 65396cb8..00000000 --- a/resources/scripts/address_scrambler.pl +++ /dev/null @@ -1,64 +0,0 @@ -#!/usr/bin/perl -use warnings; -use strict; - -my $filename = shift || die; - -open(FH, "$filename"); - -while() -{ - # Get all the data adress: - $_ =~ /(\d+):\s+(\w+)\s+0x([\w\d]+)/; - my $time = $1; - my $command = $2; - my $address = $3; - my $new_address; - - # Convert to binary: - $address = sprintf( "%032b", hex( $address ) ); - - # example: - # 31 0 - # 00000000000000000000000000000001 - # 00000000000000000000010000000000 - - # Swap adresses: - $new_address = substr($address,31 - 31,1). # R 31 - substr($address,31 - 30,1). # R 30 - substr($address,31 - 29,1). # R 29 - substr($address,31 - 28,1). # R 28 - substr($address,31 - 27,1). # R 27 - substr($address,31 - 26,1). # R 26 - substr($address,31 - 25,1). # R 25 - substr($address,31 - 24,1). # R 24 - substr($address,31 - 23,1). # R 23 - substr($address,31 - 22,1). # R 22 - substr($address,31 - 21,1). # R 21 - substr($address,31 - 20,1). # R 20 - substr($address,31 - 19,1). # R 19 - substr($address,31 - 18,1). # R 18 - substr($address,31 - 17,1). # R 17 - substr($address,31 - 16,1). # R 16 - substr($address,31 - 8,1). # R 15 - substr($address,31 - 7,1). # R 14 - substr($address,31 - 6,1). # R 13 - substr($address,31 - 11,1). # B 12 - substr($address,31 - 9,1). # B 11 - substr($address,31 - 0,1). # B 10 - substr($address,31 - 15,1). # C 9 - substr($address,31 - 14,1). # C 8 - substr($address,31 - 13,1). # C 7 - substr($address,31 - 12,1). # C 6 - substr($address,31 - 10,1). # C 5 - substr($address,31 - 5,1). # C 4 - substr($address,31 - 4,1). # C 3 - substr($address,31 - 3,1). # C 2 - substr($address,31 - 2,1). # C 1 - substr($address,31 - 1,1); # C 0 - - $new_address = sprintf("%X", oct( "0b$new_address" ) ); - - print $time.":\t".$command."\t0x".$new_address."\n"; -} - diff --git a/resources/scripts/analyse_trace.pl b/resources/scripts/analyse_trace.pl deleted file mode 100644 index 671179c2..00000000 --- a/resources/scripts/analyse_trace.pl +++ /dev/null @@ -1,378 +0,0 @@ -#!/usr/bin/perl -use List::Util 'max'; -use warnings; -use strict; - -my $filename = shift || die("Please provide a input STL file"); - -my $numberOfRows = 16384; -my $numberOfBanks = 8; -my $numberOfColumns = 1024; -my $numberOfBytes = 8; # Byte Offset from e.g. DIMM - -my $numberOfBits = 32; -my $burstLength = 8; - -my $addressCorrection = 1; - -my $numberOfRowBits = log($numberOfRows)/log(2); -my $numberOfBankBits = log($numberOfBanks)/log(2); -my $numberOfColumnBits = log($numberOfColumns)/log(2); -my $numberOfByteBits = log($numberOfBytes)/log(2); -my $numberOfBurstBits = log($burstLength)/log(2); - -print "Number of Address Bits:\t".$numberOfBits."\n\n"; -print "Number of Row Bits:\t".$numberOfRowBits."\n"; -print "Number of Bank Bits:\t".$numberOfBankBits."\n"; -print "Number of Col Bits:\t".$numberOfColumnBits."\n"; -print ">Burst Bits in Col:\t".$numberOfBurstBits."\n"; -print "Number of Byte Bits:\t".$numberOfByteBits."\n"; - -my $numberOfXBits = $numberOfBits - $numberOfRowBits - $numberOfBankBits - $numberOfColumnBits - $numberOfByteBits; - -print "Number of Unused Bits:\t".$numberOfXBits."\n"; -print "\n"; -print "\n"; - -open(FH, "$filename"); - -my @activityCounter; -my @mapping; - -# Initialize: -for(my $i = 0; $i < $numberOfBits; $i++) -{ - $activityCounter[$i] = 0; -} - -for(my $i = $numberOfXBits-1; $i >= 0; $i--) -{ - $mapping[$numberOfBits-($numberOfXBits-$i)] = "X".$i; -} - -my $old_address = "00000000000000000000000000000000"; - -while() -{ - # Get the adress: - $_ =~ /\d+:\s+\w+\s+0x([\w\d]+)\s*[\d\w]*/; - my $address = $1; - $address = sprintf( "%0".$numberOfBits."b", hex( $address ) * $addressCorrection ); - - # $i = 0 :: most significant bit - for(my $i = 0; $i < $numberOfBits; $i++) - { - my $new = substr($address, $i, 1); - my $old = substr($old_address, $i, 1); - - if($new ne $old) - { - $activityCounter[$numberOfBits-1-$i]++; - } - } - - $old_address = $address; -} - -close(FH); - -# Make Consistency Check: -for(my $i = 0; $i < ($numberOfByteBits+$numberOfBankBits); $i++) -{ - if($activityCounter[$i] != 0) - { - print "Bits of lower C part or Y have toggled, this should not happen\n"; - exit -1; - } -} - -# Print bit numbers: -print "Bits\t\t"; -for(my $i = $numberOfBits-1; $i >= 0; $i--) -{ - print $i."\t"; -} - -#Print Activity -print "\nActivity\t"; -for(my $i = $numberOfBits-1; $i >= 0; $i--) -{ - print $activityCounter[$i]."\t"; -} - -#Print relative Activity -print "\nPercent\t\t"; -my $sum = 0; -my @percent; -for(my $i = $numberOfBits-1; $i >= 0; $i--) -{ - $sum = $sum + $activityCounter[$i]; -} - -for(my $i = $numberOfBits-1; $i >= 0; $i--) -{ - my $string = $activityCounter[$i]/$sum*100; - $string = sprintf("%.2f", $string); - $string =~ s/\./,/g; - $percent[$i] = $string."%"; - $string .= "%\t"; - print $string; -} - -#Fix Byte Offset: -for(my $i = 0; $i < $numberOfByteBits; $i++) -{ - $activityCounter[$i] = -1; - $mapping[$i] = "Y$i"; -} - -#Fix Constant 0 Bits in Column due to Burstlength: -for(my $i=0; $i < $numberOfBurstBits; $i++) -{ - $activityCounter[$numberOfByteBits + $i] = -1; - $mapping[$numberOfByteBits + $i] = "C$i"; -} - -#Search Column Locations -for(my $i = $numberOfBurstBits; $i < $numberOfColumnBits; $i++) -{ - my $maximum = max(@activityCounter); - my ($index) = grep $activityCounter[$_] == $maximum , 0.. $#activityCounter; - $mapping[$index] = "C$i"; - $activityCounter[$index] = -1; -} - -#Search Bank Locations -for(my $i = 0; $i < $numberOfBankBits; $i++) -{ - my $maximum = max(@activityCounter); - my ($index) = grep $activityCounter[$_] == $maximum , 0.. $#activityCounter; - $mapping[$index] = "B$i"; - $activityCounter[$index] = -1; -} - -#Search Row Locations -for(my $i = 0; $i < $numberOfRowBits; $i++) -{ - my $maximum = max(@activityCounter); - my ($index) = grep $activityCounter[$_] == $maximum , 0.. $#activityCounter; - $mapping[$index] = "R$i"; - $activityCounter[$index] = -1; -} - -#Print final mapping -my $header = ' -strict graph G -{ - forcelabels=true; - rankdir=LR; - { - graph [fontname = "courier"]; - node [shape=square, fontname="courier", fixedsize=true, width=0.85, height=0.85] - edge [fontname = "courier"]; -'; - -for(my $i = $numberOfBits-1; $i >= 0; $i--) -{ - $header .= " $i [pos=\"".($numberOfBits-1-$i).",0!\", xlp=\"-5,0\", label=\"$i\n".$percent[$i]."\" ]\n"; -} - -my $pos = 0; -for(my $i = $numberOfXBits-1; $i >= 0; $i--) -{ - my $pos2 = $numberOfBits-$pos-1; - $header .= " X$i [ label=\"$pos2\nX$i\" pos=\"$pos,-5!\"]\n"; - $pos++; -} -for(my $i = $numberOfBankBits-1; $i >= 0; $i--) -{ - my $pos2 = $numberOfBits-$pos-1; - $header .= " B$i [ label=\"$pos2\nB$i\" pos=\"$pos,-5!\"]\n"; - $pos++; -} -for(my $i = $numberOfRowBits-1; $i >= 0; $i--) -{ - my $pos2 = $numberOfBits-$pos-1; - $header .= " R$i [ label=\"$pos2\nR$i\" pos=\"$pos,-5!\"]\n"; - $pos++; -} -for(my $i = $numberOfColumnBits-1; $i >= 0; $i--) -{ - my $pos2 = $numberOfBits-$pos-1; - $header .= " C$i [ label=\"$pos2\nC$i\" pos=\"$pos,-5!\"]\n"; - $pos++; -} -for(my $i = $numberOfByteBits-1; $i >= 0; $i--) -{ - my $pos2 = $numberOfBits-$pos-1; - $header .= " Y$i [ label=\"$pos2\nY$i\" pos=\"$pos,-5!\"]\n"; - $pos++; -} -$header .= " }\n"; - -print "\nMapping\t\t"; -my $maximum = max(@activityCounter); -for(my $i = $numberOfBits-1; $i >= 0; $i--) -{ - if($mapping[$i] =~ /X\d/) - { - $header .= "$i -- ".$mapping[$i]." [ color=\"grey\"];\n"; - } - elsif($mapping[$i] =~ /B\d/) - { - $header .= "$i -- ".$mapping[$i]." [ color=\"green\"];\n"; - } - elsif($mapping[$i] =~ /R\d/) - { - $header .= "$i -- ".$mapping[$i]." [ color=\"blue\"];\n"; - } - elsif($mapping[$i] =~ /C\d/) - { - $header .= "$i -- ".$mapping[$i]." [ color=\"red\"];\n"; - } - elsif($mapping[$i] =~ /Y\d/) - { - $header .= "$i -- ".$mapping[$i]." [ color=\"grey\"];\n"; - } - print $mapping[$i]."\t"; -} -$header .= "}"; -print "\n"; - -#Generate Scrambled Trace: - -#Generate Configuration for 32x32 MUX: -# Assumption e.g. 32 bit: -# B R C -# X X B B B R R R R R R R R R R R R R R C C C C C C C C C C Y Y Y -# 31 30 29 27 26 13 12 3 2 0 -# A B C D E F -# -#print "A:".($numberOfBits-1)."\n"; -#print "B:".($numberOfBits-$numberOfXBits-1)."\n"; -#print "C:".($numberOfBits-$numberOfXBits-$numberOfBankBits-1)."\n"; -#print "D:".($numberOfBits-$numberOfXBits-$numberOfBankBits-$numberOfRowBits-1)."\n"; -#print "E:".($numberOfBits-$numberOfXBits-$numberOfBankBits-$numberOfRowBits-$numberOfColumnBits-1)."\n"; -#print "F:".($numberOfBits-$numberOfXBits-$numberOfBankBits-$numberOfRowBits-$numberOfColumnBits-$numberOfByteBits)."\n"; - -my @confVectorDecimal; -my @checkVector; -my $XCounter = 0; -my $rowCounter = 0; -my $bankCounter = 0; -my $columnCounter = 0; -my $byteCounter = 0; - -for(my $i = $numberOfBits-1; $i >= 0; $i--) -{ - if($mapping[$i] =~ /X(\d+)/) - { - my $idx = $numberOfBits-$numberOfXBits+$1; - #print "\$1=".$1." i=".$i." idx=".$idx." mapping=".$mapping[$i]."\n"; - $confVectorDecimal[$idx] = $i; - $checkVector[$idx] = "X"; - } - elsif($mapping[$i] =~ /B(\d+)/) - { - my $idx = $numberOfBits-$numberOfXBits-$numberOfBankBits+$1; - #print "\$1=".$1." i=".$i." idx=".$idx." mapping=".$mapping[$i]."\n"; - $confVectorDecimal[$idx] = $i; - $checkVector[$idx] = "B"; - } - elsif($mapping[$i] =~ /R(\d+)/) - { - my $idx = $numberOfBits-$numberOfXBits-$numberOfBankBits-$numberOfRowBits+$1; - #print "\$1=".$1." i=".$i." idx=".$idx." mapping=".$mapping[$i]."\n"; - $confVectorDecimal[$idx] = $i; - $checkVector[$idx] = "R"; - } - elsif($mapping[$i] =~ /C(\d+)/) - { - my $idx = $numberOfBits-$numberOfXBits-$numberOfBankBits-$numberOfRowBits-$numberOfColumnBits+$1; - #print "\$1=".$1." i=".$i." idx=".$idx." mapping=".$mapping[$i]."\n"; - $confVectorDecimal[$idx] = $i; - $checkVector[$idx] = "C"; - } - elsif($mapping[$i] =~ /Y(\d+)/) - { - my $idx = $numberOfBits-$numberOfXBits-$numberOfBankBits-$numberOfRowBits-$numberOfColumnBits-$numberOfByteBits+$1; - #print "\$1=".$1." i=".$i." idx=".$idx." mapping=".$mapping[$i]."\n"; - $confVectorDecimal[$idx] = $i; - $checkVector[$idx] = "Y"; - } -} - -print "\n"; -print "\n"; -print "Configuration Vector for the mapping "; -for(my $m = $numberOfBits-1; $m >= 0; $m--) -{ - print $checkVector[$m]; -} -print ":\n\n"; - -for(my $m = $numberOfBits-1; $m >= 0; $m--) -{ - #Debug: - print "mux: $m\t-->\t".$confVectorDecimal[$m]."\n"; -} - -print "\n"; -print "\n"; - -for(my $m = $numberOfBits-1; $m >= 0; $m--) -{ - print sprintf( "%05b", $confVectorDecimal[$m] ); -} -print "\n"; -print "\n"; - -# Generate Graph -my $dotname; -my $pdfname; -my $stlname; - -if($filename =~ /(.+)\.stl/) -{ - $dotname = $1.".dot"; - $pdfname = $1.".pdf"; - $stlname = $1."_scram.stl"; - - open(FH,">$dotname"); - print FH $header; - close(FH); - system("neato -o $pdfname -Tpdf $dotname"); -} - - -open(FH, "$filename"); -open(SH, ">$stlname"); - -while() -{ - # Get all the data adress: - $_ =~ /(\d+):\s+(\w+)\s+0x([\w\d]+)/; # XXX - my $time = $1; - my $command = $2; - my $address = $3; - my $new_address; - - # Convert to binary: - $address = sprintf( "%032b", hex( $address ) ); - - # Swap adresses: - $new_address = ""; - for(my $m = $numberOfBits-1; $m >= 0; $m--) - { - #print $confVectorDecimal[$m]."\n"; - $new_address .= substr($address,$numberOfBits-1-$confVectorDecimal[$m],1); - } - - # Convert to Hex: - $new_address = sprintf("%X", oct( "0b$new_address" ) ); - - print SH $time.":\t".$command."\t0x".$new_address."\n"; -} - -close(FH); -close(SH); diff --git a/resources/scripts/generateTrace.py b/resources/scripts/generateTrace.py deleted file mode 100644 index ba22f861..00000000 --- a/resources/scripts/generateTrace.py +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/python -# This script generates an example trace for DDR3 -# -# -# -# -# 26 downto 13 --> 2^14 = 16384 -# Burstlength = 8 --> 8 down bits always zero --> 12 downto 3 --> 7 --> 2^7 = 128 -# 2^3 = 8 -# - -numberOfRows = 16384 -numberOfColumns = 128 -byteOffset = 64 -bankOffset = numberOfRows * numberOfColumns - -# Write to Bank 0 -for x in range(0, bankOffset): - print "{0:d}:\tread\t0x{1:X}".format(x,(x*byteOffset)) - -# Write to Bank 1 -for x in range(bankOffset, 2*bankOffset): - print "{0:d}:\tread\t0x{1:X}".format(x,(x*byteOffset)) diff --git a/resources/scripts/memoryHog.pl b/resources/scripts/memoryHog.pl deleted file mode 100644 index 0d2cf321..00000000 --- a/resources/scripts/memoryHog.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/perl -w -use warnings; -use strict; - -open(LINEAR, "> ../traces/linear.stl"); -open(RANDOM, "> ../traces/random.stl"); - -my $length = shift || die ("please give length of traces"); -my $size = 0x40; - -for(my $i=0; $i < $length; $i++) -{ - my $r = int(rand($length)); - #print $r." ".($size*$r)."\n"; - - print LINEAR "$i: read ".sprintf("0x%x",($size*$i))."\n"; - print RANDOM "$i: read ".sprintf("0x%x",($size*$r))."\n"; - - #my $rw = int(rand(2))%2; - #if($rw == 0) - #{ - # print LINEAR "$i: read ".sprintf("0x%x",($size*$i))."\n"; - # print RANDOM "$i: read ".sprintf("0x%x",($size*$r))."\n"; - #} - #else - #{ - # print LINEAR "$i: write ".sprintf("0x%x",($size*$i))."\n"; - # print RANDOM "$i: write ".sprintf("0x%x",($size*$r))."\n"; - #} -} - - -close(LINEAR); -close(RANDOM); diff --git a/resources/scripts/stride_detection.pl b/resources/scripts/stride_detection.pl deleted file mode 100644 index c15b2c28..00000000 --- a/resources/scripts/stride_detection.pl +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/perl -use List::Util 'max'; -use warnings; -use strict; - -my $filename = shift || die("Please provide a input STL file"); -my $command = shift || die ("Pleas provide read/write"); - -open(FH, "$filename"); - -my $old_address = 0; -my %histogram; -my $command_occurance = 0; - -while() -{ - # Get the adress: - $_ =~ /\d+:\s+(\w+)\s+0x([\w\d]+)\s*[\d\w]*/; - if($command eq $1) - { - my $address = hex($2); - my $distance = $address - $old_address; - $histogram{$distance} ++; - $old_address = $address; - $command_occurance++; - } -} - -foreach my $key ( keys %histogram) -{ - my $percent = $histogram{$key}/$command_occurance; - my $hexkey = sprintf( "%032b", abs($key) ); - print "0x".$hexkey." ".abs($key)." = ".$histogram{$key}." (".$percent.")\n"; -} diff --git a/resources/scripts/traceGenerationForNNTraining.pl b/resources/scripts/traceGenerationForNNTraining.pl deleted file mode 100644 index 58a534bc..00000000 --- a/resources/scripts/traceGenerationForNNTraining.pl +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/perl -use warnings; -use strict; - -my $phaseLength = 100; -my $phaseStatus = 0; -my $max = 100000; -my $base = 0; -my $maxAddressExp = 26; -my $maxAddress = 2**$maxAddressExp; - -for(my $i = 0; $i < $max; $i++) -{ - if($phaseStatus == 0) # Linear - { - my $addr = (($base << 6) + (($i % $phaseLength) << 6)) % $maxAddress; - print "$i: read 0x".sprintf("%x", $addr)."\n"; - } - else # Random - { - my $addr = (rand(2**($maxAddressExp-6))) << 6; - print "$i: read 0x".sprintf("%x", $addr)."\n"; - } - - if($i % 100 == 0 && $i != 0) - { - $phaseStatus = ($phaseStatus == 0) ? 1 : 0; - $base = rand(2**($maxAddressExp-6)); - } -} - diff --git a/resources/scripts/trace_gen.py b/resources/scripts/trace_gen.py deleted file mode 100644 index a2b42f42..00000000 --- a/resources/scripts/trace_gen.py +++ /dev/null @@ -1,137 +0,0 @@ -#! /usr/bin/env python3 -# vim: set fileencoding=utf-8 - -# Copyright (c) 2018, Technische Universität Kaiserslautern -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Author: Éder F. Zulian - -import ctypes - -# A trace file is a pre-recorded file containing memory transactions. Each -# memory transaction has a timestamp that tells the simulator when it shall -# happen, a transaction type (read or write) and a memory address given in -# hexadecimal. -# -# Here is an example syntax: -# -# ``` -# # Comment lines begin with # -# # [clock-cyle]: [write|read] [hex-address] -# 31: read 0x400140 -# 33: read 0x400160 -# 56: write 0x7fff8000 -# 81: read 0x400180 -# ``` -# -# The timestamp corresponds to the time the request is to be issued and it is -# given in cycles of the bus master device. Example: the device is a FPGA with -# frequency 200 MHz (clock period of 5 ns). If the timestamp is 10 it means -# that the request is to be issued when time is 50 ns. -# - -# The default values given as example assume the following address mapping: -# -# DIMM Characteristics: -# Byte Offset (Y): 8 [0:2] (8-byte-wide memory module, i.e., 64-bit-wide data bus) -> 3 bit -# Cols (C): 1K [3:12] (A0 - A9) -> 10 bit -# Rows (R): 128K [13:29] (A0 - A16) -> 17 bit -# Bank (B): 8 [30:32] (BA0 - BA2) -> 3 bit -# -# 3 3 3 | 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1 -# 2 1 0 | 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0 -# B B B | R R R R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y -# - -# Transaction type (read or write) -transaction = 'read' - -# Channel information. If your address mapping does not have channel bits keep -# it equal to 1 and set the shift to the extreme left of the address. -num_ch = 1 # Number of channels -ch_shift = 34 # Shift to reach the frist bit reserved for channels in the address -ch_mask = 0x1 # Mask for all channel bits in the address - -# Bank group information. If your address mapping does not have bank groups -# keep it equal to 1 and set the shift to the extreme left of the address. -num_bank_groups = 1 # Number of bank groups -bgroup_shift = 33 # Shift to reach the frist bit reserved for bank groups in the address -bgroup_mask = 0x1 # Mask for all bits in the address related to bank groups - -# Bank information -num_banks = 8 # Number of banks -bank_shift = 30 # Shift to reach the frist bit reserved for banks in the address -bank_mask = 0x7 # Mask for all bank bits in the address - -# Row information -num_rows = 128 * 1024 # Number of rows -row_shift = 13 # Shift to reach the frist bit reserved for rows in the address -row_mask = 0x1ffff # Mask for all row bits in the address - -# Column information -num_col = 1 * 1024 # Number of columns -col_shift = 3 # Shift to reach the frist bit reserved for columns in the address -col_mask = 0x3ff # Mask for all column bits in the address - -# Burst length of 8 columns. 8 columns written/read per access (in 4 full -# clock cycles of the memory bus). -burst_len = 8 - -# Initial clock cycle -clock_cycle = 0 - -# Clock cycle increment between two accesses -clock_increment = 10 - - -def clear_bits(mask, shift, val): - m = ctypes.c_uint64(~(mask << shift)).value - return ctypes.c_uint64(val & m).value - - -def set_bits(mask, shift, val, v): - val = clear_bits(mask, shift, val) - return ctypes.c_uint64(val | (v << shift)).value - - -address = 0 -for ch in range(0, num_ch): - address = set_bits(ch_mask, ch_shift, address, ch) - for bg in range(0, num_bank_groups): - address = set_bits(bgroup_mask, bgroup_shift, address, bg) - for b in range(0, num_banks): - address = set_bits(bank_mask, bank_shift, address, b) - for row in range(0, num_rows): - address = set_bits(row_mask, row_shift, address, row) - for col in range(0, num_col, burst_len): - address = set_bits(col_mask, col_shift, address, col) - print('# clock cycle: {0:d} | {1} | address: 0x{2:010X} | channel: {3} | bank group: {4} | bank: {5} | row: {6} | column: {7}'.format(clock_cycle, transaction, address, ch, bg, b, row, col)) - print('{0:d}:\t{1}\t0x{2:010X}'.format(clock_cycle, transaction, address)) - clock_cycle = clock_cycle + clock_increment diff --git a/resources/scripts/video_rendering/Makefile b/resources/scripts/video_rendering/Makefile deleted file mode 100644 index 51190ca8..00000000 --- a/resources/scripts/video_rendering/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -all: - modulecmd bash load gnuplot/latest - modulecmd bash load image-magick/latest - ./temperatur.pl -movie: - ffmpeg -start_number 00000000 -i ../out/%08d.jpg -vcodec mpeg4 ../out.avi - -clean: - rm *.out *.err diff --git a/resources/scripts/video_rendering/temperatur.job.pl b/resources/scripts/video_rendering/temperatur.job.pl deleted file mode 100644 index 5c05db4c..00000000 --- a/resources/scripts/video_rendering/temperatur.job.pl +++ /dev/null @@ -1,135 +0,0 @@ -#!/usr/bin/perl -w -use warnings; -use strict; -use File::Copy; - -my $file = shift; -my $id = shift; -my $samples = shift; -my $inputPath = "/gu2/jungma/thermal/in/out-backup"; -my $extractPath = "/gu2/jungma/thermal/tmp/$id"; - -print "Create TMP path... "; -system("mkdir $extractPath"); -print " done\n"; - -print "Extract... "; -system("tar -xf $inputPath/$file -C $extractPath"); -print " done\n"; - -print "Preprocessing... "; -system("sed '1d' $extractPath/out/output_core_die_full.txt > $extractPath/die0.txt"); -system("sed '1d' $extractPath/out/output_mem_die_1_full.txt > $extractPath/die1.txt"); -system("sed '1d' $extractPath/out/output_mem_die_2_full.txt > $extractPath/die2.txt"); -system("sed '1d' $extractPath/out/output_mem_die_3_full.txt > $extractPath/die3.txt"); -system("sed '1d' $extractPath/out/output_mem_die_4_full.txt > $extractPath/die4.txt"); -print " done\n"; - -print "Gnuplot..."; -open( my $GP, '|-', 'gnuplot' ); -print $GP " - reset - set terminal pngcairo size 500,500 enhanced font 'Verdana,10' - - set border linewidth 0 - unset key - unset colorbox - unset tics - set lmargin screen 0.0 - set rmargin screen 1.0 - set tmargin screen 1.0 - set bmargin screen 0.0 - - set pm3d map - set pm3d interpolate 2,2 - set cbrange [318.0:388.0] - - #set palette rgbformulae 22,13,-31 - set palette defined ( 0 \"blue\", 3 \"green\", 4 \"yellow\", 5 \"red\", 6 \"black\" ) - - set output '$extractPath/die0.png' - splot '$extractPath/die0.txt' matrix every ::1 - - set output '$extractPath/die1.png' - splot '$extractPath/die1.txt' matrix every ::1 - - set output '$extractPath/die2.png' - splot '$extractPath/die2.txt' matrix every ::1 - - set output '$extractPath/die3.png' - splot '$extractPath/die3.txt' matrix every ::1 - - set output '$extractPath/die4.png' - splot '$extractPath/die4.txt' matrix every ::1"; -close($GP); -print " done\n"; - -print "Wait for files... "; -while (1) { last if -e "$extractPath/die0.png"; print "."; sleep 1;} -while (1) { last if -e "$extractPath/die1.png"; print "."; sleep 1;} -while (1) { last if -e "$extractPath/die2.png"; print "."; sleep 1;} -while (1) { last if -e "$extractPath/die3.png"; print "."; sleep 1;} -while (1) { last if -e "$extractPath/die4.png"; print "."; sleep 1;} -print " done\n"; - -print "Composite ..."; -system("composite -gravity center constants/thermal_model_core.png $extractPath/die0.png $extractPath/die0b.png"); -system("composite -gravity center constants/thermal_model_dram_0_1.png $extractPath/die1.png $extractPath/die1b.png"); -system("composite -gravity center constants/thermal_model_dram_2_3.png $extractPath/die2.png $extractPath/die2b.png"); -system("composite -gravity center constants/thermal_model_dram_4_5.png $extractPath/die3.png $extractPath/die3b.png"); -system("composite -gravity center constants/thermal_model_dram_6_7.png $extractPath/die4.png $extractPath/die4b.png"); -print " done\n"; - -print "Wait for files... "; -while (1) { last if -e "$extractPath/die0b.png"; print "."; sleep 1;} -while (1) { last if -e "$extractPath/die1b.png"; print "."; sleep 1;} -while (1) { last if -e "$extractPath/die2b.png"; print "."; sleep 1;} -while (1) { last if -e "$extractPath/die3b.png"; print "."; sleep 1;} -while (1) { last if -e "$extractPath/die4b.png"; print "."; sleep 1;} -print " done\n"; - -print "Convert ..."; -system("convert $extractPath/die0b.png -alpha set -background none -shear 0x-40 -rotate 60 +repage -crop 1048x485+0+205 $extractPath/die0c.png"); -system("convert $extractPath/die1b.png -alpha set -background none -shear 0x-40 -rotate 60 +repage -crop 1048x485+0+205 $extractPath/die1c.png"); -system("convert $extractPath/die2b.png -alpha set -background none -shear 0x-40 -rotate 60 +repage -crop 1048x485+0+205 $extractPath/die2c.png"); -system("convert $extractPath/die3b.png -alpha set -background none -shear 0x-40 -rotate 60 +repage -crop 1048x485+0+205 $extractPath/die3c.png"); -system("convert $extractPath/die4b.png -alpha set -background none -shear 0x-40 -rotate 60 +repage -crop 1048x485+0+205 $extractPath/die4c.png"); -print " done\n"; - -print "Wait for files... "; -while (1) { last if -e "$extractPath/die0c.png"; print "."; sleep 1;} -while (1) { last if -e "$extractPath/die1c.png"; print "."; sleep 1;} -while (1) { last if -e "$extractPath/die2c.png"; print "."; sleep 1;} -while (1) { last if -e "$extractPath/die3c.png"; print "."; sleep 1;} -while (1) { last if -e "$extractPath/die4c.png"; print "."; sleep 1;} -print " done\n"; - -my $outFileName = sprintf("%08d", $id); - -print "Produce Output ..."; -system("convert -size 1048x1680 xc:black $extractPath/die0c.png -geometry +0+1200 -composite $extractPath/die1c.png -geometry +0+900 -composite $extractPath/die2c.png -geometry +0+600 -composite $extractPath/die3c.png -geometry +0+300 -composite $extractPath/die4c.png -composite $extractPath/a$outFileName.jpg"); - -while (1) { last if -e "$extractPath/a$outFileName.jpg"; print "."; sleep 1;} -system("convert $extractPath/a$outFileName.jpg -pointsize 80 -fill white -gravity northeast -draw \"text 20,20 '".$samples."ms'\" $extractPath/b$outFileName.jpg"); - -while (1) { last if -e "$extractPath/b$outFileName.jpg"; print "."; sleep 1;} -system("convert $extractPath/b$outFileName.jpg constants/legend/legend4.png +append ../out/$outFileName.jpg"); - -print " done\n"; - -print "Produce Samples ..."; -for(my $i = 0; $i < $samples-1; $i++) -{ - $id++; - my $outFileNameCopy = sprintf("%08d", $id); - copy("../out/$outFileName.jpg","../out/$outFileNameCopy.jpg"); -} -print " done\n"; - -# cleanup -print "Cleanup ... "; -while (1) { last if -e "/gu2/jungma/thermal/out/$outFileName.jpg"; print "."; sleep 1;} -system("rm -rf $extractPath"); -print " done\n"; - -##ffmpeg -start_number 00000000 -i %08d.jpg -vcodec mpeg4 test.avi diff --git a/resources/scripts/video_rendering/temperatur.pl b/resources/scripts/video_rendering/temperatur.pl deleted file mode 100644 index 11279c14..00000000 --- a/resources/scripts/video_rendering/temperatur.pl +++ /dev/null @@ -1,67 +0,0 @@ -#!/usr/bin/perl -w -use warnings; -use strict; -use List::Util qw( min max ); - -#/Volumes/Etana_tmp2/tmp_sadri/backup/sep_16/log_smartbench_traces_50_cpu_1650_mhz_100_mhz_dram_100_mhz_sampling8X_bankwise_on_test/out-backup -my $inputPath = "../in/out-backup"; -my $extractPath = "../tmp"; -my $samplingFile = "../in/sampling"; - -# Read the input file names and store it in an array -opendir (DIR, $inputPath) or die $!; - -my @files; -my @sortetFiles; - -while (my $file = readdir(DIR)) -{ - push(@files, $file); -} - -@sortetFiles = sort @files; - - -print "Cleanup\n"; -system("rm -rf *.err *.out"); -system("rm -rf ../tmp/*"); -print "Load modules\n"; - - -# Estimate sampeling numbers - -open(SF,$samplingFile); - -my @refreshRates; - -while() -{ - $_ =~ /(\d+)\.0/; - my $rate = $1; - push(@refreshRates, $rate); -} - -print "Max. Rate:".max(@refreshRates)."\n"; -print "Min. Rate:".min(@refreshRates)."\n"; - -my $counter = 0; -my $i = 0; -# For each data package start one job! -foreach(@sortetFiles) -{ - my $file = $_; - - if($file =~ /(\d+)-(\d+)-(\d+)-(\d+)-(\d+)-(\d+)-(\d+)\.tgz/) - { - my $samples = $refreshRates[$i]; - system("bsub -W 00:05 ./temperatur.job.pl $file $counter $samples"); - $counter+=$samples; - $i++; - #if($i == 100) - #{ - # last; - #} - } -} - -##ffmpeg -start_number 00000000 -i %08d.jpg -vcodec mpeg4 test.avi diff --git a/resources/traces/generateErrorTest.pl b/resources/traces/generateErrorTest.pl deleted file mode 100644 index 39589e25..00000000 --- a/resources/traces/generateErrorTest.pl +++ /dev/null @@ -1,141 +0,0 @@ -#!/usr/bin/perl -w - -# Copyright (c) 2015, Technische Universität Kaiserslautern -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: -# Matthias Jung -# Eder F. Zulian -# Lukas Steiner - -use warnings; -use strict; - -# Assuming this address mapping: -# { -# "CONGEN": { -# "BYTE_BIT": [ -# 0, -# 1, -# 2, -# 3 -# ], -# "BANK_BIT": [ -# 4, -# 5 -# ], -# "COLUMN_BIT": [ -# 6, -# 7, -# 8, -# 9, -# 10, -# 11, -# 12 -# ], -# "ROW_BIT": [ -# 13, -# 14, -# 15, -# 16, -# 17, -# 18, -# 19, -# 20, -# 21, -# 22, -# 23, -# 24 -# ], -# "CHANNEL_BIT": [ -# 25, -# 26 -# ] -# } -# } - -# This is how it should look like later: -# 31: write 0x0 0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff - -my $numberOfChannels = 4; -my $numberOfRows = 4096; -my $numberOfColumns = 128; -my $bytesPerColumn = 16; -my $burstLength = 4; # burst length of 4 columns --> 4 columns written or read per access -my $dataLength = $bytesPerColumn * $burstLength; - -my $channelOffset = 0x2000000; -my $rowOffset = 0x2000; -my $columnOffset = 0x40; - -# Generate Data Pattern: -my $dataPatternByte = "ff"; - -my $dataPattern = "0x"; -for(my $i = 0; $i < $dataLength; $i++) -{ - $dataPattern .= $dataPatternByte; -} - -my $clkCounter = 0; -my $addr = 0; - -# Generate Trace file (writes): -for(my $cha = 0; $cha < ($numberOfChannels * $channelOffset); $cha = $cha + $channelOffset) -{ - for(my $row = 0; $row < ($numberOfRows * $rowOffset); $row = $row + $rowOffset) - { - for(my $col = 0; $col < ($numberOfColumns * $columnOffset); $col = $col + ($columnOffset * $burstLength)) - { - my $addrHex = sprintf("0x%x", $addr); - print "$clkCounter:\twrite\t$addrHex\t$dataPattern\n"; - $clkCounter++; - $addr += $columnOffset * $burstLength; - } - } -} - -$clkCounter = 50000000; -$addr = 0; - -# Generate Trace file (reads): -for(my $cha = 0; $cha < ($numberOfChannels * $channelOffset); $cha = $cha + $channelOffset) -{ - for(my $row = 0; $row < ($numberOfRows * $rowOffset); $row = $row + $rowOffset) - { - for(my $col = 0; $col < ($numberOfColumns * $columnOffset); $col = $col + ($columnOffset * $burstLength)) - { - my $addrHex = sprintf("0x%x", $addr); - print "$clkCounter:\tread\t$addrHex\n"; - $clkCounter++; - $addr += $columnOffset * $burstLength; - } - } -} \ No newline at end of file diff --git a/src/configuration/DRAMSys/config/AddressMapping.h b/src/configuration/DRAMSys/config/AddressMapping.h index bcc9f4df..4426ff8d 100644 --- a/src/configuration/DRAMSys/config/AddressMapping.h +++ b/src/configuration/DRAMSys/config/AddressMapping.h @@ -42,7 +42,7 @@ namespace DRAMSys::Config { -const std::string addressMappingPath = "configs/amconfigs"; +const std::string addressMappingPath = "addressmapping"; struct XorPair { diff --git a/src/configuration/DRAMSys/config/McConfig.h b/src/configuration/DRAMSys/config/McConfig.h index 5197812b..16769e4b 100644 --- a/src/configuration/DRAMSys/config/McConfig.h +++ b/src/configuration/DRAMSys/config/McConfig.h @@ -44,7 +44,7 @@ namespace DRAMSys::Config { -const std::string mcConfigPath = "configs/mcconfigs"; +const std::string mcConfigPath = "mcconfig"; enum class PagePolicy { diff --git a/src/configuration/DRAMSys/config/SimConfig.h b/src/configuration/DRAMSys/config/SimConfig.h index 67309695..5dee2443 100644 --- a/src/configuration/DRAMSys/config/SimConfig.h +++ b/src/configuration/DRAMSys/config/SimConfig.h @@ -42,7 +42,7 @@ namespace DRAMSys::Config { -const std::string simConfigPath = "configs/simulator"; +const std::string simConfigPath = "simconfig"; enum class StoreMode { diff --git a/src/configuration/DRAMSys/config/memspec/MemSpec.h b/src/configuration/DRAMSys/config/memspec/MemSpec.h index 79708d63..d20f0c03 100644 --- a/src/configuration/DRAMSys/config/memspec/MemSpec.h +++ b/src/configuration/DRAMSys/config/memspec/MemSpec.h @@ -45,7 +45,7 @@ namespace DRAMSys::Config { -const std::string memSpecPath = "configs/memspecs"; +const std::string memSpecPath = "memspec"; struct MemSpec { diff --git a/src/libdramsys/README.md b/src/libdramsys/README.md new file mode 100644 index 00000000..9dd07852 --- /dev/null +++ b/src/libdramsys/README.md @@ -0,0 +1,14 @@ +## Architecture and Functionality + +A UML diagram of the software architecture is presented below; different component implementations are left out for simplicity. More information about the architecture and functionality can be found in the papers [1] [2] [3] and in the introduction video on [Youtube](https://www.youtube.com/watch?v=8EkC3mYWpQY). + +UML + +[1] TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration +M. Jung, C. Weis, N. Wehn, K. Chandrasekar. International Conference on High-Performance and Embedded Architectures and Compilers 2013 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2013, Berlin. + +[2] DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework +M. Jung, C. Weis, N. Wehn. IPSJ Transactions on System LSI Design Methodology (T-SLDM), October, 2015. + +[3] DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator +L. Steiner, M. Jung, F. S. Prado, K. Bykov, N. Wehn. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), July, 2020, Samos Island, Greece. \ No newline at end of file diff --git a/src/simulator/simulator/main.cpp b/src/simulator/simulator/main.cpp index 769fb23c..3f04a683 100644 --- a/src/simulator/simulator/main.cpp +++ b/src/simulator/simulator/main.cpp @@ -74,15 +74,15 @@ int sc_main(int argc, char **argv) { // Get path of resources: resources = pathOfFile(argv[0]) - + std::string("/../../resources/"); - simulationJson = resources + "simulations/ddr4-example.json"; + + std::string("/../../configs/"); + simulationJson = resources + "ddr4-example.json"; } // Run with specific config but default resource folders: else if (argc == 2) { // Get path of resources: resources = pathOfFile(argv[0]) - + std::string("/../../resources/"); + + std::string("/../../configs/"); simulationJson = argv[1]; } // Run with specific config and specific resource folder: diff --git a/tests/tests_regression/DDR3/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json b/tests/tests_regression/DDR3/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json deleted file mode 100644 index c82926c9..00000000 --- a/tests/tests_regression/DDR3/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json +++ /dev/null @@ -1,51 +0,0 @@ -{ - "CONGEN": { - "XOR":[ - { - "FIRST":13, - "SECOND":16 - } - ], - "BANK_BIT": [ - 13, - 14, - 15 - ], - "BYTE_BIT": [ - 0, - 1, - 2 - ], - "COLUMN_BIT": [ - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12 - ], - "ROW_BIT": [ - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27, - 28, - 29 - ], - "RANK_BIT": [ - 30 - ] - } -} diff --git a/tests/tests_regression/DDR3/configs/mcconfigs/fr_fcfs_grp.json b/tests/tests_regression/DDR3/configs/mcconfigs/fr_fcfs_grp.json deleted file mode 100644 index ec7ba66c..00000000 --- a/tests/tests_regression/DDR3/configs/mcconfigs/fr_fcfs_grp.json +++ /dev/null @@ -1,14 +0,0 @@ -{ - "mcconfig": { - "PagePolicy": "Open", - "Scheduler": "FrFcfsGrp", - "RequestBufferSize": 8, - "CmdMux": "Oldest", - "RespQueue": "Fifo", - "RefreshPolicy": "Rankwise", - "RefreshMaxPostponed": 0, - "RefreshMaxPulledin": 0, - "PowerDownPolicy": "Staggered", - "PowerDownTimeout": 100 - } -} \ No newline at end of file diff --git a/tests/tests_regression/DDR3/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json b/tests/tests_regression/DDR3/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json deleted file mode 100644 index e9dc9a59..00000000 --- a/tests/tests_regression/DDR3/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json +++ /dev/null @@ -1,61 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 2, - "nbrOfChannels": 1, - "nbrOfRows": 16384, - "width": 64, - "nbrOfDevices": 1 - }, - "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 720.0, - "idd2n": 400.0, - "idd2p0": 80.0, - "idd2p1": 200.0, - "idd3n": 440.0, - "idd3p0": 240.0, - "idd3p1": 240.0, - "idd4r": 1200.0, - "idd4w": 1200.0, - "idd5": 1760.0, - "idd6": 48.0, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 7, - "DQSCK": 0, - "FAW": 20, - "RAS": 20, - "RC": 27, - "RCD": 7, - "REFI": 4160, - "RFC": 59, - "RL": 7, - "RP": 7, - "RRD": 4, - "RTP": 4, - "WL": 6, - "WR": 8, - "WTR": 4, - "XP": 4, - "XPDLL": 13, - "XS": 64, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 533 - } - } -} diff --git a/tests/tests_regression/DDR3/configs/simulator/ddr3.json b/tests/tests_regression/DDR3/configs/simulator/ddr3.json deleted file mode 100644 index 1ade5aea..00000000 --- a/tests/tests_regression/DDR3/configs/simulator/ddr3.json +++ /dev/null @@ -1,19 +0,0 @@ -{ - "simconfig": { - "AddressOffset": 0, - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Disabled", - "EnableWindowing": false, - "ErrorCSVFile": "", - "ErrorChipSeed": 42, - "PowerAnalysis": true, - "SimulationName": "ddr3", - "SimulationProgressBar": true, - "StoreMode": "NoStorage", - "ThermalSimulation": false, - "UseMalloc": false, - "WindowSize": 1000 - } -} diff --git a/tests/tests_regression/DDR3/configs/thermalsim/config.json b/tests/tests_regression/DDR3/configs/thermalsim/config.json deleted file mode 100644 index b88ed84c..00000000 --- a/tests/tests_regression/DDR3/configs/thermalsim/config.json +++ /dev/null @@ -1,15 +0,0 @@ -{ - "thermalsimconfig": { - "TemperatureScale": "Celsius", - "StaticTemperatureDefaultValue": 89, - "ThermalSimPeriod":100, - "ThermalSimUnit":"us", - "PowerInfoFile": "powerInfo.json", - "IceServerIp": "127.0.0.1", - "IceServerPort": 11880, - "SimPeriodAdjustFactor" : 10, - "NPowStableCyclesToIncreasePeriod": 5, - "GenerateTemperatureMap": true, - "GeneratePowerMap": true - } -} diff --git a/tests/tests_regression/DDR3/configs/thermalsim/core.flp b/tests/tests_regression/DDR3/configs/thermalsim/core.flp deleted file mode 100644 index e85e6801..00000000 --- a/tests/tests_regression/DDR3/configs/thermalsim/core.flp +++ /dev/null @@ -1,45 +0,0 @@ -CPUs : - - position 0, 0 ; - dimension 2750, 4300 ; - -GPU : - - position 3350, 0 ; - dimension 2750, 4000 ; - -BASEBAND1 : - - position 4250, 4000 ; - dimension 1850, 3300 ; - -BASEBAND2 : - - position 3350, 7300 ; - dimension 2750, 3300 ; - -LLCACHE : - - position 0, 4300 ; - dimension 1900, 3000 ; - -DRAMCTRL1 : - - position 1900, 4300 ; - dimension 850, 3000 ; - -DRAMCTRL2 : - - position 3350, 4000 ; - dimension 900, 3300 ; - -TSVS : - - position 2750, 2300 ; - dimension 600, 6000 ; - -ACELLERATORS : - - position 0, 7300 ; - dimension 2750, 3300 ; - diff --git a/tests/tests_regression/DDR3/configs/thermalsim/mem.flp b/tests/tests_regression/DDR3/configs/thermalsim/mem.flp deleted file mode 100644 index 29d02254..00000000 --- a/tests/tests_regression/DDR3/configs/thermalsim/mem.flp +++ /dev/null @@ -1,16 +0,0 @@ -channel0 : - position 150, 100 ; - dimension 2600, 5200 ; - -channel1 : - position 3350, 100 ; - dimension 2600, 5200 ; - -channel2 : - position 150, 5300 ; - dimension 2600, 5200 ; - -channel3 : - position 3350, 5300 ; - dimension 2600, 5200 ; - diff --git a/tests/tests_regression/DDR3/configs/thermalsim/powerInfo.json b/tests/tests_regression/DDR3/configs/thermalsim/powerInfo.json deleted file mode 100644 index 524f690f..00000000 --- a/tests/tests_regression/DDR3/configs/thermalsim/powerInfo.json +++ /dev/null @@ -1,20 +0,0 @@ -{ - "powerInfo": { - "dram_die_channel0": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel1": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel2": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel3": { - "init_pow": 0, - "threshold": 1.0 - } - } -} diff --git a/tests/tests_regression/DDR3/configs/thermalsim/stack.stk b/tests/tests_regression/DDR3/configs/thermalsim/stack.stk deleted file mode 100644 index ec74f020..00000000 --- a/tests/tests_regression/DDR3/configs/thermalsim/stack.stk +++ /dev/null @@ -1,49 +0,0 @@ -material SILICON : - thermal conductivity 1.30e-4 ; - volumetric heat capacity 1.628e-12 ; - -material BEOL : - thermal conductivity 2.25e-6 ; - volumetric heat capacity 2.175e-12 ; - -material COPPER : - thermal conductivity 4.01e-04 ; - volumetric heat capacity 3.37e-12 ; - -top heat sink : - //sink height 1e03, area 100e06, material COPPER ; - //spreader height 0.5e03, area 70e06, material SILICON ; - heat transfer coefficient 1.3e-09 ; - temperature 318.15 ; -dimensions : - chip length 6100, width 10600 ; - cell length 100, width 100 ; - - -layer PCB : - height 10 ; - material BEOL ; - -die DRAM : - layer 58.5 SILICON ; - source 2 SILICON ; - layer 1.5 BEOL ; - layer 58.5 SILICON ; - - -stack: - die DRAM_DIE DRAM floorplan "./mem.flp" ; - layer CONN_TO_PCB PCB ; - -solver: - transient step 0.01, slot 0.05 ; - initial temperature 300.0 ; - -output: - Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); - Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); - Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); - Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); - Tmap (DRAM_DIE, "output1.txt", slot) ; - Pmap (DRAM_DIE, "output2.txt", slot) ; - diff --git a/tests/tests_regression/DDR3/ddr3-example.json b/tests/tests_regression/DDR3/ddr3-example.json new file mode 100644 index 00000000..2f4f6f56 --- /dev/null +++ b/tests/tests_regression/DDR3/ddr3-example.json @@ -0,0 +1,148 @@ +{ + "simulation": { + "addressmapping": { + "XOR": [ + { + "FIRST": 13, + "SECOND": 16 + } + ], + "BANK_BIT": [ + 13, + 14, + 15 + ], + "BYTE_BIT": [ + 0, + 1, + 2 + ], + "COLUMN_BIT": [ + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12 + ], + "ROW_BIT": [ + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29 + ], + "RANK_BIT": [ + 30 + ] + }, + "mcconfig": { + "PagePolicy": "Open", + "Scheduler": "FrFcfsGrp", + "RequestBufferSize": 8, + "CmdMux": "Oldest", + "RespQueue": "Fifo", + "RefreshPolicy": "Rankwise", + "RefreshMaxPostponed": 0, + "RefreshMaxPulledin": 0, + "PowerDownPolicy": "Staggered", + "PowerDownTimeout": 100 + }, + "memspec": { + "memarchitecturespec": { + "burstLength": 8, + "dataRate": 2, + "nbrOfBanks": 8, + "nbrOfColumns": 1024, + "nbrOfRanks": 2, + "nbrOfChannels": 1, + "nbrOfRows": 16384, + "width": 64, + "nbrOfDevices": 1 + }, + "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", + "memoryType": "DDR3", + "mempowerspec": { + "idd0": 720.0, + "idd2n": 400.0, + "idd2p0": 80.0, + "idd2p1": 200.0, + "idd3n": 440.0, + "idd3p0": 240.0, + "idd3p1": 240.0, + "idd4r": 1200.0, + "idd4w": 1200.0, + "idd5": 1760.0, + "idd6": 48.0, + "vdd": 1.5 + }, + "memtimingspec": { + "AL": 0, + "CCD": 4, + "CKE": 3, + "CKESR": 4, + "CL": 7, + "DQSCK": 0, + "FAW": 20, + "RAS": 20, + "RC": 27, + "RCD": 7, + "REFI": 4160, + "RFC": 59, + "RL": 7, + "RP": 7, + "RRD": 4, + "RTP": 4, + "WL": 6, + "WR": 8, + "WTR": 4, + "XP": 4, + "XPDLL": 13, + "XS": 64, + "XSDLL": 512, + "ACTPDEN": 1, + "PRPDEN": 1, + "REFPDEN": 1, + "RTRS": 1, + "clkMhz": 533 + } + }, + "simconfig": { + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "ECCControllerMode": "Disabled", + "EnableWindowing": false, + "ErrorCSVFile": "", + "ErrorChipSeed": 42, + "PowerAnalysis": true, + "SimulationName": "ddr3", + "SimulationProgressBar": true, + "StoreMode": "NoStorage", + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 + }, + "simulationid": "ddr3-dual-rank", + "tracesetup": [ + { + "clkMhz": 533, + "name": "trace_test2.stl" + } + ] + } +} diff --git a/tests/tests_regression/DDR3/simulations/ddr3-example.json b/tests/tests_regression/DDR3/simulations/ddr3-example.json deleted file mode 100644 index b924da62..00000000 --- a/tests/tests_regression/DDR3/simulations/ddr3-example.json +++ /dev/null @@ -1,16 +0,0 @@ -{ - "simulation": { - "addressmapping": "am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json", - "mcconfig": "fr_fcfs_grp.json", - "memspec": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json", - "simconfig": "ddr3.json", - "simulationid": "ddr3-dual-rank", - "thermalconfig": "config.json", - "tracesetup": [ - { - "clkMhz": 533, - "name": "trace_test2.stl" - } - ] - } -} diff --git a/tests/tests_regression/DDR4/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json b/tests/tests_regression/DDR4/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json deleted file mode 100644 index be30b98f..00000000 --- a/tests/tests_regression/DDR4/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json +++ /dev/null @@ -1,46 +0,0 @@ -{ - "CONGEN": { - "BANKGROUP_BIT":[ - 30, - 31 - ], - "BANK_BIT": [ - 28, - 29 - ], - "BYTE_BIT": [ - 0, - 1, - 2 - ], - "COLUMN_BIT": [ - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12 - ], - "ROW_BIT": [ - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27 - ] - } -} diff --git a/tests/tests_regression/DDR4/configs/mcconfigs/fr_fcfs.json b/tests/tests_regression/DDR4/configs/mcconfigs/fr_fcfs.json deleted file mode 100644 index 787d87e2..00000000 --- a/tests/tests_regression/DDR4/configs/mcconfigs/fr_fcfs.json +++ /dev/null @@ -1,11 +0,0 @@ -{"mcconfig": { - "PagePolicy": "ClosedAdaptive", - "Scheduler": "FrFcfs", - "RequestBufferSize": 8, - "CmdMux": "Oldest", - "RespQueue": "Fifo", - "RefreshPolicy": "Rankwise", - "RefreshMaxPostponed": 8, - "RefreshMaxPulledin": 8, - "PowerDownPolicy": "NoPowerDown", - "PowerDownTimeout": 100}} diff --git a/tests/tests_regression/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json b/tests/tests_regression/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json deleted file mode 100644 index 95234154..00000000 --- a/tests/tests_regression/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json +++ /dev/null @@ -1,71 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBankGroups": 4, - "nbrOfBanks": 16, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfChannels": 1, - "nbrOfRows": 32768, - "width": 8, - "nbrOfDevices": 8 - }, - "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", - "memoryType": "DDR4", - "mempowerspec": { - "idd0": 56.25, - "idd02": 4.05, - "idd2n": 33.75, - "idd2p0": 17.0, - "idd2p1": 17.0, - "idd3n": 39.5, - "idd3p0": 22.5, - "idd3p1": 22.5, - "idd4r": 157.5, - "idd4w": 135.0, - "idd5": 118.0, - "idd6": 20.25, - "idd62": 2.6, - "vdd": 1.2, - "vdd2": 2.5 - }, - "memtimingspec": { - "AL": 0, - "CCD_L": 5, - "CCD_S": 4, - "CKE": 6, - "CKESR": 7, - "CL": 13, - "DQSCK": 2, - "FAW": 22, - "RAS": 32, - "RC": 45, - "RCD": 13, - "REFM": 1, - "REFI": 3644, - "RFC": 243, - "RL": 13, - "RPRE": 1, - "RP": 13, - "RRD_L": 5, - "RRD_S": 4, - "RTP": 8, - "WL": 12, - "WPRE": 1, - "WR": 14, - "WTR_L": 7, - "WTR_S": 3, - "XP": 8, - "XPDLL": 255, - "XS": 252, - "XSDLL": 512, - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1, - "clkMhz": 933 - } - } -} diff --git a/tests/tests_regression/DDR4/configs/simulator/ddr4.json b/tests/tests_regression/DDR4/configs/simulator/ddr4.json deleted file mode 100644 index c88964d3..00000000 --- a/tests/tests_regression/DDR4/configs/simulator/ddr4.json +++ /dev/null @@ -1,19 +0,0 @@ -{ - "simconfig": { - "AddressOffset": 0, - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Disabled", - "EnableWindowing": false, - "ErrorCSVFile": "", - "ErrorChipSeed": 42, - "PowerAnalysis": true, - "SimulationName": "ddr4", - "SimulationProgressBar": true, - "StoreMode": "NoStorage", - "ThermalSimulation": false, - "UseMalloc": false, - "WindowSize": 1000 - } -} diff --git a/tests/tests_regression/DDR4/configs/thermalsim/config.json b/tests/tests_regression/DDR4/configs/thermalsim/config.json deleted file mode 100644 index b88ed84c..00000000 --- a/tests/tests_regression/DDR4/configs/thermalsim/config.json +++ /dev/null @@ -1,15 +0,0 @@ -{ - "thermalsimconfig": { - "TemperatureScale": "Celsius", - "StaticTemperatureDefaultValue": 89, - "ThermalSimPeriod":100, - "ThermalSimUnit":"us", - "PowerInfoFile": "powerInfo.json", - "IceServerIp": "127.0.0.1", - "IceServerPort": 11880, - "SimPeriodAdjustFactor" : 10, - "NPowStableCyclesToIncreasePeriod": 5, - "GenerateTemperatureMap": true, - "GeneratePowerMap": true - } -} diff --git a/tests/tests_regression/DDR4/configs/thermalsim/core.flp b/tests/tests_regression/DDR4/configs/thermalsim/core.flp deleted file mode 100644 index e85e6801..00000000 --- a/tests/tests_regression/DDR4/configs/thermalsim/core.flp +++ /dev/null @@ -1,45 +0,0 @@ -CPUs : - - position 0, 0 ; - dimension 2750, 4300 ; - -GPU : - - position 3350, 0 ; - dimension 2750, 4000 ; - -BASEBAND1 : - - position 4250, 4000 ; - dimension 1850, 3300 ; - -BASEBAND2 : - - position 3350, 7300 ; - dimension 2750, 3300 ; - -LLCACHE : - - position 0, 4300 ; - dimension 1900, 3000 ; - -DRAMCTRL1 : - - position 1900, 4300 ; - dimension 850, 3000 ; - -DRAMCTRL2 : - - position 3350, 4000 ; - dimension 900, 3300 ; - -TSVS : - - position 2750, 2300 ; - dimension 600, 6000 ; - -ACELLERATORS : - - position 0, 7300 ; - dimension 2750, 3300 ; - diff --git a/tests/tests_regression/DDR4/configs/thermalsim/mem.flp b/tests/tests_regression/DDR4/configs/thermalsim/mem.flp deleted file mode 100644 index 29d02254..00000000 --- a/tests/tests_regression/DDR4/configs/thermalsim/mem.flp +++ /dev/null @@ -1,16 +0,0 @@ -channel0 : - position 150, 100 ; - dimension 2600, 5200 ; - -channel1 : - position 3350, 100 ; - dimension 2600, 5200 ; - -channel2 : - position 150, 5300 ; - dimension 2600, 5200 ; - -channel3 : - position 3350, 5300 ; - dimension 2600, 5200 ; - diff --git a/tests/tests_regression/DDR4/configs/thermalsim/powerInfo.json b/tests/tests_regression/DDR4/configs/thermalsim/powerInfo.json deleted file mode 100644 index 524f690f..00000000 --- a/tests/tests_regression/DDR4/configs/thermalsim/powerInfo.json +++ /dev/null @@ -1,20 +0,0 @@ -{ - "powerInfo": { - "dram_die_channel0": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel1": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel2": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel3": { - "init_pow": 0, - "threshold": 1.0 - } - } -} diff --git a/tests/tests_regression/DDR4/configs/thermalsim/stack.stk b/tests/tests_regression/DDR4/configs/thermalsim/stack.stk deleted file mode 100644 index ec74f020..00000000 --- a/tests/tests_regression/DDR4/configs/thermalsim/stack.stk +++ /dev/null @@ -1,49 +0,0 @@ -material SILICON : - thermal conductivity 1.30e-4 ; - volumetric heat capacity 1.628e-12 ; - -material BEOL : - thermal conductivity 2.25e-6 ; - volumetric heat capacity 2.175e-12 ; - -material COPPER : - thermal conductivity 4.01e-04 ; - volumetric heat capacity 3.37e-12 ; - -top heat sink : - //sink height 1e03, area 100e06, material COPPER ; - //spreader height 0.5e03, area 70e06, material SILICON ; - heat transfer coefficient 1.3e-09 ; - temperature 318.15 ; -dimensions : - chip length 6100, width 10600 ; - cell length 100, width 100 ; - - -layer PCB : - height 10 ; - material BEOL ; - -die DRAM : - layer 58.5 SILICON ; - source 2 SILICON ; - layer 1.5 BEOL ; - layer 58.5 SILICON ; - - -stack: - die DRAM_DIE DRAM floorplan "./mem.flp" ; - layer CONN_TO_PCB PCB ; - -solver: - transient step 0.01, slot 0.05 ; - initial temperature 300.0 ; - -output: - Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); - Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); - Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); - Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); - Tmap (DRAM_DIE, "output1.txt", slot) ; - Pmap (DRAM_DIE, "output2.txt", slot) ; - diff --git a/tests/tests_regression/DDR4/ddr4-example.json b/tests/tests_regression/DDR4/ddr4-example.json new file mode 100644 index 00000000..93e7a55e --- /dev/null +++ b/tests/tests_regression/DDR4/ddr4-example.json @@ -0,0 +1,153 @@ +{ + "simulation": { + "addressmapping": { + "BANKGROUP_BIT": [ + 30, + 31 + ], + "BANK_BIT": [ + 28, + 29 + ], + "BYTE_BIT": [ + 0, + 1, + 2 + ], + "COLUMN_BIT": [ + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12 + ], + "ROW_BIT": [ + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27 + ] + }, + "mcconfig": { + "PagePolicy": "ClosedAdaptive", + "Scheduler": "FrFcfs", + "RequestBufferSize": 8, + "CmdMux": "Oldest", + "RespQueue": "Fifo", + "RefreshPolicy": "Rankwise", + "RefreshMaxPostponed": 8, + "RefreshMaxPulledin": 8, + "PowerDownPolicy": "NoPowerDown", + "PowerDownTimeout": 100 + }, + "memspec": { + "memarchitecturespec": { + "burstLength": 8, + "dataRate": 2, + "nbrOfBankGroups": 4, + "nbrOfBanks": 16, + "nbrOfColumns": 1024, + "nbrOfRanks": 1, + "nbrOfChannels": 1, + "nbrOfRows": 32768, + "width": 8, + "nbrOfDevices": 8 + }, + "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", + "memoryType": "DDR4", + "mempowerspec": { + "idd0": 56.25, + "idd02": 4.05, + "idd2n": 33.75, + "idd2p0": 17.0, + "idd2p1": 17.0, + "idd3n": 39.5, + "idd3p0": 22.5, + "idd3p1": 22.5, + "idd4r": 157.5, + "idd4w": 135.0, + "idd5": 118.0, + "idd6": 20.25, + "idd62": 2.6, + "vdd": 1.2, + "vdd2": 2.5 + }, + "memtimingspec": { + "AL": 0, + "CCD_L": 5, + "CCD_S": 4, + "CKE": 6, + "CKESR": 7, + "CL": 13, + "DQSCK": 2, + "FAW": 22, + "RAS": 32, + "RC": 45, + "RCD": 13, + "REFM": 1, + "REFI": 3644, + "RFC": 243, + "RL": 13, + "RPRE": 1, + "RP": 13, + "RRD_L": 5, + "RRD_S": 4, + "RTP": 8, + "WL": 12, + "WPRE": 1, + "WR": 14, + "WTR_L": 7, + "WTR_S": 3, + "XP": 8, + "XPDLL": 255, + "XS": 252, + "XSDLL": 512, + "ACTPDEN": 1, + "PRPDEN": 1, + "REFPDEN": 1, + "RTRS": 1, + "clkMhz": 933 + } + }, + "simconfig": { + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "ECCControllerMode": "Disabled", + "EnableWindowing": false, + "ErrorCSVFile": "", + "ErrorChipSeed": 42, + "PowerAnalysis": true, + "SimulationName": "ddr4", + "SimulationProgressBar": true, + "StoreMode": "NoStorage", + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 + }, + "simulationid": "ddr4-bankgrp", + "tracesetup": [ + { + "clkMhz": 933, + "name": "trace_test3.stl" + } + ] + } +} diff --git a/tests/tests_regression/DDR4/simulations/ddr4-example.json b/tests/tests_regression/DDR4/simulations/ddr4-example.json deleted file mode 100644 index d97481d9..00000000 --- a/tests/tests_regression/DDR4/simulations/ddr4-example.json +++ /dev/null @@ -1,16 +0,0 @@ -{ - "simulation": { - "addressmapping": "am_ddr4_8x4Gbx8_dimm_p1KB_brc.json", - "mcconfig": "fr_fcfs.json", - "memspec": "MICRON_4Gb_DDR4-1866_8bit_A.json", - "simconfig": "ddr4.json", - "simulationid": "ddr4-bankgrp", - "thermalconfig": "config.json", - "tracesetup": [ - { - "clkMhz": 933, - "name": "trace_test3.stl" - } - ] - } -} diff --git a/tests/tests_regression/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json b/tests/tests_regression/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json deleted file mode 100644 index c9362ea4..00000000 --- a/tests/tests_regression/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json +++ /dev/null @@ -1,47 +0,0 @@ -{ - "CONGEN": { - "CHANNEL_BIT":[ - 30 - ], - "BANKGROUP_BIT":[ - 28, - 29 - ], - "BANK_BIT": [ - 26, - 27 - ], - "BYTE_BIT": [ - 0, - 1, - 2, - 3 - ], - "COLUMN_BIT": [ - 4, - 5, - 6, - 7, - 8, - 9, - 10 - ], - "ROW_BIT": [ - 11, - 12, - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25 - ] - } -} diff --git a/tests/tests_regression/HBM2/configs/mcconfigs/fifoStrict.json b/tests/tests_regression/HBM2/configs/mcconfigs/fifoStrict.json deleted file mode 100644 index a1b1bc77..00000000 --- a/tests/tests_regression/HBM2/configs/mcconfigs/fifoStrict.json +++ /dev/null @@ -1,14 +0,0 @@ -{ - "mcconfig": { - "PagePolicy": "Closed", - "Scheduler": "Fifo", - "RequestBufferSize": 8, - "CmdMux": "Strict", - "RespQueue": "Fifo", - "RefreshPolicy": "NoRefresh", - "RefreshMaxPostponed": 0, - "RefreshMaxPulledin": 0, - "PowerDownPolicy": "NoPowerDown", - "PowerDownTimeout": 100 - } -} \ No newline at end of file diff --git a/tests/tests_regression/HBM2/configs/memspecs/HBM2.json b/tests/tests_regression/HBM2/configs/memspecs/HBM2.json deleted file mode 100644 index de681372..00000000 --- a/tests/tests_regression/HBM2/configs/memspecs/HBM2.json +++ /dev/null @@ -1,48 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 4, - "dataRate": 2, - "nbrOfBankGroups": 4, - "nbrOfBanks": 16, - "nbrOfColumns": 128, - "nbrOfPseudoChannels": 1, - "nbrOfChannels": 2, - "nbrOfDevices": 1, - "nbrOfRows": 32768, - "width": 128 - }, - "memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder", - "memoryType": "HBM2", - "memtimingspec": { - "CCDL": 3, - "CCDS": 2, - "CKE": 8, - "DQSCK": 1, - "FAW": 16, - "PL": 0, - "RAS": 28, - "RC": 42, - "RCDRD": 12, - "RCDWR": 6, - "REFI": 3900, - "REFISB": 244, - "RFC": 220, - "RFCSB": 96, - "RL": 17, - "RP": 14, - "RRDL": 6, - "RRDS": 4, - "RREFD": 8, - "RTP": 5, - "RTW": 18, - "WL": 7, - "WR": 14, - "WTRL": 9, - "WTRS": 4, - "XP": 8, - "XS": 216, - "clkMhz": 1000 - } - } -} diff --git a/tests/tests_regression/HBM2/configs/simulator/hbm2.json b/tests/tests_regression/HBM2/configs/simulator/hbm2.json deleted file mode 100644 index 608aec41..00000000 --- a/tests/tests_regression/HBM2/configs/simulator/hbm2.json +++ /dev/null @@ -1,19 +0,0 @@ -{ - "simconfig": { - "AddressOffset": 0, - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Disabled", - "EnableWindowing": false, - "ErrorCSVFile": "", - "ErrorChipSeed": 42, - "PowerAnalysis": false, - "SimulationName": "hbm2", - "SimulationProgressBar": true, - "StoreMode": "NoStorage", - "ThermalSimulation": false, - "UseMalloc": false, - "WindowSize": 1000 - } -} diff --git a/tests/tests_regression/HBM2/configs/thermalsim/config.json b/tests/tests_regression/HBM2/configs/thermalsim/config.json deleted file mode 100644 index b88ed84c..00000000 --- a/tests/tests_regression/HBM2/configs/thermalsim/config.json +++ /dev/null @@ -1,15 +0,0 @@ -{ - "thermalsimconfig": { - "TemperatureScale": "Celsius", - "StaticTemperatureDefaultValue": 89, - "ThermalSimPeriod":100, - "ThermalSimUnit":"us", - "PowerInfoFile": "powerInfo.json", - "IceServerIp": "127.0.0.1", - "IceServerPort": 11880, - "SimPeriodAdjustFactor" : 10, - "NPowStableCyclesToIncreasePeriod": 5, - "GenerateTemperatureMap": true, - "GeneratePowerMap": true - } -} diff --git a/tests/tests_regression/HBM2/configs/thermalsim/core.flp b/tests/tests_regression/HBM2/configs/thermalsim/core.flp deleted file mode 100644 index e85e6801..00000000 --- a/tests/tests_regression/HBM2/configs/thermalsim/core.flp +++ /dev/null @@ -1,45 +0,0 @@ -CPUs : - - position 0, 0 ; - dimension 2750, 4300 ; - -GPU : - - position 3350, 0 ; - dimension 2750, 4000 ; - -BASEBAND1 : - - position 4250, 4000 ; - dimension 1850, 3300 ; - -BASEBAND2 : - - position 3350, 7300 ; - dimension 2750, 3300 ; - -LLCACHE : - - position 0, 4300 ; - dimension 1900, 3000 ; - -DRAMCTRL1 : - - position 1900, 4300 ; - dimension 850, 3000 ; - -DRAMCTRL2 : - - position 3350, 4000 ; - dimension 900, 3300 ; - -TSVS : - - position 2750, 2300 ; - dimension 600, 6000 ; - -ACELLERATORS : - - position 0, 7300 ; - dimension 2750, 3300 ; - diff --git a/tests/tests_regression/HBM2/configs/thermalsim/mem.flp b/tests/tests_regression/HBM2/configs/thermalsim/mem.flp deleted file mode 100644 index 29d02254..00000000 --- a/tests/tests_regression/HBM2/configs/thermalsim/mem.flp +++ /dev/null @@ -1,16 +0,0 @@ -channel0 : - position 150, 100 ; - dimension 2600, 5200 ; - -channel1 : - position 3350, 100 ; - dimension 2600, 5200 ; - -channel2 : - position 150, 5300 ; - dimension 2600, 5200 ; - -channel3 : - position 3350, 5300 ; - dimension 2600, 5200 ; - diff --git a/tests/tests_regression/HBM2/configs/thermalsim/powerInfo.json b/tests/tests_regression/HBM2/configs/thermalsim/powerInfo.json deleted file mode 100644 index 524f690f..00000000 --- a/tests/tests_regression/HBM2/configs/thermalsim/powerInfo.json +++ /dev/null @@ -1,20 +0,0 @@ -{ - "powerInfo": { - "dram_die_channel0": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel1": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel2": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel3": { - "init_pow": 0, - "threshold": 1.0 - } - } -} diff --git a/tests/tests_regression/HBM2/configs/thermalsim/stack.stk b/tests/tests_regression/HBM2/configs/thermalsim/stack.stk deleted file mode 100644 index ec74f020..00000000 --- a/tests/tests_regression/HBM2/configs/thermalsim/stack.stk +++ /dev/null @@ -1,49 +0,0 @@ -material SILICON : - thermal conductivity 1.30e-4 ; - volumetric heat capacity 1.628e-12 ; - -material BEOL : - thermal conductivity 2.25e-6 ; - volumetric heat capacity 2.175e-12 ; - -material COPPER : - thermal conductivity 4.01e-04 ; - volumetric heat capacity 3.37e-12 ; - -top heat sink : - //sink height 1e03, area 100e06, material COPPER ; - //spreader height 0.5e03, area 70e06, material SILICON ; - heat transfer coefficient 1.3e-09 ; - temperature 318.15 ; -dimensions : - chip length 6100, width 10600 ; - cell length 100, width 100 ; - - -layer PCB : - height 10 ; - material BEOL ; - -die DRAM : - layer 58.5 SILICON ; - source 2 SILICON ; - layer 1.5 BEOL ; - layer 58.5 SILICON ; - - -stack: - die DRAM_DIE DRAM floorplan "./mem.flp" ; - layer CONN_TO_PCB PCB ; - -solver: - transient step 0.01, slot 0.05 ; - initial temperature 300.0 ; - -output: - Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); - Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); - Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); - Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); - Tmap (DRAM_DIE, "output1.txt", slot) ; - Pmap (DRAM_DIE, "output2.txt", slot) ; - diff --git a/tests/tests_regression/HBM2/hbm2-example.json b/tests/tests_regression/HBM2/hbm2-example.json new file mode 100644 index 00000000..b17b6b48 --- /dev/null +++ b/tests/tests_regression/HBM2/hbm2-example.json @@ -0,0 +1,135 @@ +{ + "simulation": { + "addressmapping": { + "CHANNEL_BIT": [ + 30 + ], + "BANKGROUP_BIT": [ + 28, + 29 + ], + "BANK_BIT": [ + 26, + 27 + ], + "BYTE_BIT": [ + 0, + 1, + 2, + 3 + ], + "COLUMN_BIT": [ + 4, + 5, + 6, + 7, + 8, + 9, + 10 + ], + "ROW_BIT": [ + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25 + ] + }, + "mcconfig": { + "PagePolicy": "Closed", + "Scheduler": "Fifo", + "RequestBufferSize": 8, + "CmdMux": "Strict", + "RespQueue": "Fifo", + "RefreshPolicy": "NoRefresh", + "RefreshMaxPostponed": 0, + "RefreshMaxPulledin": 0, + "PowerDownPolicy": "NoPowerDown", + "PowerDownTimeout": 100 + }, + "memspec": { + "memarchitecturespec": { + "burstLength": 4, + "dataRate": 2, + "nbrOfBankGroups": 4, + "nbrOfBanks": 16, + "nbrOfColumns": 128, + "nbrOfPseudoChannels": 1, + "nbrOfChannels": 2, + "nbrOfDevices": 1, + "nbrOfRows": 32768, + "width": 128 + }, + "memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder", + "memoryType": "HBM2", + "memtimingspec": { + "CCDL": 3, + "CCDS": 2, + "CKE": 8, + "DQSCK": 1, + "FAW": 16, + "PL": 0, + "RAS": 28, + "RC": 42, + "RCDRD": 12, + "RCDWR": 6, + "REFI": 3900, + "REFISB": 244, + "RFC": 220, + "RFCSB": 96, + "RL": 17, + "RP": 14, + "RRDL": 6, + "RRDS": 4, + "RREFD": 8, + "RTP": 5, + "RTW": 18, + "WL": 7, + "WR": 14, + "WTRL": 9, + "WTRS": 4, + "XP": 8, + "XS": 216, + "clkMhz": 1000 + } + }, + "simconfig": { + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "ECCControllerMode": "Disabled", + "EnableWindowing": false, + "ErrorCSVFile": "", + "ErrorChipSeed": 42, + "PowerAnalysis": false, + "SimulationName": "hbm2", + "SimulationProgressBar": true, + "StoreMode": "NoStorage", + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 + }, + "simulationid": "hbm2-example", + "tracesetup": [ + { + "clkMhz": 1000, + "name": "trace1_test4.stl" + }, + { + "clkMhz": 1000, + "name": "trace2_test4.stl" + } + ] + } +} diff --git a/tests/tests_regression/HBM2/simulations/hbm2-example.json b/tests/tests_regression/HBM2/simulations/hbm2-example.json deleted file mode 100644 index 6fd5f064..00000000 --- a/tests/tests_regression/HBM2/simulations/hbm2-example.json +++ /dev/null @@ -1,20 +0,0 @@ -{ - "simulation": { - "addressmapping": "am_hbm2_8Gb_pc_brc.json", - "mcconfig": "fifoStrict.json", - "memspec": "HBM2.json", - "simconfig": "hbm2.json", - "simulationid": "hbm2-example", - "thermalconfig": "config.json", - "tracesetup": [ - { - "clkMhz": 1000, - "name": "trace1_test4.stl" - }, - { - "clkMhz": 1000, - "name": "trace2_test4.stl" - } - ] - } -} diff --git a/tests/tests_regression/LPDDR4/configs/amconfigs/am_lpddr4_8Gbx16_brc.json b/tests/tests_regression/LPDDR4/configs/amconfigs/am_lpddr4_8Gbx16_brc.json deleted file mode 100644 index e9b3ac9f..00000000 --- a/tests/tests_regression/LPDDR4/configs/amconfigs/am_lpddr4_8Gbx16_brc.json +++ /dev/null @@ -1,42 +0,0 @@ -{ - "CONGEN": { - "BANK_BIT": [ - 27, - 28, - 29 - ], - "BYTE_BIT": [ - 0 - ], - "COLUMN_BIT": [ - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10 - ], - "ROW_BIT": [ - 11, - 12, - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26 - ] - } -} \ No newline at end of file diff --git a/tests/tests_regression/LPDDR4/configs/mcconfigs/fifo.json b/tests/tests_regression/LPDDR4/configs/mcconfigs/fifo.json deleted file mode 100644 index d1793358..00000000 --- a/tests/tests_regression/LPDDR4/configs/mcconfigs/fifo.json +++ /dev/null @@ -1,14 +0,0 @@ -{ - "mcconfig": { - "PagePolicy": "OpenAdaptive", - "Scheduler": "Fifo", - "RequestBufferSize": 8, - "CmdMux": "Oldest", - "RespQueue": "Fifo", - "RefreshPolicy": "Bankwise", - "RefreshMaxPostponed": 8, - "RefreshMaxPulledin": 8, - "PowerDownPolicy": "NoPowerDown", - "PowerDownTimeout": 100 - } -} \ No newline at end of file diff --git a/tests/tests_regression/LPDDR4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json b/tests/tests_regression/LPDDR4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json deleted file mode 100644 index 34230486..00000000 --- a/tests/tests_regression/LPDDR4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json +++ /dev/null @@ -1,51 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 16, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 1, - "nbrOfChannels": 1, - "nbrOfDevices": 1, - "nbrOfRows": 65536, - "width": 16 - }, - "memoryId": "JEDEC_8Gb_LPDDR4-3200_16bit", - "memoryType": "LPDDR4", - "memtimingspec": { - "CCD": 8, - "CKE": 12, - "CMDCKE": 3, - "DQS2DQ": 2, - "DQSCK": 6, - "DQSS": 1, - "ESCKE": 3, - "FAW": 64, - "PPD": 4, - "RAS": 68, - "RCD": 29, - "REFI": 6246, - "REFIPB": 780, - "RFCAB": 448, - "RFCPB": 224, - "RL": 28, - "RPAB": 34, - "RPPB": 29, - "RCAB": 102, - "RCPB": 97, - "RPST": 0, - "RRD": 16, - "RTP": 12, - "SR": 24, - "WL": 14, - "WPRE": 2, - "WR": 29, - "WTR": 16, - "XP": 12, - "XSR": 460, - "RTRS": 1, - "clkMhz": 1600 - } - } -} diff --git a/tests/tests_regression/LPDDR4/configs/simulator/lpddr4.json b/tests/tests_regression/LPDDR4/configs/simulator/lpddr4.json deleted file mode 100644 index 6ea5b1bd..00000000 --- a/tests/tests_regression/LPDDR4/configs/simulator/lpddr4.json +++ /dev/null @@ -1,19 +0,0 @@ -{ - "simconfig": { - "AddressOffset": 0, - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Disabled", - "EnableWindowing": false, - "ErrorCSVFile": "", - "ErrorChipSeed": 42, - "PowerAnalysis": false, - "SimulationName": "lpddr4", - "SimulationProgressBar": true, - "StoreMode": "NoStorage", - "ThermalSimulation": false, - "UseMalloc": false, - "WindowSize": 1000 - } -} diff --git a/tests/tests_regression/LPDDR4/configs/thermalsim/config.json b/tests/tests_regression/LPDDR4/configs/thermalsim/config.json deleted file mode 100644 index b88ed84c..00000000 --- a/tests/tests_regression/LPDDR4/configs/thermalsim/config.json +++ /dev/null @@ -1,15 +0,0 @@ -{ - "thermalsimconfig": { - "TemperatureScale": "Celsius", - "StaticTemperatureDefaultValue": 89, - "ThermalSimPeriod":100, - "ThermalSimUnit":"us", - "PowerInfoFile": "powerInfo.json", - "IceServerIp": "127.0.0.1", - "IceServerPort": 11880, - "SimPeriodAdjustFactor" : 10, - "NPowStableCyclesToIncreasePeriod": 5, - "GenerateTemperatureMap": true, - "GeneratePowerMap": true - } -} diff --git a/tests/tests_regression/LPDDR4/configs/thermalsim/core.flp b/tests/tests_regression/LPDDR4/configs/thermalsim/core.flp deleted file mode 100644 index e85e6801..00000000 --- a/tests/tests_regression/LPDDR4/configs/thermalsim/core.flp +++ /dev/null @@ -1,45 +0,0 @@ -CPUs : - - position 0, 0 ; - dimension 2750, 4300 ; - -GPU : - - position 3350, 0 ; - dimension 2750, 4000 ; - -BASEBAND1 : - - position 4250, 4000 ; - dimension 1850, 3300 ; - -BASEBAND2 : - - position 3350, 7300 ; - dimension 2750, 3300 ; - -LLCACHE : - - position 0, 4300 ; - dimension 1900, 3000 ; - -DRAMCTRL1 : - - position 1900, 4300 ; - dimension 850, 3000 ; - -DRAMCTRL2 : - - position 3350, 4000 ; - dimension 900, 3300 ; - -TSVS : - - position 2750, 2300 ; - dimension 600, 6000 ; - -ACELLERATORS : - - position 0, 7300 ; - dimension 2750, 3300 ; - diff --git a/tests/tests_regression/LPDDR4/configs/thermalsim/mem.flp b/tests/tests_regression/LPDDR4/configs/thermalsim/mem.flp deleted file mode 100644 index 29d02254..00000000 --- a/tests/tests_regression/LPDDR4/configs/thermalsim/mem.flp +++ /dev/null @@ -1,16 +0,0 @@ -channel0 : - position 150, 100 ; - dimension 2600, 5200 ; - -channel1 : - position 3350, 100 ; - dimension 2600, 5200 ; - -channel2 : - position 150, 5300 ; - dimension 2600, 5200 ; - -channel3 : - position 3350, 5300 ; - dimension 2600, 5200 ; - diff --git a/tests/tests_regression/LPDDR4/configs/thermalsim/powerInfo.json b/tests/tests_regression/LPDDR4/configs/thermalsim/powerInfo.json deleted file mode 100644 index 524f690f..00000000 --- a/tests/tests_regression/LPDDR4/configs/thermalsim/powerInfo.json +++ /dev/null @@ -1,20 +0,0 @@ -{ - "powerInfo": { - "dram_die_channel0": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel1": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel2": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel3": { - "init_pow": 0, - "threshold": 1.0 - } - } -} diff --git a/tests/tests_regression/LPDDR4/configs/thermalsim/stack.stk b/tests/tests_regression/LPDDR4/configs/thermalsim/stack.stk deleted file mode 100644 index ec74f020..00000000 --- a/tests/tests_regression/LPDDR4/configs/thermalsim/stack.stk +++ /dev/null @@ -1,49 +0,0 @@ -material SILICON : - thermal conductivity 1.30e-4 ; - volumetric heat capacity 1.628e-12 ; - -material BEOL : - thermal conductivity 2.25e-6 ; - volumetric heat capacity 2.175e-12 ; - -material COPPER : - thermal conductivity 4.01e-04 ; - volumetric heat capacity 3.37e-12 ; - -top heat sink : - //sink height 1e03, area 100e06, material COPPER ; - //spreader height 0.5e03, area 70e06, material SILICON ; - heat transfer coefficient 1.3e-09 ; - temperature 318.15 ; -dimensions : - chip length 6100, width 10600 ; - cell length 100, width 100 ; - - -layer PCB : - height 10 ; - material BEOL ; - -die DRAM : - layer 58.5 SILICON ; - source 2 SILICON ; - layer 1.5 BEOL ; - layer 58.5 SILICON ; - - -stack: - die DRAM_DIE DRAM floorplan "./mem.flp" ; - layer CONN_TO_PCB PCB ; - -solver: - transient step 0.01, slot 0.05 ; - initial temperature 300.0 ; - -output: - Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); - Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); - Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); - Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); - Tmap (DRAM_DIE, "output1.txt", slot) ; - Pmap (DRAM_DIE, "output2.txt", slot) ; - diff --git a/tests/tests_regression/LPDDR4/lpddr4-example.json b/tests/tests_regression/LPDDR4/lpddr4-example.json new file mode 100644 index 00000000..5aa31ec2 --- /dev/null +++ b/tests/tests_regression/LPDDR4/lpddr4-example.json @@ -0,0 +1,129 @@ +{ + "simulation": { + "addressmapping": { + "BANK_BIT": [ + 27, + 28, + 29 + ], + "BYTE_BIT": [ + 0 + ], + "COLUMN_BIT": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10 + ], + "ROW_BIT": [ + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26 + ] + }, + "mcconfig": { + "PagePolicy": "OpenAdaptive", + "Scheduler": "Fifo", + "RequestBufferSize": 8, + "CmdMux": "Oldest", + "RespQueue": "Fifo", + "RefreshPolicy": "Bankwise", + "RefreshMaxPostponed": 8, + "RefreshMaxPulledin": 8, + "PowerDownPolicy": "NoPowerDown", + "PowerDownTimeout": 100 + }, + "memspec": { + "memarchitecturespec": { + "burstLength": 16, + "dataRate": 2, + "nbrOfBanks": 8, + "nbrOfColumns": 1024, + "nbrOfRanks": 1, + "nbrOfChannels": 1, + "nbrOfDevices": 1, + "nbrOfRows": 65536, + "width": 16 + }, + "memoryId": "JEDEC_8Gb_LPDDR4-3200_16bit", + "memoryType": "LPDDR4", + "memtimingspec": { + "CCD": 8, + "CKE": 12, + "CMDCKE": 3, + "DQS2DQ": 2, + "DQSCK": 6, + "DQSS": 1, + "ESCKE": 3, + "FAW": 64, + "PPD": 4, + "RAS": 68, + "RCD": 29, + "REFI": 6246, + "REFIPB": 780, + "RFCAB": 448, + "RFCPB": 224, + "RL": 28, + "RPAB": 34, + "RPPB": 29, + "RCAB": 102, + "RCPB": 97, + "RPST": 0, + "RRD": 16, + "RTP": 12, + "SR": 24, + "WL": 14, + "WPRE": 2, + "WR": 29, + "WTR": 16, + "XP": 12, + "XSR": 460, + "RTRS": 1, + "clkMhz": 1600 + } + }, + "simconfig": { + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "ECCControllerMode": "Disabled", + "EnableWindowing": false, + "ErrorCSVFile": "", + "ErrorChipSeed": 42, + "PowerAnalysis": false, + "SimulationName": "lpddr4", + "SimulationProgressBar": true, + "StoreMode": "NoStorage", + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 + }, + "simulationid": "lpddr4-example", + "tracesetup": [ + { + "clkMhz": 1600, + "name": "trace_lpddr4.stl" + } + ] + } +} diff --git a/tests/tests_regression/LPDDR4/simulations/lpddr4-example.json b/tests/tests_regression/LPDDR4/simulations/lpddr4-example.json deleted file mode 100644 index 30211e69..00000000 --- a/tests/tests_regression/LPDDR4/simulations/lpddr4-example.json +++ /dev/null @@ -1,16 +0,0 @@ -{ - "simulation": { - "addressmapping": "am_lpddr4_8Gbx16_brc.json", - "mcconfig": "fifo.json", - "memspec": "JEDEC_8Gb_LPDDR4-3200_16bit.json", - "simconfig": "lpddr4.json", - "simulationid": "lpddr4-example", - "thermalconfig": "config.json", - "tracesetup": [ - { - "clkMhz": 1600, - "name": "trace_lpddr4.stl" - } - ] - } -}