Remove deprecated gem5 files.
This commit is contained in:
Lukas Steiner
@@ -141,10 +141,6 @@ Syntax example:
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10: read 0x400180
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```
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### Elastic Traces
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More information about elastic traces can be found in the [gem5 readme](../src/gem5/README.md).
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## Trace Player
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A trace player is equivalent to a bus master device (processor, FPGA, etc.). It reads an input trace file and translates each line into a new memory request. By adding a new device element into the trace setup section one can specify a new trace player, its operating frequency and its trace file.
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@@ -1,448 +0,0 @@
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[root]
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type=Root
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children=system
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eventq_index=0
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full_system=false
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sim_quantum=0
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time_sync_enable=false
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time_sync_period=100000000000
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time_sync_spin_threshold=100000000
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[system]
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type=System
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children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler membus physmem tlm voltage_domain
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boot_osflags=a
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cache_line_size=64
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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exit_on_work_items=false
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init_param=0
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kernel=
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kernel_addr_check=true
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kernel_extras=
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load_addr_mask=18446744073709551615
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load_offset=0
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mem_mode=timing
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mem_ranges=0:536870911:0:0:0:0
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memories=system.physmem
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mmap_using_noreserve=false
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multi_thread=false
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num_work_ids=16
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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power_model=
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readfile=
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symbolfile=
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thermal_components=
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thermal_model=Null
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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system_port=system.membus.slave[0]
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[system.clk_domain]
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type=SrcClockDomain
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clock=1000
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domain_id=-1
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eventq_index=0
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init_perf_level=0
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voltage_domain=system.voltage_domain
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[system.cpu]
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type=TraceCPU
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children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
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checker=Null
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clk_domain=system.clk_domain
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cpu_id=0
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dataTraceFile=../../DRAMSys/gem5/gem5_etrace/system.cpu.traceListener.data.gz
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default_p_state=UNDEFINED
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do_checkpoint_insts=true
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do_quiesce=true
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do_statistics_insts=true
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dstage2_mmu=system.cpu.dstage2_mmu
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dtb=system.cpu.dtb
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enableEarlyExit=false
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eventq_index=0
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freqMultiplier=1.0
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function_trace=false
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function_trace_start=0
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instTraceFile=../../DRAMSys/gem5/gem5_etrace/system.cpu.traceListener.inst.gz
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interrupts=system.cpu.interrupts
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isa=system.cpu.isa
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istage2_mmu=system.cpu.istage2_mmu
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itb=system.cpu.itb
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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numThreads=1
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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power_gating_on_idle=false
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power_model=
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profile=0
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progressMsgInterval=0
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progress_interval=0
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pwr_gating_latency=300
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simpoint_start_insts=
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sizeLoadBuffer=16
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sizeROB=40
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sizeStoreBuffer=16
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socket_id=0
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switched_out=false
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syscallRetryLatency=10000
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system=system
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tracer=system.cpu.tracer
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wait_for_remote_gdb=false
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workload=
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dcache_port=system.cpu.dcache.cpu_side
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icache_port=system.cpu.icache.cpu_side
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[system.cpu.dcache]
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type=Cache
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children=replacement_policy tags
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addr_ranges=0:18446744073709551615:0:0:0:0
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assoc=2
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clk_domain=system.clk_domain
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clusivity=mostly_incl
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data_latency=2
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default_p_state=UNDEFINED
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demand_mshr_reserve=1
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eventq_index=0
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is_read_only=false
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max_miss_count=0
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mshrs=4
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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power_model=
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prefetch_on_access=false
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prefetcher=Null
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replacement_policy=system.cpu.dcache.replacement_policy
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tag_latency=2
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tags=system.cpu.dcache.tags
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tgts_per_mshr=20
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warmup_percentage=0
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write_buffers=8
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writeback_clean=false
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cpu_side=system.cpu.dcache_port
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mem_side=system.membus.slave[2]
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[system.cpu.dcache.replacement_policy]
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type=LRURP
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eventq_index=0
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[system.cpu.dcache.tags]
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type=BaseSetAssoc
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assoc=2
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block_size=64
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clk_domain=system.clk_domain
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data_latency=2
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default_p_state=UNDEFINED
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eventq_index=0
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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power_model=
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replacement_policy=system.cpu.dcache.replacement_policy
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sequential_access=false
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size=32768
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tag_latency=2
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warmup_percentage=0
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[system.cpu.dstage2_mmu]
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type=ArmStage2MMU
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children=stage2_tlb
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eventq_index=0
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stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
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sys=system
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tlb=system.cpu.dtb
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[system.cpu.dstage2_mmu.stage2_tlb]
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type=ArmTLB
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children=walker
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eventq_index=0
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is_stage2=true
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size=32
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sys=system
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walker=system.cpu.dstage2_mmu.stage2_tlb.walker
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[system.cpu.dstage2_mmu.stage2_tlb.walker]
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type=ArmTableWalker
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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is_stage2=true
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num_squash_per_cycle=2
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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power_model=
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sys=system
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[system.cpu.dtb]
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type=ArmTLB
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children=walker
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eventq_index=0
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is_stage2=false
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size=64
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sys=system
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walker=system.cpu.dtb.walker
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[system.cpu.dtb.walker]
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type=ArmTableWalker
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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is_stage2=false
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num_squash_per_cycle=2
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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power_model=
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sys=system
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[system.cpu.icache]
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type=Cache
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children=replacement_policy tags
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addr_ranges=0:18446744073709551615:0:0:0:0
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assoc=2
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clk_domain=system.clk_domain
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clusivity=mostly_incl
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data_latency=2
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default_p_state=UNDEFINED
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demand_mshr_reserve=1
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eventq_index=0
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is_read_only=true
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max_miss_count=0
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mshrs=4
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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power_model=
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prefetch_on_access=false
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prefetcher=Null
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replacement_policy=system.cpu.icache.replacement_policy
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tag_latency=2
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tags=system.cpu.icache.tags
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tgts_per_mshr=20
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warmup_percentage=0
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write_buffers=8
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writeback_clean=true
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cpu_side=system.cpu.icache_port
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mem_side=system.membus.slave[1]
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[system.cpu.icache.replacement_policy]
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type=LRURP
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eventq_index=0
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[system.cpu.icache.tags]
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type=BaseSetAssoc
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assoc=2
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block_size=64
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clk_domain=system.clk_domain
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data_latency=2
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default_p_state=UNDEFINED
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eventq_index=0
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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power_model=
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replacement_policy=system.cpu.icache.replacement_policy
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sequential_access=false
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size=32768
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tag_latency=2
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warmup_percentage=0
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[system.cpu.interrupts]
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type=ArmInterrupts
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eventq_index=0
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[system.cpu.isa]
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type=ArmISA
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decoderFlavour=Generic
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eventq_index=0
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fpsid=1090793632
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id_aa64afr0_el1=0
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||||
id_aa64afr1_el1=0
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id_aa64dfr0_el1=1052678
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id_aa64dfr1_el1=0
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id_aa64isar0_el1=0
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id_aa64isar1_el1=0
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||||
id_aa64mmfr0_el1=15728642
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id_aa64mmfr1_el1=0
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id_isar0=34607377
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id_isar1=34677009
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id_isar2=555950401
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id_isar3=17899825
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||||
id_isar4=268501314
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id_isar5=0
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id_mmfr0=270536963
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id_mmfr1=0
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id_mmfr2=19070976
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id_mmfr3=34611729
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impdef_nop=false
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midr=1091551472
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pmu=Null
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system=system
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vecRegRenameMode=Full
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[system.cpu.istage2_mmu]
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type=ArmStage2MMU
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children=stage2_tlb
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eventq_index=0
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||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
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sys=system
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tlb=system.cpu.itb
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[system.cpu.istage2_mmu.stage2_tlb]
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type=ArmTLB
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children=walker
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||||
eventq_index=0
|
||||
is_stage2=true
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size=32
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sys=system
|
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walker=system.cpu.istage2_mmu.stage2_tlb.walker
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[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
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default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
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type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.cpu_voltage_domain
|
||||
|
||||
[system.cpu_voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.tlm.port
|
||||
slave=system.system_port system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
range=0:134217727:0:0:0:0
|
||||
|
||||
[system.tlm]
|
||||
type=ExternalSlave
|
||||
addr_ranges=0:536870911:0:0:0:0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
port_data=transactor
|
||||
port_type=tlm_slave
|
||||
power_model=
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@@ -1,553 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler external_memory l2 membus physmem tol2bus voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=false
|
||||
kernel_extras=
|
||||
load_addr_mask=18446744073709551615
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:536870911:0:0:0:0
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
istage2_mmu=system.cpu.istage2_mmu
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_gating_on_idle=false
|
||||
power_model=
|
||||
profile=0
|
||||
progress_interval=0
|
||||
pwr_gating_latency=300
|
||||
simpoint_start_insts=
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
wait_for_remote_gdb=false
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=65536
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.tol2bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.dcache.replacement_policy
|
||||
sequential_access=false
|
||||
size=65536
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
port=system.tol2bus.slave[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.tol2bus.slave[0]
|
||||
|
||||
[system.cpu.icache.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.cpu.icache.replacement_policy
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
warmup_percentage=0
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
impdef_nop=false
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
vecRegRenameMode=Full
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
sys=system
|
||||
port=system.tol2bus.slave[2]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=Process
|
||||
cmd=../../DRAMSys/gem5/gem5_se/hello-ARM/hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=../../DRAMSys/gem5/gem5_se/hello-ARM/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
maxStackSize=67108864
|
||||
output=cout
|
||||
pgid=100
|
||||
pid=100
|
||||
ppid=0
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.cpu_voltage_domain
|
||||
|
||||
[system.cpu_voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.external_memory]
|
||||
type=ExternalSlave
|
||||
addr_ranges=0:536870911:0:0:0:0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
port_data=transactor
|
||||
port_type=tlm_slave
|
||||
power_model=
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.l2]
|
||||
type=Cache
|
||||
children=replacement_policy tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
replacement_policy=system.l2.replacement_policy
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
system=system
|
||||
tag_latency=20
|
||||
tags=system.l2.tags
|
||||
tgts_per_mshr=12
|
||||
warmup_percentage=0
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.tol2bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.l2.replacement_policy]
|
||||
type=LRURP
|
||||
eventq_index=0
|
||||
|
||||
[system.l2.tags]
|
||||
type=BaseSetAssoc
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
replacement_policy=system.l2.replacement_policy
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
tag_latency=20
|
||||
warmup_percentage=0
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.external_memory.port
|
||||
slave=system.system_port system.l2.mem_side
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
range=0:134217727:0:0:0:0
|
||||
|
||||
[system.tol2bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=1
|
||||
snoop_filter=system.tol2bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.l2.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.tol2bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
Binary file not shown.
@@ -1,282 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler external_memory membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=false
|
||||
kernel_extras=
|
||||
kvm_vm=Null
|
||||
load_addr_mask=18446744073709551615
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:536870911:0:0:0:0
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=apic_clk_domain dtb interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_gating_on_idle=false
|
||||
power_model=
|
||||
profile=0
|
||||
progress_interval=0
|
||||
pwr_gating_latency=300
|
||||
simpoint_start_insts=
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
wait_for_remote_gdb=false
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.apic_clk_domain]
|
||||
type=DerivedClockDomain
|
||||
clk_divider=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
system=system
|
||||
port=system.membus.slave[4]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clk_domain=system.cpu.apic_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
int_latency=1000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
power_model=
|
||||
system=system
|
||||
int_master=system.membus.slave[5]
|
||||
int_slave=system.membus.master[1]
|
||||
pio=system.membus.master[0]
|
||||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
system=system
|
||||
port=system.membus.slave[3]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=Process
|
||||
cmd=../../DRAMSys/gem5/gem5_se/hello-X86/hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=../../DRAMSys/gem5/gem5_se/hello-X86/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
maxStackSize=67108864
|
||||
output=cout
|
||||
pgid=100
|
||||
pid=100
|
||||
ppid=0
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.cpu_voltage_domain
|
||||
|
||||
[system.cpu_voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.external_memory]
|
||||
type=ExternalSlave
|
||||
addr_ranges=0:536870911:0:0:0:0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
port_data=transactor
|
||||
port_type=tlm_slave
|
||||
power_model=
|
||||
port=system.membus.master[2]
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
point_of_unification=true
|
||||
power_model=
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.external_memory.port
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=
|
||||
range=0:134217727:0:0:0:0
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.0
|
||||
|
||||
Binary file not shown.
Reference in New Issue
Block a user