Commit Graph

1798 Commits

Author SHA1 Message Date
Lukas Steiner
efdba2c9ee Merge branch 'TA_dynamic_windows' into 'develop'
TA Dynamic Windows and Fixes

See merge request ems/astdm/dram.sys!272
2020-11-25 16:14:15 +01:00
Lukas Steiner
0f0eaf62bd Merge branch 'power_and_buffer_analysis' into TA_dynamic_windows 2020-11-25 15:28:59 +01:00
Lukas Steiner
e11420cecd Change initial splitter size in TA. 2020-11-25 15:27:47 +01:00
Lukas Steiner
2e652deaf4 Fix checkboxes in metrics window. 2020-11-25 15:02:08 +01:00
Matthias Jung
09eed96338 New delayed metric 2020-11-25 11:02:48 +01:00
Lukas Steiner
21afa61a6b Add splitters. 2020-11-23 17:32:07 +01:00
Lukas Steiner
2277a6b5f9 Merge branch 'power_and_buffer_analysis' into 'develop'
Power and buffer analysis

See merge request ems/astdm/dram.sys!271
2020-11-23 14:51:34 +01:00
Matthias Jung
e7b7653029 Some changes in analyzer 2020-11-23 14:41:21 +01:00
Lukas Steiner
0cbe09aca1 Merge branch 'DDR5' into 'develop'
Rambus Analysis Features

See merge request ems/astdm/dram.sys!270
2020-11-23 13:24:44 +01:00
Lukas Steiner
c5f89293bd Insert window bandwidth/buffer depth only when windowing is enabled. 2020-11-23 11:50:44 +01:00
Lukas Steiner
fc3252f6ef Handle empty configuration files. 2020-11-13 10:57:48 +01:00
Lukas Steiner
362ca31303 Use uint64_t for number of lines in trace player. 2020-11-13 09:01:05 +01:00
Matthias Jung
981637188f Added Power Analysis in Trace Analyzer 2020-11-11 10:31:49 +01:00
Lukas Steiner
7bba11e047 Move initial SQL table into source file. 2020-11-11 09:52:34 +01:00
Lukas Steiner
3be2d9f56b Include average bandwidth windowing. 2020-11-11 09:51:31 +01:00
Lukas Steiner
ed8ee0ec06 Merge branch 'rambus_scheduler' into DDR5 2020-11-04 16:50:06 +01:00
Lukas Steiner
ccf686baf6 Merge branch 'traceAnalyzer_LatencyAnalysis' into rambus_scheduler 2020-11-04 16:48:31 +01:00
Lukas Steiner
fe53143f64 Merge branch 'rambus_scheduler' into DDR5 2020-11-04 16:04:25 +01:00
Lukas Steiner
7d7dba4c68 Reset simulator config. 2020-11-04 16:03:49 +01:00
Lukas Steiner
cc3a7a617b Merge branch 'traceAnalyzer_LatencyAnalysis' into rambus_scheduler 2020-11-04 15:58:55 +01:00
Lukas Steiner
d723306130 Merge branch 'rambus_scheduler' into DDR5
# Conflicts:
#	DRAMSys/library/src/common/TlmRecorder.cpp
2020-11-04 15:56:26 +01:00
Lukas Steiner
6108c6ca93 Add max buffer depth to general info table. 2020-11-04 15:46:08 +01:00
Matthias Jung
5b4f5e0c74 Added Queue Analysis Plot 2020-11-04 15:36:13 +01:00
Lukas Steiner
d7409542a1 Add simple arbiter. 2020-11-04 15:26:51 +01:00
Lukas Steiner
d85790ad63 Add shared scheduler buffer counter. 2020-11-04 13:26:28 +01:00
Lukas Steiner
0fec34240d Add scheduler buffer depth recording. 2020-11-04 11:15:22 +01:00
Lukas Steiner
e5d340a603 Merge branch 'rambus_scheduler' into DDR5. 2020-11-03 15:13:19 +01:00
Matthias Jung
11bfed8b6a Finished Latency Analysis Tool in TA 2020-11-02 19:53:53 +01:00
Lukas Steiner
9315cd1345 Set payload IDs at correct time. 2020-10-28 11:59:09 +01:00
Lukas Steiner
d2878c62f2 Add reorder arbiter. 2020-10-28 11:18:13 +01:00
Matthias Jung
c744c43ab2 Added first latency analysis 2020-10-27 21:29:39 +01:00
Lukas Steiner
fe1d8eafdd Code cleanup. 2020-10-27 16:41:00 +01:00
Lukas Steiner
2d507fb327 Decrement active transactions after BEGIN_RESP. 2020-10-27 16:16:48 +01:00
Lukas Steiner
f6752cb09a Improved arbiter with thread and channel queues. 2020-10-27 16:02:11 +01:00
Lukas Steiner
ac670f2ea7 Merge branch 'rambus_scheduler' into DDR5 2020-10-27 10:04:15 +01:00
Lukas Steiner
5d6042a16a Renaming of payload IDs in arbiter. 2020-10-27 09:57:48 +01:00
Lukas Steiner
2c7f555172 Add threadPayloadID. 2020-10-26 14:36:35 +01:00
Lukas Steiner
baf2440a4d Change payloadID to channelPayloadID. 2020-10-26 14:15:06 +01:00
Lukas Steiner
b70c3351d3 Prepare arbiter for reorder buffer. 2020-10-26 13:54:11 +01:00
Lukas Steiner
3af9159b44 Missing cmake changes. 2020-10-26 09:10:35 +01:00
Lukas Steiner
ffca62be70 Renaming scheduler buffer to buffer counter. 2020-10-26 09:05:50 +01:00
Lukas Steiner
11ec4036ee Merge branch 'rambus_scheduler' into DDR5
# Conflicts:
#	DRAMSys/library/src/configuration/memspec/MemSpec.h
#	DRAMSys/library/src/controller/Controller.cpp
#	DRAMSys/library/src/simulation/DRAMSys.cpp
#	DRAMSys/library/src/simulation/DRAMSysRecordable.cpp
2020-10-26 08:37:59 +01:00
Lukas Steiner
e26a438d06 Code formatting. 2020-10-23 15:04:40 +02:00
Lukas Steiner
7bab23f80e Move methods from config to memspec. 2020-10-23 15:00:49 +02:00
Lukas Steiner
bfb5f16563 Move getSimMemSizeInBytes to memspec. 2020-10-23 14:24:32 +02:00
Lukas Steiner
65d148b7a7 Improved configuration process. 2020-10-23 12:07:30 +02:00
Lukas Steiner
472c810f89 Add separate scheduler buffers (bankwise, separate read/write). 2020-10-22 16:41:49 +02:00
Lukas Steiner
f95a35e9e8 Merge branch 'develop' into DDR5 2020-10-22 14:10:24 +02:00
Lukas Steiner
27819b4a7b Merge branch 'cpp_speedups' into 'develop'
Source code level speedups.

See merge request ems/astdm/dram.sys!269
2020-10-22 14:05:38 +02:00
Lukas Steiner
32c7148dd9 Set correct time of generation in arbiter. 2020-10-22 13:43:00 +02:00