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Author SHA1 Message Date
Matthias Jung
7eebbf3bdf Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system 2017-07-19 10:37:46 +03:00
Matthias Jung
9985b9175e Changed FR_FCFS_RP Scheduler 
Added hazard detection and simplification of the code.
 2017-07-19 10:37:00 +03:00
Éder F. Zulian
3a3d8162b2 Minor improvements after PR#169 2017-07-15 13:55:45 +02:00
fzeder
db7f4dbee0 Merge pull request #169 from trancong/master 
Update  to generate per-thread plots and per-thread metrics
 2017-07-15 13:09:49 +02:00
Thanh C. Tran
391bd79ac0 Enable per-thread metrics 2017-07-14 21:31:51 +02:00
Thanh C. Tran
024b288f3f Change script to automatically generate per-thread plots 2017-07-14 14:43:11 +02:00
Matthias Jung
e27b147634 Merge pull request #168 from trancong/master 
Few fixes for plotting script, TLM Recorder and Debugger
 2017-07-13 13:21:21 +02:00
Matthias Jung
ba3a1d704f Read Priorization for FR_FCFS 
I Added the feature that RD is always prioritized before WR for FR_FCFS.
Instead of searching the next row hit for a specific bank it searches
for the next row hit which is a read. If there is not read hit found it
searches for a write read. If no write read is found it takes the oldest
request. Even this could be further improved of course because RD/WR
switching is actually not a per bank problem its because of the shared
busses.
 2017-07-12 23:32:17 +02:00
Thanh C. Tran
665b38f5cf Fix system hang when plotting histogram 2017-07-12 15:55:52 +02:00
Thanh C. Tran
09993f793f Fix memory leak when destroy TlmRecoder object by calling sqlite3_finalize() 2017-07-12 15:52:24 +02:00
Thanh C. Tran
5bc71d04e7 Add missing step to write debug message into a text file 2017-07-12 15:50:13 +02:00
Matthias Jung
e65f3c3573 Added elastic trace example for the memory hog 2017-06-26 00:23:40 +02:00
Matthias Jung
f17fd94616 Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system 2017-06-25 18:10:05 +02:00
Matthias Jung
2239fefa61 Added some more gem5 related files 2017-06-25 18:08:25 +02:00
fzeder
85f36de55b Merge pull request #164 from jfeldman/master 
ECC Controller implementation with basic Hamming code
 2017-06-22 14:56:32 +02:00
fzeder
bd883f031c Merge branch 'master' into master 2017-06-22 13:32:19 +02:00
fzeder
53056bc2b4 Merge pull request #160 from trancong/Simple_SMS 
Simple SMS branch
 2017-06-22 13:20:52 +02:00
Thanh C. Tran
a5e62f75ab Revert back to use default simulation file 2017-06-22 12:37:46 +02:00
Thanh C. Tran
78a4637fdd Merge branch 'master' into Simple_SMS 
* master:
  Fix some segfaults.
 2017-06-22 12:31:16 +02:00
Éder F. Zulian
de7381ae49 Fix some segfaults. 
In the current implementation the object deletion order is important.

Messages regarding power and energy are printed inside the Dram destructor.
The controller object was destructed and then called by the Dram object.

The behavior varies with compiler (clang or gcc). It seems that clang deletes
objects later than gcc masking some bugs.
 2017-06-22 12:05:40 +02:00
Johannes Feldmann
928d13af2f Merge branch 'develop' 
# Conflicts:
#	DRAMSys/simulator/src/error/controllerECC.h
 2017-06-22 09:38:20 +02:00
Thanh C. Tran
64b105d5c7 Fix Disable Refresh Issue 2017-06-21 16:42:47 +02:00
Thanh C. Tran
f09d47e143 Remove unused parameters and add Request Buffer's Size parameter in SMS xml config file 2017-06-21 15:41:11 +02:00
Thanh C. Tran
276c9efb18 Merge branch 'master' into Simple_SMS 
* master:
  Commented the FR_FCFS scheduler
  added a script for generating the memory hog traces
  Update path of gem5 files.
 2017-06-21 15:26:31 +02:00
Johannes Feldmann
ae0e7d47f9 Test configuration reverted. 2017-06-21 10:05:57 +02:00
Johannes Feldmann
d2ea359b50 AdjustNumBytesAfterECC function added and used in DRAM.h and errormodel.h 2017-06-21 10:03:56 +02:00
Johannes Feldmann
efbc723bab EccBaseClass ready to use. ECCHammnigClass created. 2017-06-20 21:29:03 +02:00
Matthias Jung
9ed9ba480b Commented the FR_FCFS scheduler 
since the original implementation the comments are missed. I just added
the comments such that anybody can understand it.
 2017-06-20 17:12:05 +02:00
Matthias Jung
2b332515bc Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system 2017-06-20 00:36:23 +02:00
Matthias Jung
6ebf9b5ac7 added a script for generating the memory hog traces 2017-06-20 00:34:42 +02:00
Éder F. Zulian
904aef9361 Update path of gem5 files. 2017-06-16 10:53:16 +02:00
Thanh C. Tran
dca7d88a68 Clean up unused classes & Add notes about SMS scheduler 2017-06-12 12:34:53 +02:00
Johannes Feldmann
d04f894592 BugFix: Data pointer are now stored correctly in the map of ECC Controller 2017-06-09 17:00:59 +02:00
Johannes Feldmann
d7e843c6e0 BugFix: Data pointer are now stored correctly in the map of ECC Controller 2017-06-09 16:57:46 +02:00
Johannes Feldmann
7de21cf056 Configuration for ECC Controller extended to make it possible to add other ECC Controller 2017-06-08 11:01:08 +02:00
Johannes Feldmann
778834f15c Removed deprecated files 2017-06-02 17:19:19 +02:00
Thanh C. Tran
ab2b87aaeb Fix bug 
1. Trying to drain request from empty request buffers & empty ready batch iterators
2. lastSelectedThread Iterator pointing to readybatchIters instead
 2017-06-01 02:24:05 +02:00
Thanh C. Tran
6d739c64f1 Finish multiple ready batch formation 2017-05-16 02:03:10 +02:00
Thanh C. Tran
dab2237572 First try to form multiple ready batches 2017-05-16 01:38:53 +02:00
Thanh C. Tran
d489db6a46 Fix bug 2017-05-16 01:35:10 +02:00
Thanh C. Tran
066569c856 Adding MPKC & bypass mechanism 2017-05-15 16:25:26 +02:00
Thanh C. Tran
ea8213da17 Add raw MPKC module for calculating MPKC rate 2017-05-11 23:27:47 +02:00
Thanh C. Tran
65c1abcc7a Simplify picking policy of the batch scheduler 2017-05-11 15:54:53 +02:00
Thanh C. Tran
9c4cb6f979 Fix auxiliary stuffs for simulating SMS 2017-05-11 15:28:45 +02:00
Thanh C. Tran
92bd873a3e Fix segmentation fault due to calling methods on NULL ReadyBatch Object 2017-05-09 23:23:44 +02:00
Thanh C. Tran
7d15ebc45e Fix undefined symbols for architecture x86_64 
"SMS::batchScheduler()", referenced from:
SMS::SMS(sc_core::sc_module_name, ControllerCore&, unsigned int) in libDRAMSys.a(Controller.o)
"vtable for SMS", referenced from:
SMS::SMS(sc_core::sc_module_name, ControllerCore&, unsigned int) in libDRAMSys.a(Controller.o)
NOTE: a missing vtable usually means the first non-inline virtual member function has no definition.
 2017-05-09 19:13:17 +02:00
Thanh C. Tran
9a6f012cc1 Merge branch 'master' into Simple_SMS 
* master: (36 commits)
  Reference code provided by Menbere.
  AddressOffset is only used when we use gem5.
  Avoid some assertions when using gem5
  Small fix.
  Fix for disable refresh
  Further imporovement of the gem5 integration
  gem5 subproject added to DRAMSys
  Added sonification script to the arbiter
  Sonification script added
  changes for 4 channels
  wideio
  Bandwidth over time plot
  Fix compilation for newer gcc versions.
  First step in fixing the test system
  Fixed Test Starting Script
  Fixed small bug in resource file
  Added outputs to plots.py for Matlab
  Bugfix order of compilation
  Fixed compile bug on MAC
  Fixed bug which was introduced due to boost removal
  ...

# Conflicts:
#	DRAMSys/simulator/resources/resources.pri
#	DRAMSys/simulator/simulator.pro
#	DRAMSys/simulator/src/simulation/main.cpp
 2017-05-09 17:13:09 +02:00
Johannes Feldmann
4d9a6f74d8 ControllerECC: stored data pointer will be erased from map if not needed anymore. 
Moved {ErrorChipSeed, ErrorCSVFile, StoreMode} from mcconfig zu simconfig
Error files moved to resources/error/ and are now named correctly.
 2017-05-08 10:13:57 +02:00
Johannes Feldmann
0b55dfd7e7 Revert several changes. 2017-05-04 12:22:31 +02:00
Johannes Feldmann
b3309eb238 Added comments 
Reverted all configurations
Adjusted resources.pri
Added the enable switch for controllerECC to README.md
 2017-05-04 12:08:07 +02:00