Added some more gem5 related files
This commit is contained in:
Matthias Jung
751
DRAMSys/gem5/configs/dualElasticTraceReplay.ini
Normal file
751
DRAMSys/gem5/configs/dualElasticTraceReplay.ini
Normal file
@@ -0,0 +1,751 @@
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[root]
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type=Root
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children=system
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eventq_index=0
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full_system=false
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sim_quantum=0
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||||
time_sync_enable=false
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||||
time_sync_period=100000000000
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time_sync_spin_threshold=100000000
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[system]
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type=System
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children=clk_domain cpu0 cpu1 cpu_clk_domain cpu_voltage_domain dvfs_handler membus1 membus2 physmem tlm1 tlm2 voltage_domain
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boot_osflags=a
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cache_line_size=64
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||||
clk_domain=system.clk_domain
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||||
default_p_state=UNDEFINED
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||||
eventq_index=0
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||||
exit_on_work_items=false
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||||
init_param=0
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||||
kernel=
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kernel_addr_check=true
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load_addr_mask=1099511627775
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load_offset=0
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mem_mode=timing
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||||
mem_ranges=0:536870911:0:0:0:0
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memories=system.physmem
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||||
mmap_using_noreserve=false
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multi_thread=false
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||||
num_work_ids=16
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||||
p_state_clk_gate_bins=20
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||||
p_state_clk_gate_max=1000000000000
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||||
p_state_clk_gate_min=1000
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||||
power_model=Null
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||||
readfile=
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||||
symbolfile=
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thermal_components=
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||||
thermal_model=Null
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||||
work_begin_ckpt_count=0
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||||
work_begin_cpu_id_exit=-1
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||||
work_begin_exit_count=0
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||||
work_cpus_ckpt_count=0
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||||
work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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system_port=system.membus1.slave[0]
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[system.clk_domain]
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type=SrcClockDomain
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clock=1000
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domain_id=-1
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eventq_index=0
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init_perf_level=0
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voltage_domain=system.voltage_domain
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[system.cpu0]
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type=TraceCPU
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children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
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checker=Null
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clk_domain=system.clk_domain
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cpu_id=0
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dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz
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default_p_state=UNDEFINED
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do_checkpoint_insts=true
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do_quiesce=true
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do_statistics_insts=true
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dstage2_mmu=system.cpu0.dstage2_mmu
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dtb=system.cpu0.dtb
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enableEarlyExit=false
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eventq_index=0
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freqMultiplier=1.0
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function_trace=false
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function_trace_start=0
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instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz
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interrupts=system.cpu0.interrupts
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isa=system.cpu0.isa
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istage2_mmu=system.cpu0.istage2_mmu
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itb=system.cpu0.itb
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max_insts_all_threads=0
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max_insts_any_thread=0
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||||
max_loads_all_threads=0
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||||
max_loads_any_thread=0
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numThreads=1
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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power_model=Null
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||||
profile=0
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||||
progressMsgInterval=0
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||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
sizeLoadBuffer=16
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||||
sizeROB=40
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sizeStoreBuffer=16
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socket_id=0
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switched_out=false
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syscallRetryLatency=10000
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system=system
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tracer=system.cpu0.tracer
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workload=
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dcache_port=system.cpu0.dcache.cpu_side
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icache_port=system.cpu0.icache.cpu_side
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[system.cpu0.dcache]
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type=Cache
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||||
children=tags
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||||
addr_ranges=0:18446744073709551615:0:0:0:0
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assoc=2
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||||
clk_domain=system.clk_domain
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clusivity=mostly_incl
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||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
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||||
eventq_index=0
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||||
is_read_only=false
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||||
max_miss_count=0
|
||||
mshrs=4
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||||
p_state_clk_gate_bins=20
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||||
p_state_clk_gate_max=1000000000000
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||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
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||||
response_latency=2
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||||
sequential_access=false
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||||
size=32768
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||||
system=system
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||||
tag_latency=2
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||||
tags=system.cpu0.dcache.tags
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||||
tgts_per_mshr=20
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||||
write_buffers=8
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||||
writeback_clean=false
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||||
cpu_side=system.cpu0.dcache_port
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||||
mem_side=system.membus1.slave[2]
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||||
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||||
[system.cpu0.dcache.tags]
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type=LRU
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||||
assoc=2
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||||
block_size=64
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||||
clk_domain=system.clk_domain
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data_latency=2
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default_p_state=UNDEFINED
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||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
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||||
p_state_clk_gate_min=1000
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||||
power_model=Null
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||||
sequential_access=false
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||||
size=32768
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||||
tag_latency=2
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||||
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||||
[system.cpu0.dstage2_mmu]
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||||
type=ArmStage2MMU
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||||
children=stage2_tlb
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||||
eventq_index=0
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||||
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
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||||
sys=system
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||||
tlb=system.cpu0.dtb
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||||
[system.cpu0.dstage2_mmu.stage2_tlb]
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||||
type=ArmTLB
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||||
children=walker
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||||
eventq_index=0
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||||
is_stage2=true
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||||
size=32
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||||
sys=system
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||||
walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
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||||
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||||
[system.cpu0.dstage2_mmu.stage2_tlb.walker]
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||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
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||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
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||||
num_squash_per_cycle=2
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||||
p_state_clk_gate_bins=20
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||||
p_state_clk_gate_max=1000000000000
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||||
p_state_clk_gate_min=1000
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||||
power_model=Null
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||||
sys=system
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||||
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||||
[system.cpu0.dtb]
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||||
type=ArmTLB
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||||
children=walker
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||||
eventq_index=0
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||||
is_stage2=false
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||||
size=64
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||||
sys=system
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||||
walker=system.cpu0.dtb.walker
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||||
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||||
[system.cpu0.dtb.walker]
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||||
type=ArmTableWalker
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||||
clk_domain=system.clk_domain
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||||
default_p_state=UNDEFINED
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||||
eventq_index=0
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||||
is_stage2=false
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||||
num_squash_per_cycle=2
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||||
p_state_clk_gate_bins=20
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||||
p_state_clk_gate_max=1000000000000
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||||
p_state_clk_gate_min=1000
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||||
power_model=Null
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||||
sys=system
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||||
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[system.cpu0.icache]
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type=Cache
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children=tags
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addr_ranges=0:18446744073709551615:0:0:0:0
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assoc=2
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||||
clk_domain=system.clk_domain
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clusivity=mostly_incl
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||||
data_latency=2
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||||
default_p_state=UNDEFINED
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||||
demand_mshr_reserve=1
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||||
eventq_index=0
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||||
is_read_only=true
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||||
max_miss_count=0
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||||
mshrs=4
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||||
p_state_clk_gate_bins=20
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||||
p_state_clk_gate_max=1000000000000
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||||
p_state_clk_gate_min=1000
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||||
power_model=Null
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||||
prefetch_on_access=false
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||||
prefetcher=Null
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||||
response_latency=2
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||||
sequential_access=false
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||||
size=32768
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||||
system=system
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||||
tag_latency=2
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||||
tags=system.cpu0.icache.tags
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||||
tgts_per_mshr=20
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||||
write_buffers=8
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||||
writeback_clean=true
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||||
cpu_side=system.cpu0.icache_port
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||||
mem_side=system.membus1.slave[1]
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||||
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[system.cpu0.icache.tags]
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||||
type=LRU
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||||
assoc=2
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||||
block_size=64
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||||
clk_domain=system.clk_domain
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||||
data_latency=2
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||||
default_p_state=UNDEFINED
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||||
eventq_index=0
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||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
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||||
power_model=Null
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||||
sequential_access=false
|
||||
size=32768
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||||
tag_latency=2
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||||
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||||
[system.cpu0.interrupts]
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||||
type=ArmInterrupts
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||||
eventq_index=0
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||||
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||||
[system.cpu0.isa]
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||||
type=ArmISA
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||||
decoderFlavour=Generic
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||||
eventq_index=0
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||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
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||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
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||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
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||||
id_mmfr1=0
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||||
id_mmfr2=19070976
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||||
id_mmfr3=34611729
|
||||
midr=1091551472
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||||
pmu=Null
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||||
system=system
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||||
|
||||
[system.cpu0.istage2_mmu]
|
||||
type=ArmStage2MMU
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||||
children=stage2_tlb
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||||
eventq_index=0
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||||
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
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||||
sys=system
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||||
tlb=system.cpu0.itb
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||||
|
||||
[system.cpu0.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu0.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu0.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu0.itb.walker
|
||||
|
||||
[system.cpu0.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1]
|
||||
type=TraceCPU
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=1
|
||||
dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu1.dstage2_mmu
|
||||
dtb=system.cpu1.dtb
|
||||
enableEarlyExit=false
|
||||
eventq_index=0
|
||||
freqMultiplier=1.0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz
|
||||
interrupts=system.cpu1.interrupts
|
||||
isa=system.cpu1.isa
|
||||
istage2_mmu=system.cpu1.istage2_mmu
|
||||
itb=system.cpu1.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progressMsgInterval=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
sizeLoadBuffer=16
|
||||
sizeROB=40
|
||||
sizeStoreBuffer=16
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu1.tracer
|
||||
workload=
|
||||
dcache_port=system.cpu1.dcache.cpu_side
|
||||
icache_port=system.cpu1.icache.cpu_side
|
||||
|
||||
[system.cpu1.dcache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu1.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu1.dcache_port
|
||||
mem_side=system.membus2.slave[1]
|
||||
|
||||
[system.cpu1.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
|
||||
[system.cpu1.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu1.dtb
|
||||
|
||||
[system.cpu1.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu1.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu1.dtb.walker
|
||||
|
||||
[system.cpu1.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu1.icache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu1.icache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu1.icache_port
|
||||
mem_side=system.membus2.slave[0]
|
||||
|
||||
[system.cpu1.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
|
||||
[system.cpu1.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu1.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
|
||||
[system.cpu1.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu1.itb
|
||||
|
||||
[system.cpu1.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu1.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu1.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu1.itb.walker
|
||||
|
||||
[system.cpu1.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.cpu_voltage_domain
|
||||
|
||||
[system.cpu_voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.membus1]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus1.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.tlm1.port
|
||||
slave=system.system_port system.cpu0.icache.mem_side system.cpu0.dcache.mem_side
|
||||
|
||||
[system.membus1.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.membus2]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus2.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.tlm2.port
|
||||
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
|
||||
|
||||
[system.membus2.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:134217727:0:0:0:0
|
||||
|
||||
[system.tlm1]
|
||||
type=ExternalSlave
|
||||
addr_ranges=0:268435455:0:0:0:0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
port_data=transactor1
|
||||
port_type=tlm_slave
|
||||
power_model=Null
|
||||
port=system.membus1.master[0]
|
||||
|
||||
[system.tlm2]
|
||||
type=ExternalSlave
|
||||
addr_ranges=0:268435455:0:0:0:0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
port_data=transactor2
|
||||
port_type=tlm_slave
|
||||
power_model=Null
|
||||
port=system.membus2.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
425
DRAMSys/gem5/configs/singleElasticTraceReplay.ini
Normal file
425
DRAMSys/gem5/configs/singleElasticTraceReplay.ini
Normal file
@@ -0,0 +1,425 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler membus physmem tlm voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:536870911:0:0:0:0
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TraceCPU
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
|
||||
checker=Null
|
||||
clk_domain=system.clk_domain
|
||||
cpu_id=0
|
||||
dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
enableEarlyExit=false
|
||||
eventq_index=0
|
||||
freqMultiplier=1.0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
istage2_mmu=system.cpu.istage2_mmu
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progressMsgInterval=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
sizeLoadBuffer=16
|
||||
sizeROB=40
|
||||
sizeStoreBuffer=16
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.membus.slave[2]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
sys=system
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
sys=system
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.cpu_voltage_domain
|
||||
|
||||
[system.cpu_voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.tlm.port
|
||||
slave=system.system_port system.cpu.icache.mem_side system.cpu.dcache.mem_side
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:134217727:0:0:0:0
|
||||
|
||||
[system.tlm]
|
||||
type=ExternalSlave
|
||||
addr_ranges=0:536870911:0:0:0:0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
port_data=transactor
|
||||
port_type=tlm_slave
|
||||
power_model=Null
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
@@ -97,10 +97,20 @@ int sc_main(int argc, char **argv)
|
||||
|
||||
// Instantiate gem5:
|
||||
Gem5SimControlDRAMsys sim_control(gem5ConfigFile);
|
||||
#if 1 //If only one gem5 port is used
|
||||
Gem5SystemC::Gem5SlaveTransactor transactor("transactor", "transactor");
|
||||
|
||||
transactor.socket.bind(dramSys.tSocket);
|
||||
transactor.sim_control.bind(sim_control);
|
||||
#else // If for example two gem5 ports are used:
|
||||
Gem5SystemC::Gem5SlaveTransactor transactor1("transactor1", "transactor1");
|
||||
Gem5SystemC::Gem5SlaveTransactor transactor2("transactor2", "transactor2");
|
||||
|
||||
transactor1.socket.bind(dramSys.tSocket);
|
||||
transactor2.socket.bind(dramSys.tSocket);
|
||||
transactor1.sim_control.bind(sim_control);
|
||||
transactor2.sim_control.bind(sim_control);
|
||||
#endif
|
||||
|
||||
SC_REPORT_INFO("sc_main", "Start of Simulation");
|
||||
|
||||
|
||||
Reference in New Issue
Block a user