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Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system

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This commit is contained in:
Matthias Jung
2017-06-20 00:36:23 +02:00
parent 6ebf9b5ac7 904aef9361
commit 2b332515bc
9 changed files with 43 additions and 37 deletions
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16
DRAMSys/DRAMSys.pro
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@@ -1,8 +1,7 @@
TEMPLATE = subdirs
thermalsim = $$(THERMALSIM)
isEmpty(thermalsim)
{
isEmpty(thermalsim) {
thermalsim = false
}
@@ -19,14 +18,13 @@ SUBDIRS += analyzer/traceAnalyzer.pro
# Check if gem5 is installed:
gem5 = $$(GEM5)
isEmpty(gem5)
{
DEFINES += DRAMSYS_GEM5
}
contains(DEFINES,DRAMSYS_GEM5)
{
isEmpty(gem5) {
message(GEM5 environment variable not found)
message(Gem5 Simulation Disabled)
} else {
message(Gem5 Simulation Feature Enabled)
message(Gem5 home is $${gem5})
DEFINES += DRAMSYS_GEM5
SUBDIRS += gem5/gem5.pro
}

16
DRAMSys/gem5/gem5.pro
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@@ -48,7 +48,7 @@ INCLUDEPATH += ../simulator/src/common/third_party/DRAMPower/src/libdrampower
INCLUDEPATH += $${gem5_root}/build/$${gem5_arch}/
INCLUDEPATH += $${gem5_root}/util/tlm/examples/slave_port
INCLUDEPATH += $${gem5_root}/util/tlm/examples/common
INCLUDEPATH += $${gem5_root}/util/tlm/
INCLUDEPATH += $${gem5_root}/util/tlm/src/
INCLUDEPATH += $${gem5_root}/util/systemc
LIBS += -L$${systemc_home}/lib-$${systemc_target_arch} -lsystemc
@@ -63,13 +63,13 @@ SOURCES += $${gem5_root}/util/systemc/sc_module.cc
SOURCES += $${gem5_root}/util/systemc/stats.cc
SOURCES += $${gem5_root}/util/tlm/examples/common/cli_parser.cc
SOURCES += $${gem5_root}/util/tlm/examples/common/report_handler.cc
SOURCES += $${gem5_root}/util/tlm/master_transactor.cc
SOURCES += $${gem5_root}/util/tlm/sc_master_port.cc
SOURCES += $${gem5_root}/util/tlm/sc_slave_port.cc
SOURCES += $${gem5_root}/util/tlm/slave_transactor.cc
SOURCES += $${gem5_root}/util/tlm/sc_ext.cc
SOURCES += $${gem5_root}/util/tlm/sc_mm.cc
SOURCES += $${gem5_root}/util/tlm/sim_control.cc
SOURCES += $${gem5_root}/util/tlm/src/master_transactor.cc
SOURCES += $${gem5_root}/util/tlm/src/sc_master_port.cc
SOURCES += $${gem5_root}/util/tlm/src/sc_slave_port.cc
SOURCES += $${gem5_root}/util/tlm/src/slave_transactor.cc
SOURCES += $${gem5_root}/util/tlm/src/sc_ext.cc
SOURCES += $${gem5_root}/util/tlm/src/sc_mm.cc
SOURCES += $${gem5_root}/util/tlm/src/sim_control.cc
SOURCES += main.cpp

11
DRAMSys/simulator/library.pro
View File

@@ -28,6 +28,17 @@ $$eval(dramsys_pct) {
DEFINES += DRAMSYS_PCT
}
# Check if gem5 should be used
gem5 = $$(GEM5)
isEmpty(gem5) {
message(GEM5 environment variable not found)
message(Gem5 Simulation Disabled)
} else {
message(Gem5 Simulation Feature Enabled)
message(Gem5 home is $${gem5})
DEFINES += DRAMSYS_GEM5
}
message(SystemC home is $${systemc_home})
systemc_target_arch = $$(SYSTEMC_TARGET_ARCH)

1
DRAMSys/simulator/resources/configs/simulator/ddr3-single-device.xml
View File

@@ -11,5 +11,4 @@
<NumberOfDevicesOnDIMM value = "8" />
<CheckTLM2Protocol value = "0" />
<AddressOffset value = "0" />
<gem5 value = "0" />
</simconfig>

4
DRAMSys/simulator/resources/configs/simulator/ddr3.xml
View File

@@ -11,11 +11,9 @@
<NumberOfDevicesOnDIMM value = "8" />
<CheckTLM2Protocol value = "0" />
<AddressOffset value = "0" />
<gem5 value = "0" />
<!-- Gem5 Related Configuration:
In the memory controller file the storage mode should be set to Store
E.g. the DRAM is located at 0x80000000 for gem5
<AddressOffset value = "214748364c8" />
<gem5 value = "1" />
<AddressOffset value = "2147483648" />
-->
</simconfig>

11
DRAMSys/simulator/src/controller/core/ControllerCore.cpp
View File

@@ -160,11 +160,16 @@ void ControllerCore::scheduleRequest(Command command, tlm::tlm_generic_payload &
sc_time start = clkAlign(sc_time_stamp());
state->cleanUp(start);
ScheduledCommand scheduledCommand = schedule(command, start, payload);
if(!((command == Command::Precharge || command == Command::Activate)
&& refreshManager->hasCollision(scheduledCommand)))
{
if (config.ControllerCoreDisableRefresh == true) {
state->change(scheduledCommand);
controller.send(scheduledCommand, payload);
} else {
if(!((command == Command::Precharge || command == Command::Activate)
&& refreshManager->hasCollision(scheduledCommand)))
{
state->change(scheduledCommand);
controller.send(scheduledCommand, payload);
}
}
}

6
DRAMSys/simulator/src/controller/core/configuration/Configuration.cpp
View File

@@ -190,11 +190,13 @@ void Configuration::setParameter(std::string name, std::string value)
SC_REPORT_FATAL("Configuration", ("Invalid value for parameter " + name + ". This parameter must be at least one.").c_str());
} else
NumberOfDevicesOnDIMM = string2int(value);
else if(name == "gem5")
gem5 = string2bool(value);
else if(name == "AddressOffset")
{
#ifdef DRAMSYS_GEM5
AddressOffset = string2ull(value);
#else
AddressOffset = 0;
#endif
cout << "Address Offset: " << AddressOffset << endl;
}
else if(name == "CheckTLM2Protocol")

1
DRAMSys/simulator/src/controller/core/configuration/Configuration.h
View File

@@ -81,7 +81,6 @@ struct Configuration
bool SimulationProgressBar = false;
unsigned int NumberOfDevicesOnDIMM = 1;
bool CheckTLM2Protocol = false;
bool gem5 = false;
unsigned long long int AddressOffset = 0;
// MemSpec (from DRAM-Power XML)

14
DRAMSys/simulator/src/simulation/Dram.h
View File

@@ -390,11 +390,8 @@ struct Dram : sc_module
}
else if (phase == BEGIN_WR)
{
#ifndef DRAMSYS_PCT
if(Configuration::getInstance().gem5 == false)
{
assert(payload.get_data_length() == bytesPerBurst);
}
#if !defined (DRAMSYS_PCT) && !defined (DRAMSYS_GEM5)
assert(payload.get_data_length() == bytesPerBurst);
#endif
if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::WR, bank, cycle);}
@@ -418,11 +415,8 @@ struct Dram : sc_module
}
else if (phase == BEGIN_RD)
{
#ifndef DRAMSYS_PCT
if(Configuration::getInstance().gem5 == false)
{
assert(payload.get_data_length() == bytesPerBurst);
}
#if !defined (DRAMSYS_PCT) && !defined (DRAMSYS_GEM5)
assert(payload.get_data_length() == bytesPerBurst);
#endif
numberOfTransactionsServed++;