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7a8633d36e
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Implement stack ID for HBM3
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2025-01-13 15:36:05 +01:00 |
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Lukas Steiner
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123574ab6d
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Update README.md
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2024-12-17 14:48:14 +00:00 |
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703ee81d7e
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Introduce SimulationTime config
Use SimulationTime to forcefully stop simulation at a specified point in
time.
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2024-12-10 10:04:59 +01:00 |
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007b273760
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Add a DDR4 json example that defines everything in one single JSON
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2024-11-18 14:05:52 +01:00 |
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0ec6ea79ad
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Migrate from clkMhz to tCK entry in memspecs
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2024-02-23 12:04:22 +01:00 |
|
Lukas Steiner
|
027b6495e3
|
Update README.md
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2024-01-31 09:33:00 +00:00 |
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ea4e6fa33e
|
Update Git LFS to not track .stl files in config
|
2023-10-27 11:50:14 +02:00 |
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c27ebb6c64
|
Fix gem5 integration issues
|
2023-08-31 09:34:35 +02:00 |
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b30df49d67
|
Use tCCDMW for masked write in LPDDR4
|
2023-08-21 09:26:05 +02:00 |
|
Lukas Steiner
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e389474139
|
Remove deprecated gem5 files.
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2023-05-23 14:53:06 +02:00 |
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156c558e32
|
Resize sample HBM3 memspec and address mapping to 8 Gib
|
2023-04-21 11:14:41 +02:00 |
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85f944fe58
|
Rename RAACDR to RAADEC
|
2023-04-21 11:10:09 +02:00 |
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ad4277c0ee
|
Enable DatabaseRecording by default again
|
2023-04-14 11:11:40 +02:00 |
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b343ea821f
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Refactor Configuration and add warnings when invalid values are provided
|
2023-04-13 11:21:37 +02:00 |
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1f161b412f
|
Update documentation
|
2023-04-13 11:21:36 +02:00 |
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a49afa40eb
|
Use key "addressmapping" instead of "CONGEN" in addressmapping configs
|
2023-04-13 11:21:36 +02:00 |
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949cf944bc
|
Update tCCD_M timings in memspecs for DDR5
|
2023-04-11 14:27:26 +02:00 |
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49954df6ee
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Add tCCD_M DDR5 timings, MemSpecs still incomplete
|
2023-04-06 10:38:48 +02:00 |
|
Lukas Steiner
|
b086fa985d
|
Change names of LPDDR5 timings from tRCDRD/tRCDWR to tRCD_L/tRCD_S.
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2023-03-30 15:06:17 +02:00 |
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5d7171e537
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Add LPDDR5X configurations and separate tRCD into tRCDRD and tRCDWR
|
2023-03-29 16:49:15 +02:00 |
|
Lukas Steiner
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c4ca3d71d7
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Reorganize config files, remove unused config.
|
2023-02-23 17:02:21 +01:00 |
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