Éder Ferreira Zulian
6ee652bdca
Typo fixed (PowerAnalysys --> PowerAnalysis)
2015-05-08 15:55:27 +02:00
Éder Ferreira Zulian
b3c5bf12b0
Directory dram-power-original removed from repository.
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Its content was a duplicate of "dram.vp.system/dram/src/common/third_party/DRAMPower/memspecs".
2015-05-08 14:18:50 +02:00
Éder Ferreira Zulian
19d682c0ca
Typo fixed (PowerAnalysys --> PowerAnalysis)
2015-05-08 14:04:59 +02:00
Éder Ferreira Zulian
cd8aeebe6f
Created an enumeration to the possible values of storage mode.
2015-05-08 12:52:49 +02:00
Éder Ferreira Zulian
fd371795c7
Using relative paths instead of absolute paths in configuration files
2015-05-06 11:33:58 +02:00
Éder Ferreira Zulian
16cbd15f47
Readme file updated with information about dramSys configuration
2015-05-06 10:51:07 +02:00
Éder Ferreira Zulian
41993d87b5
Segfalut caused by misuse of sc_assert() fixed.
2015-04-27 14:36:09 +02:00
Éder Ferreira Zulian
18025343cd
Warnings eliminated.
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Variables initialized.
Variables removed with small changes in the code accordingly.
Some warnings suppressed with __attribute__((unused)).
2015-04-24 11:20:44 +02:00
Éder Ferreira Zulian
6cf6c6be95
Warnings eliminated.
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Variable surrounded by IFPOW() macro since it is only needed for power simulations.
Unused variable removed.
Warning suppressed with __attribute__((__unused__)). The variable was not
removed because of its type: sc_module_name. It may be useful.
Other changes:
cscope* added to gitignore.
2015-04-24 09:11:25 +02:00
Éder Ferreira Zulian
ce7f85c3e1
Some fixes after review.
2015-04-21 16:54:07 +02:00
Éder Ferreira Zulian
5898be7c67
Text enhanced
2015-04-21 16:08:22 +02:00
Éder Ferreira Zulian
378544be26
Minor changes in text
2015-04-21 16:03:40 +02:00
Éder Ferreira Zulian
1cb13725e2
Text enhanced.
2015-04-21 15:58:28 +02:00
Éder Ferreira Zulian
ffb8f38a9a
Added more information about configuration files.
2015-04-21 15:51:07 +02:00
Éder Ferreira Zulian
ed4b406954
Readme file improved but not yet finished.
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Added *.swp (vim swap files extension) to gititnore.
2015-04-21 14:41:14 +02:00
Éder Zulian
381a26fed7
fixed hardcoded configuration in main.cpp
2015-04-21 11:24:19 +02:00
Matthias Jung
5cd24dc0fd
Merge branch 'ehses-master'
2015-04-09 10:33:54 +02:00
Matthias Jung
e1a7f1a0a5
removed namespace core
2015-04-09 10:33:25 +02:00
Matthias Jung
7f67a82287
added error model to the configs
2015-04-09 10:33:02 +02:00
Matthias Jung
0f8ad59a1e
Merge branch 'master' of https://git.rhrk.uni-kl.de/ehses/dram.vp.system into ehses-master
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Conflicts:
dram/dramSys/dramSys.pro
2015-04-09 10:32:06 +02:00
Matthias Jung
268e839472
small changes in the metrics
2015-04-09 10:07:30 +02:00
Peter Ehses
2a587436d9
Fixed small bug
2015-04-09 10:01:27 +02:00
Peter Ehses
ce86b532c3
small changes and comments
2015-03-25 14:21:37 +01:00
Matthias Jung
836bacc76f
fixed overflow bug in StlPlayer
2015-03-23 13:40:24 +01:00
Robert Gernhardt
5fcd57a4e2
Fixed error in refresh manager and in backpressure release codepath
2015-03-23 08:45:25 +01:00
root
fe8ff6242d
bugfix of robert deadlock?
2015-02-23 17:12:17 +01:00
root
a5492a84d8
Merge branch 'master' of https://git.rhrk.uni-kl.de/EIT-Wehn/dram.vp.system
2015-02-17 22:48:10 +01:00
root
cffd844aaf
removed space
2015-02-17 22:46:31 +01:00
Matthias Jung
51f9a7f53f
test for in order check
2015-02-17 22:45:20 +01:00
Matthias Jung
aa615dae63
Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system
2015-02-17 21:52:39 +01:00
Matthias Jung
c9a01d9a33
added better metric for utilisation
2015-02-17 21:50:15 +01:00
gernhard2
beddeccb64
Fixed bug in Fifostrict that caused deadlock
2015-02-17 09:22:58 +01:00
gernhard2
f11adf51dc
Relocated the python scripts. They now live in the analyzer directory and are deployed to the output folder when building the analyzer.
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Major change to simulation logic in dramSys: Commands in a transaction are now scheduled one at a time, instead of
scheduling a whole transaction at once. Since single commands (e.g. Pre or Act) are not that long, refreshes are allowed to be delayed
to allow a command to finsh. Consequently, the whole loop in the ControllerCore about trying to scheduleding a transaction and aborting it when
it collides with a refresh could be ommitted. Lastly, Fifo_Strict has been added, which is a Fifo Scheduler that forces the read and write transactions, even
between different banks to be executed in order. Fifo and FR_FCFS have been modified to fit into the new scheduling logic.
2015-02-16 08:21:27 +01:00
Peter Ehses
571e717224
removed some errors
2014-12-02 16:05:13 +01:00
Peter Ehses
e84a3cc99b
Merge branch 'master' of https://git.rhrk.uni-kl.de/ehses/dram.vp.system
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Conflicts:
dram/dramSys/dramSys.pro
dram/resources/configs/amconfigs/am_wideio.xml
dram/resources/configs/memconfigs/fr_fcfs.xml
dram/src/common/xmlAddressdecoder.cpp
dram/src/controller/core/configuration/ConfigurationLoader.cpp
dram/src/simulation/Simulation.cpp
dram/src/simulation/Simulation.h
dram/src/simulation/TracePlayer.h
2014-12-02 15:25:48 +01:00
ehses
8ec02d3f2c
Merge pull request #1 from EIT-Wehn/master
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Error Model
2014-12-02 14:50:13 +01:00
Peter Ehses
905e75ca32
included errormodel which is presented in DATE paper
2014-12-02 14:44:46 +01:00
Janik Schlemminger
badcc37118
debug bums raus
2014-10-08 21:12:01 +02:00
Janik Schlemminger
f35cc43186
gute frage^^
2014-10-08 21:04:44 +02:00
Peter Ehses
a366ed8f91
easy error model from patrick implemented
2014-09-16 10:27:14 +02:00
Janik Schlemminger
e105d54045
added fix for bankgroups and ranks in addressdecoder
2014-09-10 16:10:07 +02:00
Janik Schlemminger
5a7efb4d88
merged
2014-09-08 15:03:10 +02:00
Janik Schlemminger
6ce8935097
fix on fifo hack
2014-09-08 14:59:28 +02:00
Matthias Jung
9fb90e9015
Experimantal change for a big FIFO
2014-09-08 13:09:52 +02:00
Janik Schlemminger
33a13d6bfd
status quo .. jetzt wirds tricky
2014-09-07 00:04:19 +02:00
Janik Schlemminger
938dbb3fdb
print mapping
2014-09-06 20:21:43 +02:00
Janik Schlemminger
30b1fbbd0c
added no powerdown option
2014-09-06 16:59:46 +02:00
Matthias Jung
e110d45e0e
Added Zoom by keys - and +
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Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system
Conflicts:
dram/src/simulation/SimulationManager.cpp
2014-09-06 01:16:13 +02:00
Janik Schlemminger
2aa07bbbe6
Quick and Dirty XML - Refactoring necessary
2014-09-04 23:35:54 +02:00
Matthias Jung
8d864afb44
Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system
2014-09-04 15:35:30 +02:00