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This commit is contained in:
Thomas Fehmel
2016-10-18 14:21:45 +02:00
commit 657a54ba18
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.gitignore vendored Normal file
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### TEX Temps
*.out
*.toc
*.aux
*.log
*.pdf
*.synctex.gz
*.lof
*.lot
*.lol
*.dvi
*.bbl
*.ps
*.blg
*.loc
*.pyg
### Other Files
*~
*.kate-swp
*.patch
*.orig
### Assembler Eclipse Stuff
assembler/.cproject
assembler/.project
assembler/.settings/org.eclipse.cdt.managedbuilder.core.prefs
### Assembler Project Compiles
assembler/obj/*
assembler/asm
assembler/test.ram
assembler/test.map
### test program files
*.ram
*.map

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As of the time of the year 2015, intellectual property ownership of the processor core LT16x32,
its software assembler, the documentation and as well as the various components comprising
the LT16 system on chip lies with the Electronics Design Automation Group, University of Kaiserlsautern, Germany (henceforth the "Owner").
The Owner grants the following rights free of charge:
* duplication
* modification, and
* use
for private, educational and academic purposes.
To obtain the following rights, the Owner needs to be contacted and explicit permission granted:
* redistribution
* republishing
of the original or modified work for commercial, academic or educational purposes, and
* use
for commercial puposes and applications.
In all cases mentioned above, the orginal author's notices and license must be kept in place and redistributed with any copies made.
Contact the original authors first in case of doubt to ensure your intended use does not violate this license or get explicit permission to use it in a way not covered or prohibited by this license.

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Setup
The following Instruction apply if you are intending to build the toolchain for the LT16x32 and associated SoC, and want to create a synthesized bitfile of said SoC.
It is assumed that:
* you run linux
* have make installed
* have gcc, flex and bison installed
* have inkscape installed
* have all required latex packages installed (install texlive-latex-extra metapackage for ubuntu/Debian)
** packages for openSUSE: texlive-latex,texlive-multirow,texlive-lineno
* pygmetize for minted source code, (python-pygments package in ubuntu/Debian/openSuse)
1. Making of...
1.1 the assembler
Change into the 'assembler' directory and run the Makefile with
$ make all
The LT16x32 assembler should then be present as 'asm' binary executeable.
To integrate this executeable, create a symbolic link in a user directory which exists in your $PATH or directly link to it.
1.2 the documentation
Change into the 'documentation' directory and run the Makefile with
$ make all
A file named 'soc.pdf' should then pop up and be placed in the documentation directory.
It contains information about the the LT16x32 core and assembler.

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################################################################################
# Automatically-generated file. Do not edit!
################################################################################
-include ../makefile.init
RM := rm -rf
CC = gcc -g
IDIR=inc
ODIR=obj
SDIR=src
CFLAGS = -Wall
_DEPS = command.h files.h labels.h
DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS))
_OBJS = output.o msg.o check.o label.o main.o handle_o.o handle_oi.o handle_omi.o handle_omr.o handle_omr2.o handle_or2.o handle_or2i.o handle_or3.o handle_ori.o handle_or.o handle_om.o
OBJS = $(patsubst %,$(ODIR)/%,$(_OBJS))
_FLEX_OBJ = asm.tab.o lex.yy.o
FLEX_OBJS = $(patsubst %,$(ODIR)/%,$(_FLEX_OBJ))
_FLEX_COMPILES = asm.tab.c asm.tab.h lex.yy.c
FLEX_COMPILES = $(patsubst %,$(ODIR)/%,$(_FLEX_COMPILES))
# All Target
all: $(ODIR) asm
$(ODIR):
mkdir -p $(ODIR)
# Tool invocations
asm: flex bison $(FLEX_OBJS) $(OBJS)
@echo 'Building target: $@'
@echo 'Invoking: GCC C Linker'
$(CC) -o "asm" -I"inc/" $(OBJS) $(FLEX_OBJS) $(CFLAGS)
@echo 'Finished building target: $@'
@echo ' '
bison: $(SDIR)/asm.y
bison -o obj/asm.tab.c -d $(SDIR)/asm.y
flex: $(SDIR)/asm.l
flex -o obj/lex.yy.c $(SDIR)/asm.l
# Object Files
#obj/%.o: src/%.c $(DEPS)
# $(CC) -c -o $@ $< $(CFLAGS)
obj/asm.tab.c: bison
obj/asm.tab.h: bison
obj/lex.yy.c : flex
$(ODIR)/output.o: $(SDIR)/output.c
$(CC) -c $(CFLAGS) -o $@ $<
$(ODIR)/msg.o: $(SDIR)/msg.c
$(CC) -c $(CFLAGS) -o $@ $<
$(ODIR)/check.o: $(SDIR)/check.c
$(CC) -c $(CFLAGS) -o $@ $<
$(ODIR)/main.o: $(SDIR)/main.c
$(CC) -c -o $@ $< $(CFLAGS)
$(ODIR)/label.o: $(SDIR)/label.c
$(CC) -c $(CFLAGS) -o $@ $<
$(ODIR)/handle_or3.o: $(SDIR)/handle_or3.c
$(CC) -c -o $@ $< $(CFLAGS)
$(ODIR)/handle_or2i.o: $(SDIR)/handle_or2i.c
$(CC) -c -o $@ $< $(CFLAGS)
$(ODIR)/handle_ori.o: $(SDIR)/handle_ori.c
$(CC) -c -o $@ $< $(CFLAGS)
$(ODIR)/handle_omr2.o: $(SDIR)/handle_omr2.c
$(CC) -c -o $@ $< $(CFLAGS)
$(ODIR)/handle_omi.o: $(SDIR)/handle_omi.c
$(CC) -c -o $@ $< $(CFLAGS)
$(ODIR)/handle_omr.o: $(SDIR)/handle_omr.c
$(CC) -c -o $@ $< $(CFLAGS)
$(ODIR)/handle_oi.o: $(SDIR)/handle_oi.c
$(CC) -c -o $@ $< $(CFLAGS)
$(ODIR)/handle_o.o: $(SDIR)/handle_o.c
$(CC) -c -o $@ $< $(CFLAGS)
$(ODIR)/handle_or2.o: $(SDIR)/handle_or2.c
$(CC) -c -o $@ $< $(CFLAGS)
$(ODIR)/handle_or.o: $(SDIR)/handle_or.c
$(CC) -c -o $@ $< $(CFLAGS)
$(ODIR)/handle_om.o: $(SDIR)/handle_om.c
$(CC) -c -o $@ $< $(CFLAGS)
$(ODIR)/asm.tab.o: $(ODIR)/asm.tab.c
$(CC) -c -o $@ $< $(CFLAGS)
$(ODIR)/lex.yy.o: $(ODIR)/lex.yy.c
$(CC) -c -o $@ $< $(CFLAGS)
# Other Targets
clean:
-$(RM) $(OBJS) $(FLEX_OBJS) $(FLEX_COMPILES) asm
-@echo ' '
.PHONY: all clean dependents
.SECONDARY:
-include ../makefile.targets

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/*
* This file declares functions for
* - checking instruction parameters for their validity
*/
#ifndef CHECK_H_
#define CHECK_H_
/*
* returns a valid register number or throws error if r out of range
* r: number of register to be checked
*/
int reg(int r);
/*
* returns a valid 8bit signed value or throws error if imm out of range
* imm: immediate to be checked
*/
int signed8(int imm);
/*
* returns a valid 4bit unsigned value or throws error if imm out of range
* imm: immediate to be checked
*/
int unsigned4(int imm);
/*
* returns a valid 32bit signed value or throws error if imm out of range
* imm: immediate to be checked
*/
int word(int imm);
#endif /* CHECK_H_ */

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/*
* This file
* - defines globally used constants
* - defines enum types
* - declares globally used variables
*/
#ifndef GLOBAL_H_
#define GLOBAL_H_
#include <stdio.h>
// maximal filename length
#define MAX_FILENAME_LENGTH (128);
// nop instruction for 16bit
#define nop16 (0b0000000000000000)
// number of link register
#define lr_num (13)
// all supported modes
typedef enum {
mode_eq, mode_neq, mode_ge, mode_gg, mode_le, mode_ll,
mode_cond_true, mode_cond_unconditional
} opmode_t;
// all supported (pseudo) instructions and directives
typedef enum {
op_add, op_sub, op_and, op_or, op_xor, op_lsh, op_rsh, op_addi,
op_cmp, op_ssr,
op_ldr, op_ld08, op_ld16, op_ld32, op_st08, op_st16, op_st32,
op_brt, op_br, op_call, op_trap, op_reti,
op_tst,
op_mov, op_nop, op_ret, op_clr,
op_word, // used for direct placement of words (=32 bit)
op_addr, // used for setting of current address (forward movement only)
op_align, // used for aligning next instruction/immediate value
} op_t;
// input file
extern FILE* f_in;
// output file
extern FILE* f_out;
// map file, 0 if unused
extern FILE* f_map;
// input filename
char* inputfile;
// do verbose output, boolean value
int verbose;
// automatically align 32bit instructions, boolean value
int autoalign;
// fill branch delay slot with nop, boolean value
int fillbds;
// continue even after error, boolean value
int continueonerror;
// error has happened in first run, boolean value
int errorhappened;
// buffer of the currently parsed line
char linebuf[500];
/* in first run, boolean value
* 1 if in first run
* 0 if in second run
*/
int isfirstrun;
// current address (byte address)
int address;
// destructor, closes programs and cleans up memory
// exitvalue: value for exit
void destruct();
#endif /* GLOBAL_H_ */

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/*
* This file declares functions for
* - handling of instructions
*/
#ifndef HANDLE_H_
#define HANDLE_H_
#include "global.h"
/*
* outputs instruction to output for instructions width or3 instruction type
* opcode: opcode of instruction
* r1: register 1
* r2: register 2
* r3: register 3
*/
void handle_or3(op_t opcode, int r1, int r2, int r3);
/*
* outputs instruction to output for instructions width ori instruction type
* opcode: opcode of instruction
* r1: register 1
* imm: immediate
*/
void handle_ori(op_t opcode, int r1, int imm);
/*
* outputs instruction to output for instructions width omr2 instruction type
* opcode: opcode of instruction
* mode: mode of instruction
* r1: register 1
* r2: register 2
*/
void handle_omr2(op_t opcode, opmode_t mode, int r1, int r2);
/*
* outputs instruction to output for instructions width omi instruction type
* opcode: opcode of instruction
* mode: mode of instruction
* imm: immediate
*/
void handle_omi(op_t opcode, opmode_t mode, int imm);
/*
* outputs instruction to output for instructions width omr instruction type
* opcode: opcode of instruction
* mode: mode of instruction
* r1: register 1
*/
void handle_omr(op_t opcode, opmode_t mode, int r1);
/*
* outputs instruction to output for instructions width oi instruction type
* opcode: opcode of instruction
* mode: mode of instruction
* imm: immediate
*/
void handle_oi(op_t opcode, int imm);
/*
* outputs instruction to output for instructions width o instruction type
* opcode: opcode of instruction
*/
void handle_o(op_t opcode);
/*
* outputs instruction to output for instructions width or instruction type
* opcode: opcode of instruction
* r1: register 1
*/
void handle_or(op_t opcode, int r1);
/*
* outputs instruction to output for instructions width or2 instruction type
* opcode: opcode of instruction
* r1: register 1
* r2: register 2
*/
void handle_or2(op_t opcode, int r1, int r2);
/*
* outputs instruction to output for instructions width or2i instruction type
* opcode: opcode of instruction
* mode: mode of instruction
* r1: register 1
* r2: register 2
* imm: immediate
*/
void handle_or2i(op_t opcode, int r1, int r2, int imm);
/*
* outputs instruction to output for instructions width om instruction type
* opcode: opcode of instruction
* mode: mode of instruction
*/
void handle_om(op_t opcode, opmode_t mode);
#endif /* HANDLE_H_ */

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/*
* This file declares functions and declares variables for
* - handling of labels
* and defines constants, types.
*/
#ifndef LABEL_H_
#define LABEL_H_
// maximum length of label names
#define LABEL_MAX_NAME_LENGTH (64)
// struct of a label item in list
typedef struct {
// name of the label
char name[LABEL_MAX_NAME_LENGTH];
// address the label points to
int address;
// next item in list
void* next;
} label_t;
// head of list
label_t* label_listhead;
/*
* adds a label to the list
* name: name of the label
* address: address the label points to
*/
void label_add(char* name, int address);
/*
* returns absolute address of a label
* name: name of the label
* return: absolute address of label or -1 if label not found
*/
int label_absolute(char* name);
/*
* returns relative address of a label
* name: name of the label
* return: relative address of label or -1 if label not found
*/
int label_relative(char* name);
/*
* frees the allocated space used for the list of labels
*/
void label_free();
#endif /* LABEL_H_ */

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/*
* This file declares functions for
* - checking instruction parameters for range
*/
#ifndef MSG_H_
#define MSG_H_
/*
* verbose output (if flag is set)
* msg: verbose message
*/
void yyverbose(char* msg);
/*
* error handler
* msg: error message
*/
void yyerror(char* msg);
#endif /* MSG_H_ */

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/*
* This file declares functions for
* - writing to output file
* - writing to map file
*/
#ifndef OUTPUT_H_
#define OUTPUT_H_
/*
* outputs a number of length bits, given in instr to the output stream and inserts a linebreak after each 32bit
* instr: number to be printed
* length: number of bits to be printed
*/
void output_instr(int instr, int length);
/*
* outputs a number of 16bits and updates address
* instr: number to be printed
*/
void output_instr16(int instr);
/*
* outputs a number of 32bits and updates address
* instr: number to be printed
*/
void output_instr32(int instr);
/*
* outputs a line to the mapfile (if specified and if in first run)
* s: string to be put to mapfile
*/
void output_line(char* s);
#endif /* OUTPUT_H_ */

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%option nodefault yylineno
%{
#include <string.h>
#include "../inc/msg.h"
#include "../inc/label.h"
#include "../inc/global.h"
#include "../inc/output.h"
#include "../obj/asm.tab.h"
void yyerror(char *s);
union yylval {
op_t op;
int i;
};
%}
LABELNAME [_a-zA-Z][_a-zA-Z0-9]*
%%
\n.* { strncpy(linebuf, yytext+1, sizeof(linebuf)); /* save the next line */
yyless(1); /* give back all but the \n to rescan */
output_line(linebuf); return EOL;
}
\r\n.* {
strncpy(linebuf, yytext+2, sizeof(linebuf)); /* save the next line */
yyless(2); /* give back all but the \r\n to rescan */
output_line(linebuf); return EOL;
}
<<EOF>> { yyterminate(); return EOL; }
[ \t] { /* ignore whitespace*/ }
[,] { return ','; }
"//".*$ { /* comment */ }
[r][0-9]+ { yylval.i = atoi(yytext+1); return REGISTER; }
(sp) { yylval.i = 12; return REGISTER; }
(lr) { yylval.i = 13; return REGISTER; }
(sr) { yylval.i = 14; return REGISTER; }
(pc) { yylval.i = 15; return REGISTER; }
[+-]?"0x"?[0-9A-F]+ { yylval.i = strtol(yytext, 0, 0); return IMMEDIATE; }
(add) { yylval.op = op_add; return MNEMONIC; }
(sub) { yylval.op = op_sub; return MNEMONIC; }
(and) { yylval.op = op_and; return MNEMONIC; }
(or) { yylval.op = op_or; return MNEMONIC; }
(xor) { yylval.op = op_xor; return MNEMONIC; }
(lsh) { yylval.op = op_lsh; return MNEMONIC; }
(rsh) { yylval.op = op_rsh; return MNEMONIC; }
(addi) { yylval.op = op_addi; return MNEMONIC; }
(cmp) { yylval.op = op_cmp; return MNEMONIC; }
(ssr) { yylval.op = op_ssr; return MNEMONIC; }
(ldr) { yylval.op = op_ldr; return MNEMONIC; }
(ld08) { yylval.op = op_ld08; return MNEMONIC; }
(ld16) { yylval.op = op_ld16; return MNEMONIC; }
(ld32) { yylval.op = op_ld32; return MNEMONIC; }
(st08) { yylval.op = op_st08; return MNEMONIC; }
(st16) { yylval.op = op_st16; return MNEMONIC; }
(st32) { yylval.op = op_st32; return MNEMONIC; }
(brt) { yylval.op = op_brt; return MNEMONIC; }
(br) { yylval.op = op_br; return MNEMONIC; }
(call) { yylval.op = op_call; return MNEMONIC; }
(trap) { yylval.op = op_trap; return MNEMONIC; }
(reti) { yylval.op = op_reti; return MNEMONIC; }
(tst) { yylval.op = op_tst; return MNEMONIC; }
(mov) { yylval.op = op_mov; return MNEMONIC; }
(nop) { yylval.op = op_nop; return MNEMONIC; }
(ret) { yylval.op = op_ret; return MNEMONIC; }
(clr) { yylval.op = op_clr; return MNEMONIC; }
(\.word) { yylval.op = op_word; return MNEMONIC; }
(\.address) { yylval.op = op_addr; return MNEMONIC; }
(\.align) { yylval.m = op_align; return MNEMONIC; }
(eq) { yylval.m = mode_eq; return MODE; }
(neq) { yylval.m = mode_neq; return MODE; }
(gg) { yylval.m = mode_gg; return MODE; }
(ge) { yylval.m = mode_ge; return MODE; }
(ll) { yylval.m = mode_ll; return MODE; }
(le) { yylval.m = mode_le; return MODE; }
(true) { yylval.m = mode_cond_true; return MODE; }
(always) { yylval.m = mode_cond_unconditional; return MODE; }
{LABELNAME} { strcpy(yylval.s, yytext); return LABEL; }
(\>{LABELNAME}) { yylval.i = label_relative(yytext+1); return IMMEDIATE; }
(\={LABELNAME}) { yylval.i = label_absolute(yytext+1); return IMMEDIATE; }
: { return ':'; }
. { yyerror("unexpected input"); }
%%
int yywrap() { return 1; }

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%{
#include <stdio.h>
#include "../inc/msg.h"
#include "../inc/handle.h"
#include "../inc/label.h"
#include "../inc/global.h"
%}
%union {
int i;
op_t op;
opmode_t m;
char s[32];
}
%token EOL
%token <op> MNEMONIC
%token <m> MODE
%token <i> REGISTER
%token <i> IMMEDIATE
%token <s> LABEL
%%
line:
| line lbldef
| line r3-line EOL
| line r2-line EOL
| line ri-line EOL
| line r2i-line EOL
| line mr2-line EOL
| line mi-line EOL
| line mr-line EOL
| line i-line EOL
| line o-line EOL
| line or-line EOL
| line om-line EOL
| line EOL
| line error-line EOL
;
r3-line: MNEMONIC REGISTER ',' REGISTER ',' REGISTER { handle_or3($1, $2, $4, $6); }
r2-line: MNEMONIC REGISTER ',' REGISTER { handle_or2($1, $2, $4); }
ri-line: MNEMONIC REGISTER ',' IMMEDIATE { handle_ori($1, $2, $4); }
r2i-line: MNEMONIC REGISTER ',' REGISTER ',' IMMEDIATE { handle_or2i($1, $2, $4, $6); }
mr2-line: MNEMONIC MODE REGISTER ',' REGISTER { handle_omr2($1, $2, $3, $5); }
mi-line: MNEMONIC MODE IMMEDIATE { handle_omi($1, $2, $3); }
mr-line: MNEMONIC MODE REGISTER { handle_omr($1, $2, $3); }
i-line: MNEMONIC IMMEDIATE { handle_oi($1, $2); }
o-line: MNEMONIC { handle_o($1); }
or-line: MNEMONIC REGISTER { handle_or($1, $2); }
om-line: MNEMONIC MODE { handle_om($1, $2); }
lbldef: LABEL ':' { label_add($1, address); }
error-line: error { }
%%

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/*
* This file implements functions for
* - checking instruction parameters for their validity
*/
#include <stdio.h>
#include "../inc/msg.h"
#include "../inc/global.h"
/*
* returns a valid register number or throws error if r out of range
* r: number of register to be checked
*/
int reg(int r) {
if ((r >= 0) && (r <= 15)) {
// in valid range
return r;
} else {
// out of valid range
yyerror("register number out of range");
return 0;
}
}
/*
* returns a valid 8bit signed value or throws error if imm out of range
* imm: immediate to be checked
*/
int signed8(int imm) {
if ((imm >= -128) && (imm <= 127)) {
// in valid range
return imm & 0xFF;
} else {
// out of valid range
yyerror(
"immediate value out of bounds. expecting 8bit signed immediate.");
return 0;
}
}
/*
* returns a valid 4bit unsigned value or throws error if imm out of range
* imm: immediate to be checked
*/
int unsigned4(int imm) {
if ((imm >= 0) && (imm <= 15)) {
// in valid range
return imm & 0x0F;
} else {
// out of valid range
yyerror(
"immediate value out of bounds. expecting 4bit unsigned immediate.");
return 0;
}
}
/*
* returns a valid 32bit signed value or throws error if imm out of range
* imm: immediate to be checked
*/
int word(int imm) {
if ((imm >= -2147483648) && (imm <= 2147483647)) {
// in valid range
return imm;
} else {
// out of valid range
yyerror(
"immediate value out of bounds. expecting 32bit signed immediate.");
return 0;
}
}

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/*
* This file implements functions for
* - handling of instructions of type o
*/
#include <stdio.h>
#include "../inc/msg.h"
#include "../inc/output.h"
#include "../inc/check.h"
#include "../inc/global.h"
/*
* outputs instruction to output for instructions width o instruction type
* opcode: opcode of instruction
*/
void handle_o(op_t opcode) {
// instruction to be build
int instr = 0;
switch (opcode) {
case op_reti: // reti instruction
// opcode: bct
instr |= (0b1100) << 12;
// mode: reti
instr |= (0b0000) << 8;
// output instruction
output_instr16(instr);
break;
case op_ret: // return instruction (unconditional)
// model with branch always to lr
// opcode: branch
instr |= (0b1100) << 12;
// mode: to register
instr |= (0b0110) << 8;
// register a: LR
instr |= lr_num << 4;
// output instruction
output_instr16(instr);
// fill branch delay with nop if flag is set
if (fillbds) {
yyverbose("filled branch delay slot with nop.");
output_instr16(nop16);
}
break;
case op_nop: // no operation instruction
// model with or r0, r0, r0
// opcode: or
instr |= (0b0000) << 12;
// all registers: r0
// output instruction
output_instr16(instr);
break;
case op_align: // make address be word-aligned
if ((address % 4) != 0) {
// not word-aligned, insert nop
output_instr16(nop16);
} else {
// already word-aligned, put verbose message
yyverbose("Already aligned, ignoring .align directive.");
}
break;
default: // invalid opcode for o-instruction
yyerror("opcode not compatible with o syntax");
break;
}
}

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assembler/src/handle_oi.c Normal file
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/*
* This file implements functions for
* - handling of instructions of type i
*/
#include <stdio.h>
#include "../inc/msg.h"
#include "../inc/output.h"
#include "../inc/check.h"
#include "../inc/global.h"
/*
* outputs instruction to output for instructions width oi instruction type
* opcode: opcode of instruction
* mode: mode of instruction
* imm: immediate
*/
void handle_oi(op_t opcode, int imm) {
// instruction to be build
int instr = 0;
switch (opcode) {
case op_word: // add immediate word
// immediate word
instr = word(imm);
// output instruction
output_instr32(instr);
break;
case op_addr: // move to new address
if (imm >= address) {
// if new address is larger than current address
while (imm - 2 >= address) {
// add nop until next new address is equal to immediate value
output_instr16(nop16);
}
} else {
// new address smaller than current address
// backward setting of address not possible
yyerror("can't move backwards with .address");
}
break;
case op_trap: // trap instruction
// opcode: bct
instr |= (0b1100) << 12;
// mode: trap
instr |= (0b1100) << 8;
// immediate: irq number
instr |= signed8(imm) << 0;
// output
output_instr16(instr);
break;
case op_br: // branch instruction to immediate (unconditional)
// opcode: bct
instr |= (0b1100) << 12;
// immediate: branch target
instr |= signed8(imm) << 0;
// mode: branch and unconditional to immediate
instr |= (0b0100) << 8;
// output
output_instr16(instr);
// fill branch delay with nop if flag is set
if (fillbds) {
yyverbose("filled branch delay slot with nop.");
output_instr16(nop16);
}
break;
case op_call: // call instruction to immediate (unconditional)
// opcode: bct
instr |= (0b1100) << 12;
// immediate: call target
instr |= signed8(imm) << 0;
// mode: call unconditional to immediate
instr |= (0b1000) << 8;
// output
output_instr16(instr);
break;
default:
// invalid opcode for oi-instruction
yyerror("opcode not compatible with i syntax");
break;
}
}

55
assembler/src/handle_om.c Normal file
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/*
* This file implements functions for
* - handling of instructions of type om
*/
#include <stdio.h>
#include "../inc/msg.h"
#include "../inc/output.h"
#include "../inc/check.h"
#include "../inc/global.h"
/*
* outputs instruction to output for instructions width om instruction type
* opcode: opcode of instruction
* mode: mode of instruction
*/
void handle_om(op_t opcode, opmode_t mode) {
// instruction to be build
int instr = 0;
switch (opcode) {
case op_ret: // return instruction
// model with branch to lr
// opcode: branch
instr |= (0b1100) << 12;
// mode: to register and condition
switch (mode) {
case mode_cond_true: // if true
instr |= (0b0111) << 8;
break;
case mode_cond_unconditional: // always
instr |= (0b0110) << 8;
break;
default: // invalid mode for branch instruction
yyerror("mode invalid for ret instruction.");
}
// register a: LR
instr |= lr_num << 4;
// output instruction
output_instr16(instr);
// fill branch delay with nop if flag is set
if (fillbds) {
yyverbose("filled branch delay slot with nop.");
output_instr16(nop16);
}
break;
default: // invalid opcode for o-instruction
yyerror("opcode not compatible with om syntax");
break;
}
}

74
assembler/src/handle_omi.c Normal file
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/*
* This file implements functions for
* - handling of instructions of type omi
*/
#include <stdio.h>
#include "../inc/msg.h"
#include "../inc/output.h"
#include "../inc/check.h"
#include "../inc/global.h"
/*
* outputs instruction to output for instructions width omi instruction type
* opcode: opcode of instruction
* mode: mode of instruction
* imm: immediate
*/
void handle_omi(op_t opcode, opmode_t mode, int imm) {
// instruction to be build
int instr = 0;
switch (opcode) {
case op_br: // branch instruction to immediate
// opcode: bct
instr |= (0b1100) << 12;
// immediate: branch target
instr |= signed8(imm) << 0;
// mode: branch and (un)conditional to immediate
switch (mode) {
case mode_cond_true: // if true
instr |= (0b0101) << 8;
break;
case mode_cond_unconditional: // always
instr |= (0b0100) << 8;
break;
default: // invalid mode for branch instruction
yyerror("mode invalid for branch instruction.");
}
// output
output_instr16(instr);
// fill branch delay with nop if flag is set
if (fillbds) {
yyverbose("filled branch delay slot with nop.");
output_instr16(nop16);
}
break;
case op_call: // call instruction to immediate
// opcode: bct
instr |= (0b1100) << 12;
// immediate: call target
instr |= signed8(imm) << 0;
// mode: call (un)conditional to immediate
switch (mode) {
case mode_cond_true: // if true
instr |= (0b1001) << 8;
break;
case mode_cond_unconditional: // always
instr |= (0b1000) << 8;
break;
default: // invalid mode for branch instruction
yyerror("mode invalid for call instruction.");
}
// output
output_instr16(instr);
break;
default: // invalid opcode for omi-instruction
yyerror("opcode not compatible with mi syntax");
break;
}
}

100
assembler/src/handle_omr.c Normal file
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/*
* This file implements functions for
* - handling of instructions of type omr
*/
#include <stdio.h>
#include "../inc/msg.h"
#include "../inc/output.h"
#include "../inc/check.h"
#include "../inc/global.h"
/*
* outputs instruction to output for instructions width omr instruction type
* opcode: opcode of instruction
* mode: mode of instruction
* r1: register 1
*/
void handle_omr(op_t opcode, opmode_t mode, int r1) {
// instruction to be build
int instr = 0;
switch (opcode) {
case op_brt: // branch to table instruction
// opcode: branch to table
instr |= (0b1100) << 12;
// register a: branch target register
instr |= reg(r1) << 4;
// mode: branch to table (un)conditional to register
switch (mode) {
case mode_cond_true: // if true
instr |= (0b0011) << 8;
break;
case mode_cond_unconditional: // always
instr |= (0b0010) << 8;
break;
default: // invalid mode for branch to table instruction
yyerror("mode invalid for branch to table instruction.");
}
// output
output_instr16(instr);
// fill branch delay with nop if flag is set
if (fillbds) {
yyverbose("filled branch delay slot with nop.");
output_instr16(nop16);
}
break;
case op_br: // branch instruction to register
// opcode: bct
instr |= (0b1100) << 12;
// register a: branch target register
instr |= reg(r1) << 4;
// mode: branch to table (un)conditional to register
switch (mode) {
case mode_cond_true: // if true
instr |= (0b0111) << 8;
break;
case mode_cond_unconditional: // always
instr |= (0b0110) << 8;
break;
default: // invalid mode for branch instruction
yyerror("mode invalid for branch instruction.");
}
// output
output_instr16(instr);
// fill branch delay with nop if flag is set
if (fillbds) {
yyverbose("filled branch delay slot with nop.");
output_instr16(nop16);
}
break;
case op_call: // call instruction to register
// opcode: bct
instr |= (0b1100) << 12;
// register a: call target
instr |= reg(r1) << 4;
// mode: call (un)conditional to register
switch (mode) {
case mode_cond_true: // if true
instr |= (0b1011) << 8;
break;
case mode_cond_unconditional: // always
instr |= (0b1010) << 8;
break;
default: // invalid mode for call instruction
yyerror("mode invalid for call instruction.");
}
// output
output_instr16(instr);
break;
default: // invalid opcode for omr-instruction
yyerror("opcode not compatible with mr syntax");
break;
}
}

64
assembler/src/handle_omr2.c Normal file
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/*
* This file implements functions for
* - handling of instructions of type omr2
*/
#include <stdio.h>
#include "../inc/msg.h"
#include "../inc/output.h"
#include "../inc/check.h"
#include "../inc/global.h"
/*
* outputs instruction to output for instructions width omr2 instruction type
* opcode: opcode of instruction
* mode: mode of instruction
* r1: register 1
* r2: register 2
*/
void handle_omr2(op_t opcode, opmode_t mode, int r1, int r2) {
// instruction to be build
int instr = 0;
switch (opcode) {
case op_cmp: // compare instruction
// opcode: compare
instr |= (0b1000) << 12;
// register a: first register
instr |= r1 << 4;
// register b: second register
instr |= r2 << 0;
// mode
switch (mode) {
case mode_eq: // equal
instr |= (0b0000) << 8;
break;
case mode_neq: // not equal
instr |= (0b1000) << 8;
break;
case mode_gg: // greater than
instr |= (0b0010) << 8;
break;
case mode_ge: // greater than or equal
instr |= (0b0001) << 8;
break;
case mode_ll: // less than
instr |= (0b1001) << 8;
break;
case mode_le: // less than or equal
instr |= (0b1010) << 8;
break;
default: // invalid mode for compare instruction
yyerror("mode invalid for call instruction.");
break;
}
// output
output_instr16(instr);
break;
default: // invalid opcode for omr2-instruction
yyerror("opcode not compatible with omr2 syntax");
break;
}
}

39
assembler/src/handle_or.c Normal file
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/*
* This file implements functions for
* - handling of instructions of type or
*/
#include <stdio.h>
#include "../inc/msg.h"
#include "../inc/output.h"
#include "../inc/check.h"
#include "../inc/global.h"
/*
* outputs instruction to output for instructions width or instruction type
* opcode: opcode of instruction
* r1: register 1
*/
void handle_or(op_t opcode, int r1) {
// instruction to be build
int instr = 0;
switch (opcode) {
case op_clr: // clear register, model as xor r1, r1, r1
// opcode: cor
instr |= (0b0100) << 12;
// register d: register 1
instr |= reg(r1) << 8;
// register a: register 1
instr |= reg(r1) << 4;
// register b: register 1
instr |= reg(r1) << 0;
// output
output_instr16(instr);
break;
default: // invalid opcode for or-instruction
yyerror("opcode not compatible with or syntax");
break;
}
}

130
assembler/src/handle_or2.c Normal file
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/*
* This file implements functions for
* - handling of instructions of type or2
*/
#include <stdio.h>
#include "../inc/msg.h"
#include "../inc/output.h"
#include "../inc/check.h"
#include "../inc/global.h"
/*
* outputs instruction to output for instructions width or2 instruction type
* opcode: opcode of instruction
* r1: register 1
* r2: register 2
*/
void handle_or2(op_t opcode, int r1, int r2) {
// instruction to be build
int instr = 0;
switch (opcode) {
case op_mov: // move instruction, model with or r1, r2, r2
// opcode: or
instr |= (0b0000) << 12;
// register d: register 1
instr |= reg(r1) << 8;
// register a: register 2
instr |= reg(r2) << 4;
// register b: register 2
instr |= reg(r2) << 0;
// output
output_instr16(instr);
break;
case op_ld08: // load byte instruction
// opcode: mem
instr |= (0b1011) << 12;
// mode: load byte
instr |= (0b0000) << 8;
// register a: register 1
instr |= reg(r1) << 4;
// register b: register 2
instr |= reg(r2) << 0;
// output
output_instr16(instr);
break;
case op_ld16: // load halfword
// opcode: mem
instr |= (0b1011) << 12;
// mode: load halfword
instr |= (0b0001) << 8;
// register a: register 1
instr |= reg(r1) << 4;
// register b: register 2
instr |= reg(r2) << 0;
// output
output_instr16(instr);
break;
case op_ld32: // load word
// opcode: mem
instr |= (0b1011) << 12;
// mode: load word
instr |= (0b0010) << 8;
// register a: register 1
instr |= reg(r1) << 4;
// register b: register 2
instr |= reg(r2) << 0;
// output
output_instr16(instr);
break;
case op_st08: // store byte
// opcode: mem
instr |= (0b1011) << 12;
// mode: store byte
instr |= (0b1000) << 8;
// register a: register 1
instr |= reg(r1) << 4;
// register b: register 2
instr |= reg(r2) << 0;
// output
output_instr16(instr);
break;
case op_st16: // store halfword
// opcode: mem
instr |= (0b1011) << 12;
// mode: store halfword
instr |= (0b1001) << 8;
// register a: register 1
instr |= reg(r1) << 4;
// register b: register 2
instr |= reg(r2) << 0;
// output
output_instr16(instr);
break;
case op_st32: // store word
// opcode: mem
instr |= (0b1011) << 12;
// mode: store word
instr |= (0b1010) << 8;
// register a: register 1
instr |= reg(r1) << 4;
// register b: register 2
instr |= reg(r2) << 0;
// output
output_instr16(instr);
break;
case op_tst: // test and set
// opcode: test and set instruction
instr |= (0b1001) << 12;
// register d: register 1
instr |= reg(r1) << 8;
// register a: register 2
instr |= reg(r2) << 4;
// output
output_instr16(instr);
break;
default: // invalid opcode for ri-instruction
yyerror("opcode not compatible with ri syntax");
break;
}
}

63
assembler/src/handle_or2i.c Normal file
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/*
* This file implements functions for
* - handling of instructions of type or2i
*/
#include <stdio.h>
#include "../inc/msg.h"
#include "../inc/output.h"
#include "../inc/check.h"
#include "../inc/global.h"
/*
* outputs instruction to output for instructions width or2i instruction type
* opcode: opcode of instruction
* mode: mode of instruction
* r1: register 1
* r2: register 2
* imm: immediate
*/
void handle_or2i(op_t opcode, int r1, int r2, int imm) {
// instruction to be build
int instr = 0;
switch (opcode) {
case op_lsh: // left shift instruction
// immediate must not be 0
if (imm == 0)
yyerror("lsh with immediate=0 not allowed");
// opcode: left shift instruction
instr |= (0b0101) << 12;
// register d: register 1
instr |= reg(r1) << 8;
// register a: register 2
instr |= reg(r2) << 4;
// immediate: imm-1 (+1 in processor)
instr |= unsigned4(imm - 1) << 0;
// output
output_instr16(instr);
break;
case op_rsh: // right shift instruction
// immediate must not be zero
if (imm == 0)
yyerror("rsh with immediate=0 not allowed");
// opcode: right shift instruction
instr |= (0b0110) << 12;
// register d: register 1
instr |= reg(r1) << 8;
// register a: register 2
instr |= reg(r2) << 4;
// immediate: imm-1 (+1 in processor)
instr |= unsigned4(imm - 1) << 0;
// output
output_instr16(instr);
break;
default: // invalid opcode for or2i-instruction
yyerror("opcode not compatible with or2i syntax");
break;
}
}

74
assembler/src/handle_or3.c Normal file
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/*
* This file implements functions for
* - handling of instructions of type or3
*/
#include <stdio.h>
#include "../inc/msg.h"
#include "../inc/output.h"
#include "../inc/check.h"
#include "../inc/global.h"
/*
* outputs instruction to output for instructions width or3 instruction type
* opcode: opcode of instruction
* r1: register 1
* r2: register 2
* r3: register 3
*/
void handle_or3(op_t opcode, int r1, int r2, int r3) {
// instruction to be build
int instr = 0;
// here, scheme is simple and always the same
// register d: register 1
instr |= r1 << 8;
// register a: register 2
instr |= r2 << 4;
// register b: register 3
instr |= r3 << 0;
// opcode
switch (opcode) {
case op_add: // add instruction
// opcode
instr |= (0b0011) << 12;
// output
output_instr16(instr);
break;
case op_sub: // subtract instruction
// opcode
instr |= (0b0001) << 12;
// output
output_instr16(instr);
break;
case op_and: // bitwise and instruction
// opcode
instr |= (0b0010) << 12;
// output
output_instr16(instr);
break;
case op_or: // bitwise or instruction
// opcode
instr |= (0b0000) << 12;
// output
output_instr16(instr);
break;
case op_xor: // bitwise xor instruction
// opcode
instr |= (0b0100) << 12;
// output
output_instr16(instr);
break;
default: // invalid opcode for or3-instruction
yyerror("opcode not compatible with or3 syntax");
break;
}
}

50
assembler/src/handle_ori.c Normal file
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/*
* This file implements functions for
* - handling of instructions of type oi
*/
#include <stdio.h>
#include "../inc/msg.h"
#include "../inc/output.h"
#include "../inc/check.h"
#include "../inc/global.h"
/*
* outputs instruction to output for instructions width ori instruction type
* opcode: opcode of instruction
* r1: register 1
* imm: immediate
*/
void handle_ori(op_t opcode, int r1, int imm) {
// instruction to be build
int instr = 0;
switch (opcode) {
case op_addi: // add immediate instruction
// opcode: add immediate instruction
instr |= (0b0111) << 12;
// register d: register 1
instr |= reg(r1) << 8;
// immediate: value to add
instr |= signed8(imm) << 0;
// output
output_instr16(instr);
break;
case op_ldr: // load pc-relative instruction
// opcode: load pc-relative instruction
instr |= (0b1010) << 12;
// register d: register 1
instr |= reg(r1) << 8;
// immediate: pc-offset
instr |= signed8(imm) << 0;
// output
output_instr16(instr);
break;
default: // invalid opcode for ori-instruction
yyerror("opcode not compatible with ori syntax");
break;
}
}

175
assembler/src/label.c Normal file
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/*
* This file implements functions for
* - handling of labels
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "../inc/msg.h"
#include "../inc/label.h"
#include "../inc/global.h"
/*
* adds a label to the list
* name: name of the label
* address: address the label points to
*/
void label_add(char* name, int address) {
// new element inserted
label_t* newelement;
// tail of list
label_t* tail;
// verbose message: added label (in second run)
if (verbose) {
char msg[64 + LABEL_MAX_NAME_LENGTH];
char tmpname[LABEL_MAX_NAME_LENGTH];
strncpy(tmpname, name, LABEL_MAX_NAME_LENGTH);
sprintf(msg, "adding label '%s' at address '0x%08x'.", tmpname,
address);
yyverbose(msg);
}
// don't add labels in second run
if (!isfirstrun) {
return;
}
// check if label already exists
if (label_absolute(name) != -1) {
yyerror("label already exists.");
return;
}
// allocate memory for new label
newelement = malloc(sizeof(label_t));
if (newelement == 0) {
fprintf(stderr, "no free memory.");
return;
}
// copy data to new label
strncpy(newelement->name, name, LABEL_MAX_NAME_LENGTH);
newelement->address = address;
newelement->next = 0;
// find tail of list
if (label_listhead == 0) {
// empty list, insert as list head
label_listhead = newelement;
} else {
// list not empty find tail
tail = label_listhead;
while (tail->next != 0) {
tail = tail->next;
}
// set next item pointer
tail->next = newelement;
}
// output information to map file
if (f_map) {
fprintf(f_map, "0x%x: %s\n", newelement->address, newelement->name);
}
}
/*
* returns absolute address of a label
* name: name of the label
* return: absolute address of label or -1 if label not found
*/
int label_absolute(char* name) {
// tail of search
label_t* tail;
if (label_listhead == 0) {
// if empty list, label is not in list, return -1
return -1;
} else {
// list not empty find tail
// start search at list head
tail = label_listhead;
while (1) {
if (strcmp(tail->name, name) == 0) {
// name of search tail matches searched name
// return address
return tail->address;
}
if (tail->next != 0) {
// end of list not reached, update tail pointer
tail = tail->next;
} else {
// end of list, not found
if (!isfirstrun) { // second run: label must be found.
yyerror("label not found.");
}
// return -1, as label is not found
return -1;
}
}
}
// program does not reach this point due to earlier returns
}
/*
* returns relative address of a label
* name: name of the label
* return: relative address of label or -1 if label not found
*/
int label_relative(char* name) {
// absolute address of label
int absolute;
// find absolute address
absolute = label_absolute(name);
if (absolute > 0) {
// label found, calculate relative address
return (absolute - address) / 2 - 1;
} else {
// label not found, error message already prompted in label_absolute
return -1;
}
}
/*
* frees the allocated space used for the list of labels
*/
void label_free() {
// current element pointer
label_t* ptr;
// next element pointer
label_t* next;
// start at list head
ptr = label_listhead;
while (ptr != 0) {
// walk through list until end of list reached
// store next pointer
next = ptr->next;
// delete current item
free(ptr);
// proceed in list
ptr = next;
}
// reset list head
label_listhead = 0;
}

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/*
* This file implements the main function
*/
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <getopt.h>
#include "../inc/msg.h"
#include "../inc/label.h"
#include "../inc/global.h"
#include "../inc/output.h"
#include "../obj/asm.tab.h"
// reference to linenumber supplied by flex/bison
extern int yylineno;
// reference to yyrestart function supplied by flex/bison
void yyrestart(FILE* inputfile);
// file variable definitions and initialization
FILE* f_in = 0;
FILE* f_out = 0;
FILE* f_map = 0;
/*
* main function
* argc: number of arguments
* argv: arguments
*/
int main(int argc, char **argv) {
// output filename
char* output = 0;
// mapfile filename
char* map = 0;
// index of command line argument
int option_index = 0;
// character of command line argument
int c;
static struct option long_options[] = { { "verbose", 0, 0, 0 }, {
"autoalign", 0, 0, 0 }, { "fillbds", 0, 0, 0 }, {
"continue-on-error", 0, 0, 0 }, { 0, 0, 0, 0 } };
// reset flags
verbose = 0;
autoalign = 0;
continueonerror = 0;
errorhappened = 0;
while (1) {
// iterate through all command line options
// reset option_index
option_index = 0;
// get next option
c = getopt_long(argc, argv, "vm:o:", long_options, &option_index);
if (c == -1)
// no more options available, end loop
break;
// check which option it was
switch (c) {
case 0: // long option
if (strcmp(long_options[option_index].name, "verbose") == 0) {
// verbose flag
verbose = 1;
} else if (strcmp(long_options[option_index].name, "autoalign")
== 0) {
// auto-align flag
autoalign = 1;
} else if (strcmp(long_options[option_index].name, "fillbds")
== 0) {
// fill branch delay slot flag
fillbds = 1;
} else if (strcmp(long_options[option_index].name,
"continue-on-error") == 0) {
// continue on error flag
continueonerror = 1;
} else {
// unknown option
fprintf(stderr, "error: unknown command line option \"%s\"\n",
long_options[option_index].name);
destruct(EXIT_FAILURE);
}
break;
case 'v':
// verbose flag (short version)
verbose = 1;
break;
case 'm':
// map file
map = (char*) optarg;
break;
case 'o':
// output file
output = (char*) optarg;
break;
default:
// unknown option
fprintf(stderr, "error: unknown command line option \"%s\"\n",
long_options[option_index].name);
destruct(EXIT_FAILURE);
}
}
// Check non-option command line arguments
if (optind < argc) {
// one option still available (input)
inputfile = argv[optind++];
if (optind < argc) {
// more than one option still available, only one input file supported
fprintf(stderr, "too many input files specified.\n");
destruct(EXIT_FAILURE);
}
} else {
// no option available (no input file)
fprintf(stderr, "no input file specified.\n");
destruct(EXIT_FAILURE);
}
// Check if output file is specified
if (output == 0) {
// output file not specified
fprintf(stderr, "no output file specified.\n");
destruct(EXIT_FAILURE);
}
// Open all (specified) files
// open input file (must be specified, is checked before)
f_in = fopen(inputfile, "r");
if (!f_in) {
// could not open input file
fprintf(stderr, "error: could not open input file %s\n", inputfile);
perror(inputfile);
destruct(EXIT_FAILURE);
}
// open output file (must be specified, is checked before)
f_out = fopen(output, "w");
if (!f_out) {
// could not open output file
fprintf(stderr, "error: could not open output file %s\n", output);
perror(output);
destruct(EXIT_FAILURE);
}
// open map file if specified
if (map != 0) {
// mapfile is specified
f_map = fopen(map, "w");
if (!f_map) {
// could not open mapfile
fprintf(stderr, "error: could not open map file %s\n", map);
perror(map);
destruct(EXIT_FAILURE);
}
}
// reset variables
address = 0;
label_listhead = 0;
// start parsing f_in - first run
isfirstrun = 1;
yyrestart(f_in);
yyparse();
// go back to first character in input file
fseek(f_in, 0, SEEK_SET);
yylineno = 1;
// start parsing f_in - second run
address = 0;
isfirstrun = 0;
yyrestart(f_in);
yyparse();
// fill last word
if (address % 4 == 2) {
output_instr16(nop16);
}
// destruction
// final message
if (verbose) {
printf("%s: : info: output written to %s.\n", inputfile, output);
}
// exit main
if (!errorhappened) {
// no error happened
destruct(EXIT_SUCCESS);
} else {
// error happend in between
destruct(EXIT_FAILURE);
}
return 0; // suppress warning, actual program exit in destruct
}
// destructor, closes programs and cleans up memory
// exitvalue: value for exit
void destruct(int exitvalue) {
if (f_in) {
fclose(f_in);
}
if (f_out) {
fclose(f_out);
}
if (f_map) {
fclose(f_map);
}
label_free();
exit(exitvalue);
}

47
assembler/src/msg.c Normal file
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@@ -0,0 +1,47 @@
/*
* This file implements functions for
* - checking instruction parameters for range
*/
#include <stdlib.h>
#include <stdio.h>
#include "../inc/global.h"
// reference to linenumber supplied by flex
extern int yylineno;
/*
* verbose output (if flag is set)
* msg: verbose message
*/
void yyverbose(char* msg) {
if (verbose) {
// if verbose flag is set
if (!isfirstrun) {
// output verbose messages in second run
printf("%s:% 3i: info: %s (\"%s\")\n", inputfile, yylineno, msg,
linebuf);
}
}
}
/*
* error handler
* msg: error message
*/
void yyerror(char *s) {
if ((!continueonerror) || (!isfirstrun)) {
// output error messages if either stop at error or in second run
fprintf(stderr, "%s:% 3i: error: %s (\"%s\")\n", inputfile, yylineno, s,
linebuf);
}
// set error happened flag
errorhappened = 1;
if (!continueonerror) {
// if stop on error, stop
destruct(EXIT_FAILURE);
}
}

105
assembler/src/output.c Normal file
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@@ -0,0 +1,105 @@
/*
* This file implements functions for
* - writing to output file
* - writing to map file
*/
#include <stdio.h>
#include "../inc/msg.h"
#include "../inc/global.h"
/*
* outputs a number of length bits, given in instr to the output stream and inserts a linebreak after each 32bit
* instr: number to be printed
* length: number of bits to be printed
*/
void output_instr(int instr, int length) {
// index of outputted bit
int i;
for (i=length-1; i>=0; i--) {
// iterate through length bits
if(instr & (1<<i)) {
// if bit is 1 output '1'
fprintf(f_out, "1");
} else {
// if bit is 0 output '0'
fprintf(f_out, "0");
}
}
}
/*
* outputs a number of 16bits and updates address
* instr: number to be printed
*/
void output_instr16(int instr) {
if ((instr & 0xFFFF) == instr) {
// instruction fits into 16 bits
if (!isfirstrun) {
// in second run, output instruction
output_instr(instr, 16);
}
// increment address
address += 2;
// add line break
if ((!isfirstrun) && ((address % 4) == 0)) {
// not in first run and word is filled
fprintf(f_out, "\n");
}
} else {
// instruction does not fit into 16 bit
yyerror("internal error. 16bit instruction did not fit");
}
}
/*
* outputs a number of 32bits and updates address
* instr: number to be printed
*/
void output_instr32(int instr) {
if ((instr & 0xFFFFFFFF) == instr) {
// instruction fits into 32bits
if ((address % 4) != 0) {
// address not aligned
if (autoalign) {
// auto-align flag set
output_instr16(nop16);
} else {
// auto-align flag not set, output error
yyerror("32bit instruction not aligned.");
return;
}
}
// increment address
address += 4;
if (!isfirstrun) {
// in second run, output instruction
output_instr(instr, 32);
fprintf(f_out, "\n");
}
} else {
// instruction does not fit into 32bits
yyerror("internal error. 32bit instruction did not fit");
}
}
/*
* outputs a line to the mapfile (if specified and if in first run)
* s: string to be put to mapfile
*/
void output_line(char* s) {
if (isfirstrun && f_map) {
// if in first run and mapfile is specified
fprintf(f_map, "\t%s\n", s);
}
}

27
documentation/Makefile Normal file
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@@ -0,0 +1,27 @@
SVGS= $(wildcard figures/*.svg)
IMGS= $(SVGS:.svg=.pdf)
SRCS= $(wildcard *.tex)
#SRCS+= refs3.bib
docu=soc
TARGET=$(addsuffix .pdf,$(docu))
all: target images
target: $(TARGET) $(IMGS)
images: $(IMGS)
figures/%.pdf: figures/%.svg
inkscape -z -T -A $@ $<
%.pdf: %.tex $(SRCS) $(IMGS)
pdflatex -jobname=$(basename $@) -synctex=1 -interaction=nonstopmode -shell-escape $<
pdflatex -jobname=$(basename $@) -synctex=1 -interaction=nonstopmode -shell-escape $<
## Other Targets
clean:
rm -f $(IMGS) *.aux *.log *.dvi soc.pdf *.ps *.pyg *.toc *.loc *.lot *.out *.lof *.lol *.synctex.gz
.PHONY: all clean

164
documentation/architecture.tex Normal file
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@@ -0,0 +1,164 @@
\chapter{Processor Architecture}
\section{Block Diagram}
A simplified block diagram of the \procname can be found in Figure \ref{fig:blockdiagram_core}.
A diagram of the datapath can be found in Figure \ref{fig:blockdiagram_dp}
\begin{figure}[htb]
\centering
\includegraphics[scale=0.5]{./figures/block_core.pdf}
\caption{Simplified Block diagram of core architecture with surrounding entities}
\label{fig:blockdiagram_core}
\end{figure}
\begin{sidewaysfigure}[htb]
\centering
\includegraphics[scale=0.6]{./figures/block_dp.pdf}
\caption{Block diagram of the datapath}
\label{fig:blockdiagram_dp}
Pipeline registers in gray, for reasons of clarity, not all signals are included.
\end{sidewaysfigure}
\section{Configuration}
\label{sec:config}
Easy ways to configure the \procname can be found in package \inlinevhdl{lt16x32\_internal} (see Listing \ref{lst:configcode_internal}) and in package \inlinevhdl{lt16x32$\_$global} (see Listing \ref{lst:configcode_global}).
\begin{vhdl}[Possible Configurations in internal package]{lst:configcode_internal}
-- execute branch delay slot. if set to true,
-- the first operation behind any type of branch
-- is executed. if set to false, stalls are inserted
constant execute_branch_delay_slot : boolean := TRUE;
-- register width
constant reg_width : integer := 32;
-- pc width (should be smaller or equal to register width)
constant pc_width : integer := 32;
\end{vhdl}
\begin{vhdl}[Possible Configurations in global package]{lst:configcode_global}
-- width of the vector holding the interrupt
-- number, maximum 7 due to processor architecture
constant irq_num_width : integer := 4;
-- width of the vector holding the interrupt
-- priority, maximum 6 due to processor architecture
constant irq_prio_width : integer := 4;
\end{vhdl}
Currently, three values can be configured:
\paragraph{Branch delay slot}
\label{sec:branchdelayslot}
If the constant \inlinevhdl{execute$\_$branch$\_$delay$\_$slot} is set to \inlinevhdl{true}, the instruction behind a branch instruction is always executed.
If the constant is set to \inlinevhdl{false}, a \inlineasm{nop} is inserted if a branch is performed.
By default, the branch delay slot is always executed.
Pay attention that even if the branch is not yet taken in the branch delay slot, the program counter may contain the new address.
Hence, instructions using the program counter should not be placed in the branch delay slot.
This also means, that storing the current address for function returns can not be done in the branch delay slot.
Instead, use the \inlinevhdl{call} instruction for this purpose.
\paragraph{Register width}
With the constant \inlinevhdl{reg$\_$width} the width of the internal registers can be set. Valid values are 8, 16 and 32, by default 32bits are used.
\paragraph{PC width}
With the constant \inlinevhdl{pc$\_$width} the width of the program counter can be set.
Valid values are 8, 16 and 32, it must be smaller or equal to the register width.
By default, 32bits are used.
\paragraph{Interrupt Number Width}
This constant holds the width of the interrupt number, values between 1 and 7 are valid.
This determines the number of possible interrupts.
By default, 4bits are used, allowing $2^4 = 16$ interrupts.
\begin{equation*}
\text{Possible Interrupts} = 2^{(\text{Width})}
\end{equation*}
\paragraph{Interrupt Priority Width}
\label{sec:config_priowidth}
This constant determines the width of the runtime/interrupt priority, values between 1 and 6 are valid.
By default, 16 levels of priority are allowed.
One additional bit is supported by the use of non-maskable interrupts (NMI, see Section \ref{sec:nmi}).
\section{Pipeline Stages}
As shown in Figure \ref{fig:blockdiagram_dp}, the processor has three pipeline stages.
Due to this scheme, there is a delay between reading the instruction and changing data in the (register) memory of three clock cycles.
\paragraph{Stage 1: Decode/Setup}
In the first stage, the instruction is fetched from the instruction memory and decoded. Also, the needed register contents are loaded from the register file.
\paragraph{Stage 2: Load and Execute}
In this stage, the ALU is performing the operation and data is read from the data memory.
\paragraph{Stage 3: Writeback}
Data is written back to the register file and written to the data memory.
Possible sources for this data are the data read from the memory in the last clock cycle or the contents of register b.
\section{Registers}
The \procname has 16 registers, 14 of which can be used as general purpose registers.
The other four have special functions, VHDL defines are given in Listing \ref{lst:vhdl_regnumbers} and can be found in the \inlinevhdl{lt16x32\_internal} package.
\begin{vhdl}[Constant Defines for the Special Purpose Registers]{lst:vhdl_regnumbers}
-- register number for stack pointer
constant sp_num : reg_number := to_reg_number(12);
-- register number for link register
constant lr_num : reg_number := to_reg_number(13);
-- register number for status register
constant sr_num : reg_number := to_reg_number(14);
-- register number for pc register
constant pc_num : reg_number := to_reg_number(15);
\end{vhdl}
\subsection{General Purpose Registers}
Registers \inlineasm{r0} to \inlineasm{r11} can be used without special consideration as general purpose registers.
Registers \inlineasm{r12} (stack pointer) and \inlineasm{r13} (link register) can also be used as general purpose register but are additionally altered with special instructions.
\subsection{Stack Pointer}
The stackpointer (\inlineasm{r12}) is used when jumping into or out of interrupt handlers (i.e. external interrupts or \inlineasm{trap} instructions and \inlineasm{reti}).
It must be set to the correct address of the stack, before any interrupt occurs.
\subsection{Link Register}
The link register (\inlineasm{r13}) is set by the \inlineasm{call} instruction.
This allows for flexible function returns using the pseudo instruction \inlineasm{ret} (a branch to the link register).
\subsection{Status Register r14}
The status register is a special 32bit register.
The register contents are displayed in table \ref{tbl:SR}, reserved bits always read zero and should be written to as zeroes for future compatibility.
\begin{table}
\center
\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|}
\hline
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24 & 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{16}{|c|}{reserved}\\
\hline
\multicolumn{16}{c}{}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8 & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0 \\
\hline
\multicolumn{8}{|c|}{reserved} & \multicolumn{6}{|c|}{priority} & T & O \\
\hline
\end{tabular}
\caption{Status Register Contents}
\label{tbl:SR}
\end{table}
\subsubsection{Runtime Priority - SR[7-2]}
Bits seven to two define the current runtime priority, larger numbers mean higher priority. The priority is left aligned.
With a runtime priority width configured to four bits, the priority is stored in bits seven to four and the other bits read zero.
Writes to not used priority bits are discarded.
\subsubsection{Truthflag - SR[1]}
Bit one is the truth flag, which can be set/reset by compare instructions and are used for conditional branches and calls.
Also, the truth flag can be set manually by writing to the status register.
\subsubsection{Overflowflag - SR[0]}
Bit zero is the overflow flag, which is set by arithmetic instructions, such as addition and subtraction.
In additions an overflow has occured, if both operands are the same sign and the result's sign is different (i.e. $5 + 6 < 0$ or $(-5) + (-7) > 0$, listing \ref{lst:ovf_add}).
In subtractions an overflow occured, if both operands are from opposing sign and the minuend's sign differ from the result's (i.e. $(-8) - 5 > 0$ or $5 - (-4) < 0$, listing \ref{lst:ovf_sub}).
This follows normal rules for signed calculations, which are as well used in other processor designs.
\begin{vhdl}[Overflow Generation for Addition]{lst:ovf_add}
c_out <= (in_a(reg_width-1) AND in_b(reg_width-1)
AND not result(reg_width-1))
OR (not in_a(reg_width-1) AND not in_b(reg_width-1)
AND result(reg_width-1));
\end{vhdl}
\begin{vhdl}[Overflow Generation for Subtraction]{lst:ovf_sub}
c_out <= (in_a(reg_width-1) AND not in_b(reg_width-1)
AND not result(reg_width-1))
OR (not in_a(reg_width-1) AND in_b(reg_width-1)
AND result(reg_width-1));
\end{vhdl}
\subsection{Program Counter}
Register \inlineasm{r15} is reserved for the program counter and is read only from the user interface. Write accesses are ignored. It may be altered with special instructions such as branch and call and in interrupt request situations by the processor itself.

212
documentation/documentation.tex Normal file
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% To make formatting easy tell LaTeX what kind of document you want to write
% by changing the according {} to {#1}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Which language do you want to write in
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%English
\newcommand{\EN}[1]{#1}
%German
\newcommand{\DE}[1]{}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% For print single or double page?
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\newcommand{\single}[1]{#1}
\newcommand{\double}[1]{}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Now this is followed by a lot of page and command definitions. For the beginning you
% should be able to continue where you find the next comment section like this one.
% However, you might want to take a look a the definitions sometime to be able to use
% them. Of course you can also add the defintions you needed yourself.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\single{\documentclass[12pt,a4paper,oneside,german,english]{book}}
\double{\documentclass[12pt,a4paper,twoside,german,english]{book}}
\usepackage[ngerman,english]{babel}
%\usepackage[draft,breaklinks=true,colorlinks=false,dvips,bookmarks,pdffitwindow,pdfcenterwindow=true,pdfstartview=Fit]{hyperref}
%\usepackage[breaklinks=true,colorlinks=false,dvips,bookmarks,pdffitwindow,pdfcenterwindow=true,pdfstartview=Fit]{hyperref}
\usepackage{setspace}
\usepackage{cite}
\usepackage{float,times}
\usepackage[utf8x]{inputenc}
\usepackage[T1]{fontenc}
\usepackage{amsmath,amsthm,latexsym}
\usepackage[dvips]{epsfig}
\usepackage{subfigure}
\usepackage{rotating}
\usepackage{minted}
\usepackage{newfloat}
\usepackage{xspace}
\usepackage{xcolor}
\usepackage{afterpage}
\usepackage{multirow}
\usepackage{array}
%! put the new-command after the inputenc package use, so 'ü' will not be shown as abomination ASCII -TF
\input{globalcommands.tex}
\newcommand{\DocuTitle}{Documentation to the LT16x32} %TODO: can not use \procname here, why so ever...
%\newcommand{\DiplTitleGerman}{Dokumentation für den LT16x32}
% format page layout.
\setlength{\topmargin}{0cm}
\setlength{\textwidth}{15cm}
\setlength{\textheight}{22cm}
\setlength{\oddsidemargin}{1cm}
\setlength{\evensidemargin}{0cm}
\setlength{\headheight}{15pt}
% \setlength{\voffset}{-0cm}
% \setlength{\topmargin}{0cm}
% \setlength{\headheight}{0.54cm}
% \setlength{\textheight}{23cm}
% % \setlength{\headsep}{1.5cm}
% %\setlength{\hoffset}{-2.54cm}
% \setlength{\hoffset}{0cm}
% \setlength{\oddsidemargin}{0.46cm}
% \setlength{\evensidemargin}{0.46cm}
% \setlength{\textwidth}{15cm}
% \setlength{\marginparsep}{0cm}
% \setlength{\marginparwidth}{1.54cm}
\setcounter{secnumdepth}{3}
% \setlength{\footskip}{1cm}
% \setlength{\parindent}{0cm}
% \setlength{\parskip}{1em}
\usepackage{fancyhdr}
\pagestyle{fancy}
\fancyhead{} % clear all header fields
%\fancyhead[LO, RE]{\slshape \nouppercase{\leftmark}} % chapter titles
%\fancyhead[LE, RO]{\slshape \nouppercase{\leftmark}\\\nouppercase{\rightmark}} % section titles
\double{\fancyhead[LE]{\slshape \nouppercase{\leftmark}}} % chapter titles
\fancyhead[RO]{\slshape \nouppercase{\rightmark}} % section titles
\fancyfoot{} % clear all footer fields
\fancyfoot[C]{\thepage}
\usepackage[%dvips,
colorlinks=false,
bookmarks,
pdffitwindow,
pdfcenterwindow=true,
pdfstartview=Fitpdftex,
pdfauthor={Lasse Schnepel},
pdftitle={\DocuTitle},
pdfsubject={LT16x32 Documentation}, % one sentence summery
pdfkeywords={Processor,Firmware-based Verification,Architecture design}, %comma-seperated keywords
pdfproducer={Latex with hyperref},
pdfcreator={}]{hyperref}
\begin{document}
%\lhead[\fancyplain{}{\thepage}] {\fancyplain{}{\rightmark}}
%\chead[\fancyplain{}{}] {\fancyplain{}{}}
%\rhead[\fancy{}{\rightmark}] {\fancy{}{\thepage}}
%\rhead[\fancyplain{}{\rightmark}] {\fancyplain{}{\thepage}}
%\lfoot[\fancyplain{}{}] {\fancyplain{\tstamp}{\tstamp}}
%\cfoot[\fancy{\thepage}{}] {\fancy{\thepage}{}}
%\cfoot[\fancyplain{\thepage}{}] {\fancyplain{\thepage}{}}
%\rfoot[\fancyplain{\tstamp} {\tstamp}] {\fancyplain{}{}}
% \fancyhf{} %delete the current section for header and footer
% \fancyhead[LE,RO]{\bfseries\thepage}
% \fancyhead[LO]{\bfseries\rightmark}
% \fancyhead[RE]{\bfseries\leftmark}
% \renewcommand{\headrulewidth}{0.5pt}
% % make space for the rule
% \fancypagestyle{plain}{%
% \fancyhead{} %get rid of the headers on plain pages
% %\renewcommand{\headrulewidth}{0} % and the line
% }
\EN{\selectlanguage{english}}
\DE{\selectlanguage{german}}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Here you have to start editing
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\title{\DiplTitle}
\author{Lasse Schnepel}
\pagenumbering{arabic}
\hyphenation{Bit-ebenen Gateprop Bit-ebene Fanin Boole-sche
Partial-produkt-generator
Code-inspektion
Verifika-tions-ablauf
IPC-Verifika-tions-ablauf
Abhangig-keiten
}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% title page
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\frontmatter
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% titel page
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\thispagestyle{empty}
\begin{center}
\mbox{}
\vspace{2cm}
\Large{Documentation of the \procname}
\vspace{1cm}
\normalsize
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Put the current year here
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
Kaiserslautern, 2014 \\
\vfill
\end{center}
\tableofcontents
\mainmatter
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Now this is followed by your chapters
% this usually starts with introduction and Fundamentals and then
% continues with whatever you need or did
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\input{content}
\backmatter
\listoffigures
\listoftables
\listofcodefloat %triggers Errors for me, for whatever reason, but the pdf is generated nonetheless -TF
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Choose your Bibtex Style File (here alphadin.bst) and references.
% Hint: For references make a local link refs2 to our jabref
% directory "/import/jabref/refs2.bib"
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\bibliographystyle{alphadin}
\bibliography{refs3}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Curriculum Vitae
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%\selectlanguage{german}
%\input{cv.tex}
%\selectlanguage{english}
\end{document}

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SVGS= $(wildcard *.svg)
IMGS= $(SVGS:.svg=.pdf)
all: $(IMGS)
%.pdf: %.svg
inkscape -z -T -A $@ $<
clean:
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%%%%%%%%%%%%
%%% MINTED
%%%%%%%%%%%%
\DeclareFloatingEnvironment[
fileext=loc,
listname=List of Listings,
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placement=htp,
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%%%%%%%%%%%%
%%% COMMENTS AND TODO-MARKERS
%%%%%%%%%%%%
% \newcommand{\comment}[3]{\marginpar{\textcolor{#2}{Comment: #1}}\textcolor{#2}{\textit{[#1: #3]}}}
% \newcommand{\TF}[1]{\comment{TF}{orange}{#1}}
% \newcommand{\LS}[1]{\comment{LS}{blue}{#1}}
%
% \newcommand{\qn}{\todo{qn!}}
% \newcommand{\sectodo}{\todo{Still todo.}}
% \newcommand{\seccheck}{\marginpar{\textcolor{orange}{reread}}}
% \newcommand{\secthomas}{\marginpar{\textcolor{green}{thomas}}}
% \newcommand{\secdone}{\marginpar{\textcolor{gray}{done}}}
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% \newcommand{\todo}[1]{\textcolor{red}{\textit{[#1]}}\marginpar{\textcolor{red}{\textbf{TODO}}}}
%
%
% %%% BLANK COMMANDS FOR PUBLISHING
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% \renewcommand{\publish}[1]{#1} % TODO: uncomment this line before printing!
%
% \publish{\renewcommand{\comment}[3]{}}
% \publish{\renewcommand{\TF}[1]{}}
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\newcommand{\TF}[1]{\comment{TF}{red}{#1}}
\newcommand{\TS}[1]{\comment{TS}{blue}{#1}}
\newcommand{\FP}[1]{\comment{TS}{orange}{#1}}
%%%%%%%%%%%%
%%% LOGIC OPERATORS
%%%%%%%%%%%%
\newcommand{\logicxor}{\texttt{XOR}\xspace}
\newcommand{\logicor}{$||$\xspace}%TODO: does not show up as OR
\newcommand{\logicand}{\&\xspace}
%%%%%%%%%%%%
%%% STUFF
%%%%%%%%%%%%
\newcommand{\mem}[1]{*#1\xspace}
\newcommand{\x}{--\xspace}
%%%%%%%%%%%%
%%% NAMES
%%%%%%%%%%%%
\newcommand{\procname}{\textsl{LT16x32}\xspace}
%%%%%%%%%%%%
%%% FORMAT SHORTCUTS
%%%%%%%%%%%%
\newcommand{\floatplace}{[ht]}
\newcommand{\tc}[1]{\textbf{#1}}
\newcommand{\hex}[1]{#1}
\newcommand{\bits}[1]{#1}
\newcommand{\filename}[1]{{\small\texttt{#1}}}
\newcommand{\command}[1]{{\small\texttt{#1}}}
\newcommand{\inlinevhdl}[1]{{\small\texttt{#1}}} %TODO with syntax highlighting and check for $\_$
\newcommand{\inlinec}[1]{{\small\texttt{#1}}} %TODO with syntax highlighting and check for $\_$
\newcommand{\inlineasm}[1]{{\small\texttt{#1}}} %TODO with syntax highlighting and check for $\_$
\newcommand{\instruction}[7]{
\subsubsection{#1}
\label{instr_#2}
\begin{description}
\nolistskip
\item[Opcode:] \texttt{#3}
\item[Assembler:] \inlineasm{#4}
\item[Operation:] #5
\item[C-Equivalent:] \inlinec{#6}
\item[Status Register:] #7
\end{description}
}
%%%%%%%%%%%%
%%% TEX WORKAROUNDS
%%%%%%%%%%%%
\newcommand{\nolistskip}{\itemsep-3pt}

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\chapter{Guides}
\section{How to implement a lookup or branch table}
Due to the limitation of the \verb=ldr= instruction,
addressing large fields of constants with it is not feasible,
especially if those constants are refered to by more than one part of the program.
This can be circumvented by using the assemblers directive \verb|=labelname| to store a pointer to a labels location (See Section~\ref{sec:AssemblerDirectives}).
Pointers to data in memory can be stored conviently close to an \verb=ldr= instruction,
making the access to the memory content via a pointer based load or store instruction possible.
The most common use of this mechanic is the lookup table.
An example is given in Listing~\ref{lst:ldr_useage}.
\begin{asm}[Example on indirect LDR use]{lst:ldr_useage}
.align
lookup_table:
.word 0x0001
.word 0x0010
//...
// large amounts of code and/or data
//...
.align
lookuptable_ptr:
.word =lookup_table
//...
ldr rX , >lookuptable_ptr
//...
ld32 rY,rX // load from pointer
addi rX, 4
ld32 rZ,rX // load from pointer with offset
//...
\end{asm}

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\chapter{Assembler and Instructions}
\section{Processor Instructions}
The \procname features a RISC instruction set with 16bit instructions and is prepared to be extended with 32bit and allows multicycle instructions.
In 16bit instructions, the first nibble (4bits) of the instruction code is the opcode determining the operation.
The opcode \bits{1111} is reserved for 32bit instructions which are always are word aligned.
\subsection{Instruction Format}
Several different instruction formats are used in the \procname.
As at the moment, no 32bit instruction is implemented, this section describes instruction formats for 16bit instructions only.
Each halfword is split up into four nibbles (each of a size of 4bits), whose meaning can be seen in Table \ref{tbl:instr_formatnibbles}.
\begin{table}
\caption{16bit Instruction Formats}
\label{tbl:instr_formatnibbles}
\begin{center}
\begin{tabular}{|l||c|c|c|c||p{0.2\textwidth}|}
\hline
Format & 15-12 & 11-8 & 7-4 & 3-0 & Example Uses\\
\hline\hline
Three Registers & opcode & Rd & Ra & Rb & Calculations\\
\hline
4bit Immediate & opcode & Rd & Ra & Imm(3-0) & Shift\\
\hline
8bit Immediate & opcode & Rd & Imm(7-4) & Imm(3-0) & Add Immediate, Load PC-Relative\\
\hline
Mode with Register & opcode & Mode & Ra & Rb & Compare, Load/Store\\
\hline
Mode with Immediate & opcode & Mode & Imm(7-4) & Imm(3-0) & Branch/Call to Immediate\\
\hline
\end{tabular}
\end{center}
\end{table}
\subsection{List of available Instructions}
\label{sec:instructionlist}
The following instructions are supported:
\paragraph{Arithmetic Operations}
\begin{itemize}
\nolistskip
\item \hyperref[instr_add]{Signed Addition}
\item \hyperref[instr_sub]{Signed Subtraction}
\item \hyperref[instr_addi]{Signed Addition with Immediate}
\end{itemize}
\paragraph{Bitwise/Logic Operations}
\begin{itemize}
\nolistskip
\item \hyperref[instr_and]{Bitwise AND}
\item \hyperref[instr_or]{Bitwise OR}
\item \hyperref[instr_xor]{Bitwise XOR}
\item \hyperref[instr_lsh]{Logic Shift Left}
\item \hyperref[instr_rsh]{Logic Shift Right}
\item \hyperref[instr_cmp]{Compare}
\end{itemize}
\paragraph{Memory Operations}
\begin{itemize}
\nolistskip
\item \hyperref[instr_ldr]{Load PC Relative}
\item \hyperref[instr_ld]{Load Data from Pointer}
\item \hyperref[instr_st]{Store Data to Pointer}
\end{itemize}
\paragraph{Branch/Call/Trap Operations}
\begin{itemize}
\nolistskip
\item \hyperref[instr_bri]{Branch to Offset}
\item \hyperref[instr_brr]{Branch to Register}
\item \hyperref[instr_calli]{Call to Offset}
\item \hyperref[instr_callr]{Call to Register}
\item \hyperref[instr_trap]{Trap}
\item \hyperref[instr_reti]{Return from Interrupt}
\item \hyperref[instr_brt]{Branch to Table}
\end{itemize}
\paragraph{Miscellaneous Operations}
\begin{itemize}
\nolistskip
\item \hyperref[instr_tst]{Test and Set}
\end{itemize}
\instruction{Signed Addition}{add}
{0011 dddd aaaa bbbb}
{add rd, ra, rb}
{Registers ra and rb are treated as two signed numbers and are added. The result is stored in rd.}
{rd = ra + rb;}
{The overflow flag is updated.}
\instruction{Signed Subtraction}{sub}
{0001 dddd aaaa bbbb}
{add rd, ra, rb}
{Registers ra and rb are treated as two signed numbers and are subtracted. The result is stored in rd.}
{rd = ra - rb;}
{The overflow flag is updated.}
\instruction{Bitwise AND}{and}
{0010 dddd aaaa bbbb}
{and rd, ra, rb}
{Registers ra and rb are treated as bit masks and are anded with each other. The result is stored in rd.}
{rd = ra \& rb;}
{No flag is updated.}
\instruction{Bitwise OR}{or}
{0000 dddd aaaa bbbb}
{or rd, ra, rb}
{Registers ra and rb are treated as bit masks and are ored with each other. The result is stored in rd.}
{rd = ra | rb;}
{No flag is updated.}
\instruction{Bitwise XOR}{xor}
{0100 dddd aaaa bbbb}
{xor rd, ra, rb}
{Registers ra and rb are treated as bit masks and are xored with each other. The result is stored in rd.}
{rd = ra $\hat\ $ rb;}
{No flag is updated.}
\instruction{Logic Shift Left}{lsh}
{0101 dddd aaaa bbbb}
{lsh rd, ra, imm}
{Register ra is treated as bit masks and shifted to the left by imm bits, ra is filled with zeroes. imm is treated as unsigned number. The result is stored in rd. Internally, imm is incremented by one, which is compensated for in the assembler.}
{rd = ra $<<$ imm;}
{No flag is updated.}
\instruction{Logic Shift Right}{rsh}
{0110 dddd aaaa bbbb}
{rsh rd, ra, imm}
{Register ra is treated as bit masks and shifted to the right by imm bits, ra is filled with zeroes. imm is treated as unsigned number. The result is stored in rd. Internally, imm is incremented by one, which is compensated for in the assembler.}
{rd = ra $>>$ imm;}
{No flag is updated.}
\instruction{Signed Addition with Immediate}{addi}
{0111 dddd iiii iiii}
{addi rd, imm}
{Register rd and imm are treated as signed numbers and are added. The result is stored in rd.}
{rd = rd + imm;}
{The overflow flag is updated.}
\instruction{Compare}{cmp}
{1000 mmmm aaaa bbbb}
{cmp mode ra, rb}
{Registers ra and rb are treated as signed numbers and are compared. If the condition, given by mode is true, the truth-flag is set, otherwise reset. Allowed modes are\begin{description}\nolistskip
\item[0000, eq]equal
\item[1000, neq]not equal
\item[0010, gg]greater
\item[0001, ge]greater or equal
\item[1001, ll]less
\item[1010, le]less or equal
\end{description}}
{(ra == rb) ? (T=1) : (T=0);\\// where == is interchangable by mode}
{The truth flag is updated.}
\instruction{Load PC Relative}{ldr}
{1010 dddd iiii iiii}
{ldr rd, imm}
{Register rd is loaded with memory data from address (PC+(imm$<<$1)), where imm is treated as signed number and is left shifted by one bit.}
{rd = *(PC + (imm$<<$1)}
{No flag is updated.}
\instruction{Load Data from Pointer}{ld}
{1011 0mmm aaaa bbbb}
{ld08 ra, rb\\ld16 ra, rb\\ld32 ra, rb}
{Loads data from pointer. Register rb's content is used as absolute address, the loaded data is written to register ra. Following modes are supported:
\begin{description}
\nolistskip
\item[000] Load byte
\item[001] Load halfword
\item[010] Load word
\end{description}
}
{ra = *rb}
{No flag is updated}
\instruction{Store Data to Pointer}{st}
{1011 1mmm aaaa bbbb}
{st08 ra, rb\\st16 ra, rb\\st32 ra, rb}
{Stores data to pointer. Register ra's content is used as absolute address to store the content of register rb. Following modes are supported:
\begin{description}
\nolistskip
\item[000] Store byte
\item[001] Store halfword
\item[010] Store word
\end{description}
As the data is valid only after two clock cycles, the user must ensure that the same address is not used in read transactions in the following instruction (such as ld, ldr, tst).
}
{*ra = rb}
{No flag is updated}
\instruction{Branch to Offset}{bri}
{1100 010c iiii iiii}
{br imm\\br always/true imm}
{Sets the program counter to PC+imm, where imm is treated as signed number. For details about the branch delay slot see section \ref{sec:branchdelayslot}. If c==1, the branch is conditional and performed only, if the truth flag is set.}
{if ((c==0) \logicor (T==1)) goto (PC+imm);}
{No flag is updated}
\instruction{Branch to Register}{brr}
{1100 011c aaaa xxxx}
{br ra\\br always/true ra}
{Sets the program counter to register a. For details about the branch delay slot see section \ref{sec:branchdelayslot}. If c==1, the branch is conditional and performed only, if the truth flag is set.}
{if ((c==0) \logicor (T==1)) goto (ra$<<$1);}
{No flag is updated}
\instruction{Call to Offset}{calli}
{1100 100c iiii iiii}
{call imm\\call always/true imm}
{Sets the program counter to PC+imm, where imm is treated as signed number, and stores the current program counter in the link register. If c==1, the call is conditional and performed only, if the truth flag is set. This is a multicycle operation which consumes two clock cycles.}
{if ((c==0) \logicor (T==1)) \{LR=PC; goto (PC+imm);\}}
{No flag is updated}
\instruction{Call to Register}{callr}
{1100 101c aaaa xxxx}
{call ra\\call always/true ra}
{Sets the program counter to register a and stores the current program counter in the link register. If c==1, the call is conditional and performed only, if the truth flag is set. This is a multicycle operation which consumes two clock cycles.}
{if ((c==0) \logicor (T==1)) \{LR=PC; goto (ra$<<$1);\}}
{No flag is updated}
\instruction{Trap}{trap}
{1100 11xx iiii iiii}
{trap imm}
{Request an interrupt of number imm. Number of bits for imm can be set in processor configuration, the number must be right aligned.}
{no equivalent}
{No flag is updated}
\instruction{Return from Interrupt}{reti}
{1100 000x xxxx xxxx}
{reti}
{Returns from Interrupt, by popping the link and status register from the stack and branching to the current link register contents. This is a multicycle operation which consumes five clock cycles.}
{no equivalent}
{No flag is updated.}
\instruction{Branch to Table}{brt}
{1100 001c aaaa xxxx}
{brt ra}
{Increments the program counter by register a. This allows for easy creation of branch tables. For details about the branch delay slot see section \ref{sec:branchdelayslot}. If c==1, the branch is conditional and only performed if the truth flag is set.}
{PC = PC + (ra$<<$1)}
{No flag is updated.}
\instruction{Test and Set}{tst}
{1001 dddd aaaa xxxx}
{tst rd, ra}
{Test and set can be used to implement mutexes. The lower seven bits of the byte can be used to implement semaphores.}
{temp=$_\text{byte}$*ra; rd = temp;\\T = (temp \& 0x80==0); temp=temp $|$ 0x80; *ra=$_\text{byte}$temp;}
{The T-flag is set if the mutex is free and reset if the mutex is already reserved.}
\section{Assembler}
The supplied assembler is a two-pass assembler (see thesis, Section 2.6) based on \filename{flex} and \filename{bison} which are used to parse the input file.
\subsection{HowTo: Assemble Input Files}
A prepared assembler file \filename{input.prog} (see examples in \filename{/source/programs/}) can easily assembled into a formatted file \filename{output.ram} supported by the \procname by calling the assembler \filename{asm}:
\begin{verbatim}
asm input.prog -o output.ram
\end{verbatim}
\subsection{Allowed Input}
The input to the assembler is case sensitive and all mnemonics have to be lower case. A typical line follows Listing \ref{lst:asm_general}, where all parts are optional (a mnemonic is needed if parameters are supplied though).
\begin{asm}[General Inputline]{lst:asm_general}
label: mnemonic mode par1, par2, par3 // comment
\end{asm}
Parameters can either be registers names r0 to r15, SP, LR, SR or PC,
or can be immediate values in various number formats (decimal, binary or hexadecimal numbers),
for prefixes see Table \ref{tbl:asm_numberformats}.
Binary and hexadecimal numbers are not sign extended and always treated as unsigned values.
Also, absolute or relative references to labels are allowed as parameters, see Section \ref{sec:labels} for details.
Number and type of parameters vary for each instruction, allowed combinations are listed in Section \ref{sec:instructionlist}.
\begin{table}
\begin{center}
\begin{tabular}{|c|c|c|}
\hline
Numberformat & Prefix & Example\\
\hline\hline
Decimal & None & -45 \\
Binary & 0b & 0b11011 \\
Hexadecimal & 0x & 0xFE \\
\hline
\end{tabular}
\end{center}
\caption{Number Format Prefixes}
\label{tbl:asm_numberformats}
\end{table}
\subsection{Pseudo Instructions}
Several instructions are supported which are not directly processed by the \procname but which are mapped to other instructions.
For details on the instructions used, see Section \ref{sec:instructionlist}.
\begin{description}
\item[No Operation (nop)] No operation is performed, wait one clock cycle. Mapped to \inlineasm{or r0, r0, r0}.
\item[Move Register (mov rd, ra)] The content of \inlineasm{ra} is copied to \inlineasm{rd}. Mapped to \inlineasm{or rd, ra, ra}.
\item[Return (ret)] Returns to callee after a call instruction. Mapped to \inlineasm{br always lr}.
\item[Clear Register (clr rd)] Resets \inlineasm{rd} to zero. Mapped to \inlineasm{xor rd, rd, rd}.
\end{description}
\subsection{Directives}%
\label{sec:AssemblerDirectives}%
The assembler supports several directives which can be included in the input code, see Listing \ref{lst:asm_directives}.
\begin{description}
\item[.word]stores the following parameter directly into the memory.
\item[.address]inserts nops until the address given as parameter is reached.
\item[.align]if needed, a 16bit nop is inserted to align the following instruction
\end{description}
\begin{asm}[Example for the use of directives]{lst:asm_directives}
// load variables from constant pointer
ldr r0, >variableA
ldr r1, >variableB
// store variableA
.align // fix eventual non-word-alignment
variableA: .word 0x1234
// store variableB
.address 0x100 // store variableB at address 0x100
variableB: .word 0xABCD
\end{asm}
\subsection{Labels}
\label{sec:labels}
Labels can be set in the code directly, as seen in Listing \ref{lst:asm_general}.
They can be reffered to in absolute or relative manner (see Listing \ref{lst:asm_labels}).
Label names can include upper and lower case letters, numbers and underscores.
While absolute referencing puts the whole address into the output, relative referencing adds only the difference to the address of instruction which is referencing to the label.
\begin{asm}[Label References]{lst:asm_labels}
label: br >label // relative reference
.word =label // absolute reference
\end{asm}
\subsection{Assembler Options}
Several command line options are available:
\begin{description}
\item[-o filename]Determines the output file.
\item[-m filename]The assembler outputs a map file, containing all labels and their addresses.
\item[-v or -\xspace -verbose]Outputs all intermediate information.
\item[-\xspace -autoalign]Automatically aligns 32bit instruction and immediate values
\item[-\xspace -fillbds]Fills branch delay slots with nop instruction (i.e. inserts nop after all branches)
\item[-\xspace -continue-on-error]Continues parsing even with errors.
\end{description}
\subsection{Output}
The standard output format is a one-word-per-line bitstring representation of the instruction memory, which can directly be read by the testbench provided and used as input for memory synthesis.
\section{HowTo: Add more instructions}
\subsection{Processor Side}
\begin{enumerate}
\item Add opcode constant define to \verb=lt16x32_internal= package.
\item Add case to 16bit decoder and set control signals that differ from default settings.
\end{enumerate}
\subsection{Assembler Side}
\begin{enumerate}
\item Add enumerate item to op$\_$t in global.h
\item Add pattern to flex code in asm.l
\item Add handling to handle$\_$xy.c according to wished syntax style.
\item Recompile assembler by running the make script.
\end{enumerate}
\subsection{32bit Extension}
If 32bit instruction should be implemented, follow the structure of the 16bit decoder to implement the 32bit decoder in \filename{decoder\_32bit.vhd}.
\subsection{Multicycle Instructions}
To implement multicycle operations, changes need to be implemented in \filename{decoder$\_$fsm.vhd}.
Use the implementation of reti as an example.

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\chapter{Interrupts}
\section{Interrupt Controller}
\label{sec:irq_ctrl}
The interrupt controller features a configurable number of interrupt lines with a configurable amount of priorities.
The configuration follows that of the \procname (see Section \ref{sec:config}).
These intterupts lines need to be asserted for one clock cycle to trigger an interrupt request to the processor core.
Additionally, trap requests from the core are handled (as described in \ref{sec:trap}).
\section{Priority, NMI}
\label{sec:nmi}
The processor features multiple levels of runtime priority (configurable, see Section \ref{sec:config_priowidth}) where a greater number means higher priority.
Additionally, non maskable interrupts (NMI) are supported which are always executed regardless the current processor runtime priority.
The processor starts with the highest possible runtime priority by default to disable interrupts at startup (with the exception of NMI).
This is needed as the stack pointer needs to be set to a valid address before any interrupt (including NMI) can be executed.
\section{Interface and Timing Diagram}
Both ports \inlinevhdl{in\_irq} and \inlinevhdl{out\_irq} (for type definitions see Listing \ref{lst:typedef_irq}) should be connected to a fitting interrupt controller (for example the implementation described in Section \ref{sec:irq_ctrl}).
\begin{vhdl}[Type definitions for Interrupt Controller Ports]{lst:typedef_irq}
-- collection of all signals from the
-- interrupt controller to the core
type irq_core is record
-- interrupt number of requested interrupt
num : unsigned(irq_num_width - 1 downto 0);
-- priority of requested interrupt
-- (higher number means higher priority)
priority : unsigned(irq_prio_width - 1 downto 0);
-- request signal, active high
req : std_logic;
-- non maskable interrupt flag, active high
nmi : std_logic;
end record;
-- collection of all signals from the core
-- to the interrupt controller
type core_irq is record
-- interrupt acknowledge
-- high if requested interrupt is processed
ack : std_logic;
-- number of interrupt requested by
-- internal trap instruction
trap_num : unsigned(irq_num_width - 1 downto 0);
-- request signal for internal trap, active high
trap_req : std_logic;
end record;
\end{vhdl}
\subsection{Interrupt Request}
The external world (i.e. the interrupt controller) can request an interrupt by writing the interrupt number, its priority to \inlinevhdl{in\_irq} and setting the \inlinevhdl{nmi} bit accordingly.
After these are set, \inlinevhdl{req} can be asserted and must be held high until the core acknowledges the interrupt request by asserting \inlinevhdl{ack} for one clock cycle (see Figure \ref{fig:signal_irq_req}).
\begin{figure}[htb]
\center
\includegraphics[scale=1]{./figures/signal_irq_req.pdf}
\caption{Signal Pattern for Interrupt Requests}
\label{fig:signal_irq_req}
\end{figure}
\subsection{Trap Implementation}
\label{sec:trap}
When executing a trap instruction, an interrupt line to the interrupt controller is asserted for one clock cycle with the interrupt number asserted as well, see Figure \ref{fig:signal_irq_trap}.
Note, that an arbitrary time (and number of instructions) may take place between a trap and the interrupt handler execution.
\begin{figure}[htb]
\centering
\includegraphics[scale=1]{./figures/signal_irq_trap.pdf}
\caption{Signal Pattern for Trap Instruction}
\label{fig:signal_irq_trap}
\end{figure}

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\chapter{Memory}
The \procname is connected to the memory through a harvard architecture style interface.
While the interface to the instruction memory is read only, the data memory interface must handle read and write transactions simultaneously.
Externally, both instruction and data memory can be mapped to a Von-Neumann architecture.
The implemented Harvard architecture is more general and allows for two caches to be implemented.
\section{Endianess and Memory Width}
The memory width is defined in the \inlinevhdl{lt16x32\_internal} package.
Currently, memory widths of 32bits are supported only.
Of course, this memory width can be mapped to any other memory width by a memory controller.
The memory organizes data in big endian format.
This can be seen (and changed) in the memory controller, Listing \ref{lst:endianess}.
The same is valid for halfword-accesses.
\begin{vhdl}[Byte-Order in Memory]{lst:endianess}
case byteaddress is
when "00" =>
dmem_data(7 downto 0) <= word(7 downto 0);
when "01" =>
dmem_data(7 downto 0) <= word(15 downto 8);
when "10" =>
dmem_data(7 downto 0) <= word(23 downto 16);
when "11" =>
dmem_data(7 downto 0) <= word(31 downto 24);
\end{vhdl}
\section{Interface and Timing Description}
\subsection{Instruction Memory Interface}
The \procname is connected to the instruction memory through two ports, as seen in Listing \ref{lst:imem_interface}.
Their datatype definitions can be found in the \inlinevhdl{lt16x32\_global} package.
\begin{vhdl}[Instruction Memory Interface]{lst:imem_interface}
entity core is
port(
[...]
-- signals from instruction memory
in_imem : in imem_core;
-- signals to instruction memory
out_imem : out core_imem;
[...]
);
end entity core;
\end{vhdl}
\subsubsection{Read Access}
As all clocked signals in this design, the address and data signals to the instruction memory must be read on each rising clock edge.
Data must be provided if enable (\inlinevhdl{en}) is asserted and the memory content is read on the next rising clock edge.
This single data rate scheme allows for double data rate memory access to allow for pseudo-simultaneous data and instruction memory access.
A standard signal pattern can found in Figure \ref{fig:signal_imem}.
\begin{figure}[htb]
\centering
\includegraphics[scale=1]{./figures/signal_imem.pdf}
\caption{Signal Pattern for the Instruction Memory Interface}
\label{fig:signal_imem}
\end{figure}
\subsection{Data Memory Interface}
The \procname is connected to the data memory through two ports, as seen in Listing \ref{lst:dmem_interface}, their datatype definitions can be found in the \inlinevhdl{lt16x32\_global} package.
The data memory interface must be able to handle simultaneous read and write accesses, as these are performed in different pipeline stages and can overlap.
This is good for memory transaction performance but introduces a high memory load.
\begin{vhdl}[Data Memory Interface]{lst:dmem_interface}
entity core is
port(
[...]
-- signals from data memory
in_dmem : in dmem_core;
-- signals to data memory
out_dmem : out core_dmem;
[...]
);
end entity core;
\end{vhdl}
\subsubsection{Read Access}
The read access to the data memory is similar to the instruction memory interface and a standard signal pattern is shown in Figure \ref{fig:signal_imem}.
\subsubsection{Write Access}
In a write access, data and address are supplied at the same time and should be copied to the memory at the rising clock edge if enable is active, see Figure \ref{fig:signal_dmem_write}.
\begin{figure}[htb]
\centering
\includegraphics[scale=1]{./figures/signal_dmem_write.pdf}
\caption{Signal Pattern for Data Memory Write}
\label{fig:signal_dmem_write}
\end{figure}
\subsection{Memory Bandwidth Solutions}
As mentioned before, the very liberal memory interface demands high memory bandwidth.
In a worst-case scenario three memory accesses are needed per clockcycle (instruction read, data read and data write).
\subsubsection{Instruction Alignment}
Fortunately this worst-case scenario can be avoided by clever instruction alignment.
As standard instructions are 16bit wide and the instruction memory is organized
in 32bit words the instruction memory must be read only once every two clock cycles\footnote{Branching may introduce additional read operations.}.
If memory access instructions are now aligned in such a way, that read/write actions are performed when the instruction memory is idle, a simple single data rate memory is sufficient.
An exemplatory signal pattern is shown in Figure \ref{fig:signal_mem_interlacing}.
Note, that the instruction memory enable must be asserted the whole time,
but the memory controller does not need to read the actual memory,
as the address is changed only every second clock cycle.
\begin{figure}[htb]
\centering
\includegraphics[scale=1]{./figures/signal_mem_interlacing.pdf}
\caption{Signal Pattern for Memory Interlacing}
\label{fig:signal_mem_interlacing}
\end{figure}
\subsubsection{Processor Stalling}
If instruction alignment is too cumbersome or the memory is too slow for any other reason, it can deassert the ready signal (\inlinevhdl{ready}) to the processor (per interface).
If \inlinevhdl{ready} is deasserted, the processor is stalled and waits for \inlinevhdl{ready} to become asserted again.
\section{Memory Mapped I/O}
\label{sec:memmappedio}
In the concept of memory mapped input/output (I/O), the processor core does not distinguish between data memory transactions and transactions with other kinds of devices.
Writing to special memory addresses (i.e. outside of the memory range) are forwarded to a device, reading from these addresses means accessing the device's registers.
The systems memory is defined as follows:
\begin{itemize}
\item The instruction memory starts at address zero, its length should be configured to a word boundary.\footnote{The default component uses is configured using a word count.}
\item The data memory starts after the instruction memory, its length is also configurable and should also end on a word boundary.
\item The address space of the peripheral components starts at address \verb=0x000F0000=
\end{itemize}
\section{Memory Controller}
\label{sec:memoryctrl}
A generic memory controller named \verb=dmem= is given.
It has a size of 256 bytes, sectioned in four 64 byte blocks with an access size of one byte.
The default configuration is that its base address is directly after the instruction memory.
It can and should be used to maintain the stack, as frequent accesses to the instruction memory can slow down the performance.
The content of the memory at startup is undefined, and should not be used without initialization.

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%%
%% The original source files were:
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%% minted.dtx (with options: `package')
%% Copyright 2013--2014 Geoffrey M. Poore
%% Copyright 2010--2011 Konrad Rudolph
%%
%% This work may be distributed and/or modified under the
%% conditions of the LaTeX Project Public License, either version 1.3
%% of this license or (at your option) any later version.
%% The latest version of this license is in
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pdfkeywords={Processor,Firmware-based Verification,Architecture design}, %comma-seperated keywords
pdfproducer={Latex with hyperref},
pdfcreator={}]{hyperref}
\begin{document}
% \EN{\selectlanguage{english}}
% \DE{\selectlanguage{german}}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Here you have to start editing
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\title{\DocuTitle}
\author{Lasse Schnepel, Thomas Fehmel}
\date{2015}
\pagenumbering{arabic}
\hyphenation{Bit-ebenen Gateprop Bit-ebene Fanin Boole-sche
Partial-produkt-generator
Code-inspektion
Verifika-tions-ablauf
IPC-Verifika-tions-ablauf
Abhangig-keiten
}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% title page
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\frontmatter
\maketitle
\tableofcontents
\mainmatter
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Now this is followed by your chapters
% this usually starts with introduction and Fundamentals and then
% continues with whatever you need or did
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\input{socscope}
\input{socarch}
\input{architecture}
\input{instructionset}
\input{interrupts}
\input{memory}
\input{guides}
\backmatter
\listoffigures
\listoftables
%\listofcodefloat %triggers Errors for me, for whatever reason, but the pdf is generated nonetheless -TF
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\bibliographystyle{alphadin}
\bibliography{refs3}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\end{document}

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\chapter{SoC Architecture}\label{chap:socarch}
The supplied ESyLab-SoC plattform is implemented by the \verb=top.vhd=,
which can be found in the \verb=<project root>/soc/top= directory.
Its structure is illustrated by Figure~\ref{fig:socoverview}.
\begin{figure}[htb]
\centering
\includegraphics[scale=0.55]{./figures/soc_overview.pdf}
\caption{Block diagram of the ESyLab-SoC}
\label{fig:socoverview}
\end{figure}
The interface of the minimal top level entity of the \procname system is shown in Listing~\ref{lst:top_interface}.
\begin{vhdl}[Top Level Entity]{lst:top_interface}
entity lt16soc_top is
generic(
programfilename : string := "programs/program.ram"
);
port(
clk : in std_logic;
rst : in std_logic;
led : out std_logic_vector(7 downto 0)
);
end entity lt16soc_top;
\end{vhdl}
The inputs \inlinevhdl{clk}, which denote the clock input, and \inlinevhdl{rst}, which is the active high reset, are system-wide signals.
The minimal system features only one output signal, which is \inlinevhdl{led}.
This signal should be connected to a set of leds and is connected to a generic I/O-controller on the bus.
The individual components of the minimal system are described in the following sections.
\section{Interconnect}
\label{chap:socarch:interconnect}
The system utilizes a synchronous Wishbone bus.
To ease integration of new bus components, a Wishbone bus interconnect component is provided.
The interconnect module currently implements only the synchronous Whisbone protocol.
Its interface is given in Listing~\ref{lst:wb_interconnect_interface}.
\begin{vhdl}[Top Level Entity]{lst:wb_interconnect_interface}
entity wb_intercon is
generic(
slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := 0;
mst_mask_vector : std_logic_vector(0 to NWBMST-1) := 0
);
port(
clk : in std_logic;
rst : in std_logic;
msti : out wb_mst_in_vector;
msto : in wb_mst_out_vector;
slvi : out wb_slv_in_vector;
slvo : in wb_slv_out_vector
);
\end{vhdl}
The system is configured to a certain maximum number of slave and master modules as \inlinevhdl{NWBSLV} and \inlinevhdl{NWBMST} respectively.
The configuration can be found in \verb=config.vhd=.
These constants are used to define a the length of two generic parameters of the module,
the mask vectors \verb=slv_mask_vector= and \verb=mst_mask_vector=,
and also define how many elements the input and output arrays have.
As for the mask vectors, as indicated in the \verb=wishbone.vhd= file.
The mask vectors are used to indicate to the interconnect if a module should be connected to the input/output port indicated by the bit position in the mask vector.
A '1' at a position in the mask vector indicates that at the respective position in the the input/output arrays,
a module should be connected.
A '0' at a position in the mask vector will facilitate that the control logic for that position in the respective input/output array is omitted.
The inputs \inlinevhdl{clk} and \inlinevhdl{rst} are currently not used, but might be in the future when synchronous wishbone transfer is implemented.
The wishbone bus signals are separated in arrays of master and slave signals.
Array of master signals is in the output \inlinevhdl{msti}, which are the inputs to the connected masters, and the input \inlinevhdl{msto}, which are the outputs of the connected master.
Analogously, \inlinevhdl{slvi} and \inlinevhdl{slvo} follow the same principle for the connected slave modules.
\subsection{Integration of new components}
To instantiate a new component in the system,
a few steps must be undertaken.
\paragraph{The component declaration}%
should not be put in the top level module,
but in the appropriate package.
This makes the top level module more readable.
\paragraph{The component instantiation}%
in the top level module must be connected to the bus interconnect system.
To do this, the port map must connect its inputs and outputs of its bus interface to a free element of the \verb=slvi= and \verb=slvo= array signals in the top level architecture.
Any element in that vector must obviously only be assigned once.
To select to which of those signals you should connect,
consult the file \verb=soc/lib/config.vhd=.
A number of of slave index constants like shown in Listing~\ref{lst:config_constants} are defined there.
Add your own by adding one to the last defined constant,
then use the defined constant to select the element of the bus slave signal arrays, as illustrated in Listing.~\ref{lst:slave_port_assignment}.
\begin{vhdl}[Slave bus indexes]{lst:config_constants}
-- >> Slave index <<
constant CFG_MEM : integer := 0;
constant CFG_LED : integer := CFG_MEM+1;
constant CFG_DMEM : integer := CFG_LED+1;
...
\end{vhdl}
\begin{vhdl}[Slave bus connection]{lst:slave_port_assignment}
... port map( ...
wslvi => slvi(CFG_FOO),
wslvo => slvo(CFG_FOO)
...
\end{vhdl}
\paragraph{The slave masking vector}%
is a constant which configures the interconnect system to only consider certain slave bus interface elements.
A slave mask vector \verb=slv_mask_vector= is defined in the top level architecture, see Listing~\ref{lst:slave_mask}.
To enable any connection on the interconnect,
the bit in the slave mask vector must be set to '1' at the same position as the targeted elements in the slave connector arrays.
Setting any bit in the slave mask vector to '0' will disable the corresponding connection to the interconnection in the way that the logic to evaluate the inputs is not generated.
\begin{vhdl}[Slave bus indexes]{lst:slave_mask}
architecture RTL of lt16soc_top is
...
constant slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := b"1110_0000_0000_0000";
...
\end{vhdl}
\section{Processor Core Wrapper}
The processor core has a data and instruction memory interface, as per standard Harvard architecture.
The instruction memory interface is unchanged, but the data memory interface is wrapped in a piece of control logic translating the processor interface to wishbone signals and takes care of timing.
\section{Instruction memory}
The instruction memory component is configurable to load a file into its memory during elaboration.
The loaded file needs to contain legal values of the type std\_logic\_vector with a length of 32 characters per line.
If the content of the file is illegal, an error in the elaboration tool will likely occur.
It has two interfaces, one for instruction read access by the processor, one for a read and write access by the Wishbone bus.
The Wishbone interface takes priority over the instruction read.
The whole range of the memory can be written, so care should be exercised when writing to the instruction memory,
so code or 'constants' are not unintentionally overwritten.

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\chapter{Scope of Delivery}
\section{Products}
Containing in the ESyLab-SoC are the the processor core \procname,
a configurable Wishbone bus interconnect module,
a minimal interrupt controller and peripheral devices.
An instruction memory is also supplied.
It reads a file with machine code during elaboration,
so the SoC can both be simulated and synthesized.
The assembler to produce that machine code is also supplied in source.
\section{HowTo: Build Products}
\label{sec:scope_build}
The products are delivered as HDL source code.
This allows adaptation to any platform, for which the needed tools are available (see sections below).
\subsection{Processor}
The processor is delivered as a set of VHDL files, including one top entity (processor in \filename{processor.vhd}) which can be used in any VHDL synthesis tool.
For simulation, the entity \inlinevhdl{core\_tb} (in \filename{core\_tb.vhd}) can be used. Both architectures instantiate the core, a memory controller and a interrupt controller.
The filename of the used program can be set in these files in the generic map of the memory controller instantiation (see Listing \ref{lst:memory_file}).
Here, also the memory size can be determined (as number of stored words). For details on the memory controller see Section \ref{sec:memoryctrl}.
\begin{vhdl}[Generic Map Extract of Memory Controller]{lst:memory_file}
memory_inst : component memory
generic map(filename => "../programs/test.ram",
size => 32,
[...]
)
\end{vhdl}
The processor is wrapped in another module,
which implements the Wishbone bus-interface for the data memory interface of the processor.
\subsection{Bus Interconnect}
The bus interconnect system is configureable to any number of slave and master modules,
the appropriate configuration values (see Listing~\ref{lst:wishbone_config}) can be found in the file \verb=lib/wishbone.vhd=.
\begin{vhdl}[Wishbone interconnect configuration]{lst:wishbone_config}
...
constant NWBMST: integer :=4;
--Number of Wishbone master connectors on the Interconnect
constant NWBSLV: integer :=16;
--Number of Wishbone slave connectors on the Interconnect
...
\end{vhdl}
All connections can be masked during its instantiation,
using the slave and master mask vectors (see Listing~\ref{lst:wishbone_mask_config}).
They are declared in the top level architecture and are used during instantiation of the interconnection component.
\begin{vhdl}[Wishbone interconnect configuration]{lst:wishbone_mask_config}
...
constant slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := b"1110_0000_0000_0000";
constant mst_mask_vector : std_logic_vector(0 to NWBMST-1) := b"1000";
...
\end{vhdl}
The component handles synchronous Wishbone cycle termination.
\subsection{Assembler}
For building the assembler the GNU tools \filename{gcc}, \filename{make}, \filename{bison} and \filename{flex} are needed. With these tools installed, the \filename{make} script can be used to generate an executable called \filename{asm}:
\begin{verbatim}
($SOCROOT)/assembler/$ make all
\end{verbatim}
It is recommended to either copy or dynamically link the assembler executable in a directory in your \verb=$PATH= or directly referenced by in your build tool chain.

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AS=../assembler/asm
RM= rm -f
SRCS= $(wildcard *.prog)
OBJS= $(SRCS:.prog=.ram)
MAPS= $(SRCS:.prog=.map)
all: $(OBJS)
maps: $(MAPS)
%.ram: %.prog
$(AS) $< -o $@
%.map: %.prog
$(AS) $< -m $@ -o $*.ram
clean:
$(RM) $(OBJS) $(MAPS)
.PHONY: all maps

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reset:
br always >main
nop
hardfault:
reti
nop
memfault:
reti
nop
.align
addr:
.word 0x000F0000
w_cnt_top: .word 0x1FC000
//w_cnt_top: .word 0x1 //for simulation only
main:
ldr r0,>addr //LED addr
addi r6,8 //outer counter top
clr r7 //wait counter
ldr r8,>w_cnt_top
out_loop:
clr r1
st08 r0,r1
call >wait
nop
fill:
lsh r1,r1,1
addi r1,1
st08 r0,r1
call >wait
nop
addi r5,1
cmp neq r5,r6
br true >fill
nop
clr r5
flush:
lsh r1,r1,1
st08 r0,r1
call >wait
nop
addi r5,1
cmp neq r5,r6
br true >flush
nop
clr r5
br always >out_loop
nop
//subroutine to iterate until counter overflow
wait:
clr r7 //inititalize inner counter
inc_i:
cmp neq r7,r8
br true >inc_i //if i=cnt_top
addi r7,1
ret //else
nop

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//big endian data memory test
//after the initialization, should the LED become a value differnt from 0, an error occured
reset:
br always >main
nop
hardfault:
reti
nop
memfault:
reti
nop
.align
pointer:
.word =constants
constants:
.word 256
.word 0x00010203
.word 0x04040404
.word 0x000000FF
main:
clr r10
call_1:
clr r0 //error msg / state
call always >echo_error
nop
ldr r11,>pointer
ld32 r1,r11 //DMEM addr
addi r11,4
ld32 r2,r11
addi r11,4
ld32 r3,r11 //increment
addi r11,4
ld32 r8,r11 //mask
addi r11,-12
//test 1: store 32 bit, load bytes
test1:
mov r4,r2
st32 r1,r4
addi r1,3 //check the LSB first
ld08 r6,r1 //r6: loaded value
and r5,r4,r8 //r5: masked constant
cmp neq r5,r6
call true >echo_error
addi r10,1
addi r1,-1
rsh r4,r4,8
ld08 r6,r1 //r6: loaded value
and r5,r4,r8 //r5: masked constant
cmp neq r5,r6
call true >echo_error
addi r10,1
addi r1,-1
rsh r4,r4,8
ld08 r6,r1 //r6: loaded value
and r5,r4,r8 //r5: masked constant
cmp neq r5,r6
call true >echo_error
addi r10,1
addi r1,-1
rsh r4,r4,8
ld08 r6,r1 //r6: loaded value
and r5,r4,r8 //r5: masked constant
cmp neq r5,r6
call true >echo_error
addi r10,1
//test 1 end
add r2,r2,r3
addi r1,4
//test 2: store bytes, load word
test2:
mov r4,r2
addi r1,3
st08 r1,r4
rsh r4,r4,8
addi r1,-1
st08 r1,r4
rsh r4,r4,8
addi r1,-1
st08 r1,r4
rsh r4,r4,8
addi r1,-1
st08 r1,r4
rsh r4,r4,8
ld32 r6,r1
cmp neq r6,r2
call true >echo_error
addi r10,1
ldr r9,>LEDaddr
st08 r9,r8
//test 3
// prewrite memory with value==baseaddress+offset,
// load 32 bit values and check if correct
test3:
ld32 r1,r11 //DMEM base address
add r8,r1,r1 //out-of-range address, incidentally equals baseaddress*2 since baseaddress==length
clr r2
test3_prewrite_mem_loop:
st08 r1,r2
addi r1,1
cmp neq r1,r8
br true >test3_prewrite_mem_loop
addi r2,1
ld32 r1,r11 //DMEM addr
addi r11,4
ld32 r2,r11 //CMP value
addi r11,4
ld32 r3,r11 //increment
addi r11,-8
add r8,r1,r1 //out-of-range address, incidentally equals baseaddress*2 since baseaddress==length
test3_loop:
ld32 r4,r1
cmp neq r4,r2
call true >echo_error
addi r0,1
addi r1,4
add r2,r2,r3
cmp neq r1,r8
br true >test3_loop
nop
//end test3
end:
nop
br >end
nop
.align
LEDaddr:
.word 0x000F0000
//expects an error code in r0
echo_error:
nop
ldr r9,>LEDaddr
st08 r9,r0
ret
nop

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// Interrupt Table
reset: br >main
nop
hardfault: br >hardfault_handler
nop
memfault: br >memfault_handler
nop
irq3: br >irq3_handler
nop
// Main Function
main:
ldr sp, >sp_init
clr sr
// endless loop to stop program
final:
br >final
nop
// Interrupt Handler
hardfault_handler:
reti
memfault_handler:
reti
irq3_handler:
reti
// Constant Declaration
.align
sp_init: .word 0x400 // Stackpointer Initial Value

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//
// This program let's the connected LEDs flash
// with a duty cycle of 50% and
// a period of approx. 1s
//
// r0: counter top
// r1: counter
// r2: LED address
// r3: ones (0xFF)
// r4: LED values
irq0: br always >main
nop
// initialization constants
.align
sp_init: .word 0x200 // Stack pointer
top: .word 16000000 // Counter top
ptr: .word 0x0 // pointer to I/O device
// main procedure
main:
// init registers
ldr sp, >sp_init
ldr r0, >top
ldr r2, >ptr
clr r1
clr r3
clr r4
addi r3, -1
// loop
loop:
cmp neq r1, r0
br true >loop // loop if not equal (BDS!)
addi r1, 1 // increment counter
// counter top reached, set LEDs and clear counter
xor r4, r4, r3 // invert last byte of r4
st08 r2, r4 // write byte to I/O device
br always >loop // branch back to loop (BDS!)
clr r1 // reset counter
nop
nop

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reset: br always >reset
nop

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addi r0,0x50
addi r1,7
st08 r0,r1
nop
nop
clr r1
ld08 r2,r0
nop
nop
st08 r3,r2
nop
end:
nop
br always >end
nop

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addi r0,0x50
addi r1,-3
nop
nop
st16 r0,r1
nop
nop
clr r1
ld16 r2,r0
nop
nop
st16 r3,r2
nop
end:
nop
br always >end
nop

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addi r0,0x50
addi r1,-3
nop
nop
st32 r0,r1
nop
nop
clr r1
ld32 r2,r0
nop
nop
st32 r3,r2
nop
end:
nop
br always >end
nop

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main:
ldr r0, >dmemaddr
clr r1
nop
st08 r1,r0
br always >main
nop
.align
dmemaddr: .word 0xFFFF

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reset:
br always >main
nop
hardfault:
reti
nop
memfault:
reti
nop
.align
addr: .word 0x000F0000
//w_cnt_top: .word 0x717D7840 //250 ms @ 100MHz
w_cnt_top: .word 0x40 //for simulation only
main:
ldr r0,>addr //LED addr
addi r6,8 //outer counter top
clr r7 //wait counter
ldr r8,>w_cnt_top
out_loop:
clr r1
st08 r0,r1
call >wait
nop
fill:
lsh r1,r1,1
addi r1,1
st08 r0,r1
call >wait
nop
addi r5,1
cmp neq r5,r6
br true >fill
nop
clr r5
flush:
lsh r1,r1,1
st08 r0,r1
call >wait
nop
addi r5,1
cmp neq r5,r6
br true >flush
nop
clr r5
br always >out_loop
nop
//subroutine that iterates until counter overflow
wait:
clr r7 //inititalize inner counter
inc_i:
cmp neq r7,r8
br true >inc_i //if i=cnt_top
addi r7,1
reti //else
nop

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addi r0,0
addi r1,0
addi r2,127
add r2,r2,r2
add r2,r2,r2
add r2,r2,r2
add r2,r2,r2
add r2,r2,r2
add r2,r2,r2
add r2,r2,r2
add r2,r2,r2
add r2,r2,r2
add r2,r2,r2
addi r3,7
st08 r0,r3
clr r3
loopout:
loopin:
addi r1,1
cmp neq r2,r1
br true >loopin
nop
clr r1
addi r3,1
st08 r0,r3
br always >loopout
nop

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reset:
br >main
nop
hardfault:
reti
nop
memfault:
reti
nop
.align
adr_a: .word 0x3C0 // actual adr at mem 0xF0 (0x3C0>>2 bits)
adr_b: .word 0x3F0 // actual adr at mem 0xFC (0x3F0>>2 bits)
main:
ldr r5, >adr_a
//wait for one cycle after a load is necessary
nop
ldr r1, >adr_b
addi r6,-2
addi r8, 0x50
nop
st32 r5, r6
//waiting for one cycle when re-accessing a stored value is in accordance with design
nop
ld32 r7,r5
addi r9,0x50
ld32 r8,r5
addi r8,1
st32 r5,r8
end: br always >end
nop

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reset: br >main
nop
hardfault: reti
nop
memfault: reti
nop
.align
adr_a: .word 0x3C0 // (30b adr), actual adr at mem 0xF00 (0x3C0<<2 bits)
adr_b: .word 0x3F0 // (30b adr), actual adr at mem 0xFC0 (0x3F0<<2 bits)
main:
clr r0
clr r1
clr r2
clr r3
//------------------------------
// read only ins test
//------------------------------
addi r1, 0x01 //expected r1 = 0x01
addi r2, 0x02 //expected r1 = 0x02
add r0, r1, r2 // expected r0 = 0x03
add r3, r0, r1 // expected r3 = 3 + 1 = 0x4
end: br always >end
nop

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reset: br >main
nop
hardfault: reti
nop
memfault: reti
nop
.align
adr_i0: .word 0x001 // (30b adr), actual adr at mem 0x004 (0x001<<2 bits)
adr_a: .word 0x3C0 // (30b adr), actual adr at mem 0xF00 (0x3C0<<2 bits)
adr_b: .word 0x3F0 // (30b adr), actual adr at mem 0xFC0 (0x3F0<<2 bits)
main:
clr r0
clr r1
clr r2
clr r3
//------------------------------
// read only mem from ins addr range
//------------------------------
addi r3, 0x10 //32 bit adr
ld32 r0, r3 // val at addr 0x04 (30 bits) = 0x000003C0 (b0 = x00, b1 = x00, b2 = x03, b3 = xC0)
add r1, r0, r0 //expected r1 = 0x3C0 + 0x3C0 = 780
addi r4, 0x12
ld08 r5, r4 // get Byte2, r5 = 0x03
end: br always >end
nop

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reset: br >main
nop
hardfault: reti
nop
memfault: reti
nop
.align
adr_a: .word 0x3C0 // (30b adr), actual adr at mem 0xF00 (0x3C0<<2 bits)
adr_b: .word 0x3F0 // (30b adr), actual adr at mem 0xFC0 (0x3F0<<2 bits)
adr_c: .word 0x09
main:
//------------------------------
// read only mem from ins addr range
//------------------------------
addi r3, 0x10 //32 bit adr
ld32 r0, r3 // val at addr 0x04 (30 bits) = 0x000003C0 (b0 = x00, b1 = x00, b2 = x03, b3 = xC0)
add r1, r0, r0 //expected r1 = 0x3C0 + 0x3C0 = 780
addi r4, 0x12
ld08 r5, r4 // get Byte2, r5 = 0x03
//------------------------------
// write mem test
//------------------------------
addi r8, 0x77
addi r7, 0x51 //32 bit adr , write to Byte 1 > xx77_xxxx at mem[0x14]
st08 r7, r8
end: br always >end
nop

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programs/simple.prog Normal file
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reset: br >main
nop
hardfault: reti
nop
memfault: reti
nop
main: // actual start of program
clr r0
clr r1
clr r2
clr r3
clr r4
//test move = or
addi r0, 0x55 // expected r0 = 0x55
mov r1, r0 // expected r1 = 0x55
//test shift
addi r2, 0x0A //expected r2 = 0x0A
lsh r3, r2, 16 //expected r3 = 0xA_0000
lsh r3, r3, 12 //expected r3 = 0xA000_0000
// test write
ldr r4, >adr_a //expected r4 = 0x3C0
st32 r4, r3 //expected value at addr 0xF00 = 0xA000_0000
end: br always >end
nop
.align
adr_a: .word 0x3C0 // actual adr at mem 0xF00 (0x3C0<<2 bits)
//adr_a: .word 0x3F8
//adr_a: .word 0x20C

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reset:
br always >main
nop
hardfault:
br always >main
reti
memfault:
br always >main
reti
.align
t1: .word 0xA0B0C0D0
t2: .word 0xF0AB2FB9
t3: .word 0xCCCCCCCC
adr1: .word 0x150
adr2: .word 0x144
adr3: .word 0x10F
main:
ldr r1, >adr1
ldr r2, >adr2
ldr r3, >adr3
addi r0,-1
ldr r4,>t1
st16 r1,r0 //mem() = 0x0000FFFF
st08 r2,r0 //mem() = 0x000000FF
st32 r3,r0 //mem() = 0xFFFFFFFF
ldr r11,>t1
ldr r10,>t2
ldr r9,>t3
ldr r7,>t1
ldr r6,>t2
ld16 r11,r1
ld08 r10,r2
ld32 r9,r3
end:
br always >end
nop

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irq0:
br always >main
nop
irq1:
br always >irq
nop
irq2:
br always >irq
nop
main:
ldr sp, >sp_init
nop
clr sr
addi r2, 1
addi r2, 2
addi r2, 3
trap 1
addi r2, 4
addi r2, 5
loop:
addi r10, 1
foo: br always >loop
nop
end: br always >end
nop
irq: addi r0, 5
reti
nop
.address 100
.word 499
sp_init: .word 500
.word 501

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//
// This program let's the connected LEDs flash
// with a duty cycle of 50%.
//
// r0: counter top
// r1: counter
// r2: LED address
// r3: ones (0xFF)
// r4: LED values
irq0: br always >main
nop
// initialization constants
.align
sp_init: .word 0x200 // Stack pointer
top: .word 160000 // Counter top
ptr: .word 0x0 // pointer to I/O device
// main procedure
main:
// init registers
ldr sp, >sp_init
ldr r0, >top
ldr r2, >ptr
clr r1
clr r3
clr r4
addi r3, -1
// loop
loop:
cmp neq r1, r0
br true >loop // loop if not equal (BDS!)
addi r1, 1 // increment counter
// counter top reached, set LEDs and clear counter
xor r4, r4, r3 // invert last byte of r4
st08 r2, r4 // write byte to I/O device
br always >loop // branch back to loop (BDS!)
clr r1 // reset counter
nop
nop

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reset: br >main
nop
hardfault: reti
nop
memfault: reti
nop
irq3: br >irq_handler
nop
main: // actual start of program
ldr sp, >sp_init
ldr r1, >startvalue
clr r2
clr sr
test: mov r1, pc
loop: addi r2, 1
cmp ll r2, r1
br true >loop
nop
cmp le r2, r1
call true >final
addi r3, 1
end: br >end
nop
final: addi r10, 1
cmp eq r10, r1
ret true
nop
br >final
nop
irq_handler: addi r4, 1
reti
nop
nop
nop
nop
.align
sp_init: .word 1020
startvalue: .word 15

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reset: br >main
nop
hardfault: reti
nop
memfault: reti
nop
main: // actual start of program
ldr sp, >sp_init
clr r5
clr r6
clr r7
clr r8
clr r9
ldr r0, >addr
addi r1, 0x01
st08 r0, r1
ld08 r5, r0
addi r0, 1
addi r1, 1
st08 r0, r1
ld08 r6, r0
addi r0, 1
addi r1, 1
st08 r0, r1
ld08 r7, r0
addi r0, 1
addi r1, 1
st08 r0, r1
ld08 r8, r0
addi r0, 1
addi r1, 1
st08 r0, r1
ld08 r9, r0
.align
sp_init: .word 1020 // 0x3FC
addr: .word 0x101

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reset: br >main
nop
hardfault: reti
nop
memfault: reti
nop
main: // actual start of program
ldr sp, >sp_init
clr r5
clr r6
clr r7
clr r8
clr r9
ldr r0, >addr
addi r1, 0x01
st32 r0, r1
ld32 r5, r0
addi r0, 1
addi r1, 1
st32 r0, r1
ld32 r6, r0
addi r0, 1
addi r1, 1
st32 r0, r1
ld32 r7, r0
addi r0, 1
addi r1, 1
st32 r0, r1
ld32 r8, r0
addi r0, 1
addi r1, 1
st32 r0, r1
ld32 r9, r0
.align
sp_init: .word 1020 // 0x3FC
addr: .word 0x101

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reset: br >main
nop
hardfault: reti
nop
memfault: reti
nop
.align
sp_init: .word 0x400 // Stackpointer Initial Value
main:
ldr sp, >sp_init
clr sr
//base addr
add r0,r0,sp
//addi r0,0x40
addi r10,4
add r1,r0,r10
add r2,r1,r10
//values t.b. stored
addi r3,-1
addi r4,-2
addi r5,-3
//store values
st32 r0,r3
st32 r1,r4
st32 r2,r5
//retrieve values
ld32 r6,r0
ld32 r7,r1
ld32 r8,r2
nop
nop
nop
nop
ld32 r6,r0
st32 r1,r6
ld32 r7,r0
ld32 r7,r0
st32 r1,r6
st32 r1,r6
ld32 r7,r0
end:
br always >end
nop

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projects/lt16lab/.gitignore vendored Normal file
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### TEX Temps
*.out
*.toc
*.aux
*.log
*.pdf
*.synctex.gz
*.lof
*.lot
*.lol
*.dvi
*.bbl
*.ps
*.blg
*.loc
*.pyg
### Other Files
*~
*.kate-swp
*.patch
*.orig
### Assembler Eclipse Stuff
assembler/.cproject
assembler/.project
assembler/.settings/org.eclipse.cdt.managedbuilder.core.prefs
### Assembler Project Compiles
assembler/obj/*
assembler/asm
assembler/test.ram
assembler/test.map
### test program files
*.ram
*.map

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-- See the file "LICENSE" for the full license governing this code. --
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.lt16x32_internal.all;
-- the ALU offers various two-input arithmetic and logic operations and is fully combinatoric
entity alu is
port(
-- Data Input
in_a : in signed(reg_width - 1 downto 0);
in_b : in signed(reg_width - 1 downto 0);
-- Truth Flag
t_out : out std_logic;
-- Overflow Flag
ovf_out : out std_logic;
-- Mode of Operation
mode : in alu_mode_type;
-- Data Output
data_out : out signed(reg_width - 1 downto 0)
);
end entity alu;
architecture RTL of alu is
begin
-- calculate the result
calc_out : process(in_a, in_b, mode) is
-- used to store the result temporarily (e.g. if needed for flag calculation)
variable result : signed(reg_width - 1 downto 0);
begin
-- default outputs
data_out <= (others => '0');
ovf_out <= '0';
t_out <= '0';
-- different result for each mode
case mode is
-- arithmetic modes
when alu_add => -- addition
result := in_a + in_b;
data_out <= result;
ovf_out <= (in_a(reg_width - 1) AND in_b(reg_width - 1) AND not result(reg_width - 1)) OR (not in_a(reg_width - 1) AND not in_b(reg_width - 1) AND result(reg_width - 1));
when alu_sub => -- subtraction
result := in_a - in_b;
data_out <= result;
ovf_out <= (in_a(reg_width - 1) AND not in_b(reg_width - 1) AND not result(reg_width - 1)) OR (not in_a(reg_width - 1) AND in_b(reg_width - 1) AND result(reg_width - 1));
when alu_and => -- bitwise and
data_out <= in_a and in_b;
when alu_or => -- bitwise or
data_out <= in_a or in_b;
when alu_xor => -- bitwise xor
data_out <= in_a xor in_b;
when alu_lsh => -- logic left shift
data_out <= in_a sll (to_integer(unsigned(in_b(3 downto 0))) + 1);
when alu_rsh => -- logic right shift
data_out <= in_a srl (to_integer(unsigned(in_b(3 downto 0))) + 1);
-- compare modes
when alu_cmp_eq => -- compare for A = B
if (in_a = in_b) then
t_out <= '1';
else
t_out <= '0';
end if;
when alu_cmp_neq => -- compare for not equal
if (in_a /= in_b) then
t_out <= '1';
else
t_out <= '0';
end if;
when alu_cmp_ge => -- compare for greater than or equal
if (in_a >= in_b) then
t_out <= '1';
else
t_out <= '0';
end if;
when alu_cmp_gg => -- compare for greater than
if (in_a > in_b) then
t_out <= '1';
else
t_out <= '0';
end if;
when alu_cmp_le => -- compare for less than or equal
if (in_a <= in_b) then
t_out <= '1';
else
t_out <= '0';
end if;
when alu_cmp_ll => -- compare for less than
if (in_a < in_b) then
t_out <= '1';
else
t_out <= '0';
end if;
when alu_cmp_true => -- always set truth-flag
t_out <= '1';
when alu_cmp_false => -- always reset truth-flag
t_out <= '0';
end case;
end process calc_out;
end architecture RTL;

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-- See the file "LICENSE" for the full license governing this code. --
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.lt16x32_internal.all;
-- the controlpath mostly covers the pipelining of control signals, but also includes some "glue"-logic
entity controlpath is
port(
-- clock signal
clk : in std_logic;
-- reset signal, active high, synchronous
rst : in std_logic;
-- stall signal, active high
stall : in std_logic;
-- signals from decoder
in_dec : in dec_cp;
-- signals to decoder
out_dec : out cp_dec;
-- signals to datapath
out_dp : out cp_dp;
-- signals to PC counter
out_pc : out cp_pc;
-- signals to data memory
out_dmem : out cp_dmem;
-- signals from datapath
in_dp : in dp_cp;
-- hardfault, active high
hardfault : out std_logic
);
end entity controlpath;
architecture RTL of controlpath is
-- pipelined signals
-- decoder information for dp-stage 2 in stage 2
signal in_dec_2_s2 : dec_cp_s2;
-- decoder information for dp-stage 3 in stage 2
signal in_dec_3_s2 : dec_cp_s3;
-- decoder information for dp-stage 3 in stage 3
signal in_dec_3_s3 : dec_cp_s3;
begin
-- forward internal signals to ports
hardfault <= in_dec.hardfault;
out_pc.instruction_width <= in_dec.s1.instruction_width;
out_dp.s1.register_read_number_a <= in_dec.s1.register_read_number_a;
out_dp.s1.register_read_number_b <= in_dec.s1.register_read_number_b;
out_dp.s2.alu_input_data_select <= in_dec_2_s2.alu_input_data_select;
out_dp.s2.alu_mode <= in_dec_2_s2.alu_mode;
out_dp.s2.immediate <= in_dec_2_s2.immediate;
out_dp.s2.memory_read_addr_select <= in_dec_2_s2.dmem_read_addr_select;
out_dmem.read_en <= in_dec_2_s2.dmem_read_en;
out_dmem.read_size <= in_dec_2_s2.dmem_read_size;
out_dmem.write_en <= in_dec_3_s3.dmem_write_en;
out_dmem.write_size <= in_dec_3_s3.dmem_write_size;
out_dp.s3.ovfflag_write_enable <= in_dec_3_s3.ovfflag_write_enable;
out_dp.s3.memory_write_data_select <= in_dec_3_s3.dmem_write_data_select;
out_dp.s3.register_write_data_select <= in_dec_3_s3.register_write_data_select;
out_dp.s3.register_write_enable <= in_dec_3_s3.register_write_enable;
out_dp.s3.register_write_number <= in_dec_3_s3.register_write_number;
out_dp.s3.register_write_size <= in_dec_3_s3.register_write_size;
out_dp.s3.tflag_write_data_select <= in_dec_3_s3.tflag_write_data_select;
out_dp.s3.tflag_write_enable <= in_dec_3_s3.tflag_write_enable;
-- pipeline register stage 1 -> 2
pipeline_s1_s2 : process(clk) is
begin
if (rising_edge(clk)) then
if (rst = '1') then
in_dec_2_s2 <= get_default_dec_cp_s2;
in_dec_3_s2 <= get_default_dec_cp_s3;
elsif (stall = '0') then
in_dec_2_s2 <= in_dec.s2;
in_dec_3_s2 <= in_dec.s3;
end if;
end if;
end process pipeline_s1_s2;
-- pipeline register stage 2 -> 3
pipeline_s2_s3 : process(clk) is
begin
if (rising_edge(clk)) then
if (rst = '1') then
in_dec_3_s3 <= get_default_dec_cp_s3;
elsif (stall = '0') then
in_dec_3_s3 <= in_dec_3_s2;
end if;
end if;
end process pipeline_s2_s3;
-- PC signal combinatorics and condition holds flag for decoder
pc_comb : process(in_dec_2_s2.pc_summand_select, in_dec_2_s2.pc_mode_select, in_dec_2_s2.pc_condition, in_dp.s2.tflag) is
begin
case in_dec_2_s2.pc_condition is
when sel_unconditional =>
-- without condition, always use proposed pc options
out_pc.summand_select <= in_dec_2_s2.pc_summand_select;
out_pc.mode_select <= in_dec_2_s2.pc_mode_select;
out_dec.condition_holds <= '1';
when sel_true =>
-- with condition = true
if (in_dp.s2.tflag = '1') then
-- if condition is true (as needed), use proposed pc options
out_pc.summand_select <= in_dec_2_s2.pc_summand_select;
out_pc.mode_select <= in_dec_2_s2.pc_mode_select;
out_dec.condition_holds <= '1';
else
-- if condition is false (opposed to what is needed) resume normal pc operation
out_pc.summand_select <= sel_run;
out_pc.mode_select <= sel_relative;
out_dec.condition_holds <= '0';
end if;
end case;
end process pc_comb;
end architecture RTL;

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-- See the file "LICENSE" for the full license governing this code. --
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.lt16x32_internal.all;
use work.lt16x32_global.all;
-- the core bundles all entities inside the core itself
entity core is
port(
-- clock signal
clk : in std_logic;
-- reset signal, active high, synchronous
rst : in std_logic;
-- external stall signal, active high, synchronous
stall : in std_logic;
-- signals from data memory
in_dmem : in dmem_core;
-- signals to data memory
out_dmem : out core_dmem;
-- signals from instruction memory
in_imem : in imem_core;
-- signals to instruction memory
out_imem : out core_imem;
-- signals from interrupt controller
in_irq : in irq_core;
-- signals to interrupt controller
out_irq : out core_irq;
-- hardfault signal, active high
hardfault : out std_logic
);
end entity core;
architecture RTL of core is
component datapath
port(clk : in std_logic;
rst : in std_logic;
stall : in std_logic;
out_dec : out dp_dec;
in_cp : in cp_dp;
out_cp : out dp_cp;
in_pc : in pc_dp;
out_pc : out dp_pc;
in_dmem : in dmem_dp;
out_dmem : out dp_dmem;
hardfault : out std_logic);
end component datapath;
component controlpath
port(clk : in std_logic;
rst : in std_logic;
stall : in std_logic;
in_dec : in dec_cp;
out_dec : out cp_dec;
out_dp : out cp_dp;
out_pc : out cp_pc;
out_dmem : out cp_dmem;
in_dp : in dp_cp;
hardfault : out std_logic);
end component controlpath;
component decoder
port(clk : in std_logic;
rst : in std_logic;
stall : in std_logic;
in_imem : in imem_dec;
in_dp : in dp_dec;
in_cp : in cp_dec;
out_cp : out dec_cp;
out_pc : out dec_pc;
out_imem : out dec_imem;
in_irq : in irq_dec;
out_irq : out dec_irq);
end component decoder;
component programcounter
port(clk : in std_logic;
rst : in std_logic;
stall : in std_logic;
in_cp : in cp_pc;
in_dp : in dp_pc;
in_dec : in dec_pc;
out_dp : out pc_dp;
out_imem : out pc_imem);
end component programcounter;
-- signals between instances
signal dp_cp_signal : dp_cp;
signal dp_dmem_signal : dp_dmem;
signal dmem_dp_signal : dmem_dp;
signal imem_dec_signal : imem_dec;
signal dec_cp_signal : dec_cp;
signal dec_imem_signal : dec_imem;
signal cp_dp_signal : cp_dp;
signal cp_dmem_signal : cp_dmem;
signal cp_dec_signal : cp_dec;
signal pc_dp_signal : pc_dp;
signal dp_pc_signal : dp_pc;
signal dec_pc_signal : dec_pc;
signal pc_imem_signal : pc_imem;
signal cp_pc_signal : cp_pc;
signal irq_dec_signal : irq_dec;
signal dec_irq_signal : dec_irq;
signal dp_dec_signal : dp_dec;
signal hardfault_dp : std_logic;
signal hardfault_cp : std_logic;
-- general halt signal
signal stall_internal : std_logic;
begin
-- configuration tests
-- irq_num_width must be smaller than or equal to 6 to fit into first byte of SR
assert (irq_prio_width <= 6) report "irq_prio_width must be <= 6." severity failure;
-- irq_num_width must fit into immediate
assert (irq_num_width < dec_cp_signal.s2.immediate'high) report "irq_num_width must be <= " & integer'image(dec_cp_signal.s2.immediate'high - 1) & "." severity failure;
-- reg_width must be 8, 16 or 32bit
assert ((reg_width = 8) or (reg_width = 16) or (reg_width = 32)) report "selected reg_width is not allowed. allowed values are 8, 16, 32, 64." severity failure;
-- pc must fit into register
assert (pc_width <= reg_width) report "pc_width must be smaller than or equal to reg_width." severity failure;
-- component instantiation
datapath_inst : component datapath
port map(clk => clk,
rst => rst,
stall => stall_internal,
out_dec => dp_dec_signal,
in_cp => cp_dp_signal,
out_cp => dp_cp_signal,
in_pc => pc_dp_signal,
out_pc => dp_pc_signal,
in_dmem => dmem_dp_signal,
out_dmem => dp_dmem_signal,
hardfault => hardfault_dp);
controlpath_inst : component controlpath
port map(clk => clk,
rst => rst,
stall => stall_internal,
in_dec => dec_cp_signal,
out_dec => cp_dec_signal,
out_dp => cp_dp_signal,
out_pc => cp_pc_signal,
out_dmem => cp_dmem_signal,
in_dp => dp_cp_signal,
hardfault => hardfault_cp);
decoder_inst : component decoder
port map(clk => clk,
rst => rst,
stall => stall_internal,
in_imem => imem_dec_signal,
in_dp => dp_dec_signal,
in_cp => cp_dec_signal,
out_cp => dec_cp_signal,
out_pc => dec_pc_signal,
out_imem => dec_imem_signal,
in_irq => irq_dec_signal,
out_irq => dec_irq_signal);
programcounter_inst : component programcounter
port map(clk => clk,
rst => rst,
stall => stall_internal,
in_cp => cp_pc_signal,
in_dp => dp_pc_signal,
in_dec => dec_pc_signal,
out_dp => pc_dp_signal,
out_imem => pc_imem_signal);
-- signals from data memory
dmem_dp_signal.read_data <= in_dmem.read_data;
-- signals to data memory
out_dmem.read_addr <= dp_dmem_signal.read_addr;
out_dmem.read_size <= to_stdlogicvector(cp_dmem_signal.read_size);
out_dmem.write_addr <= dp_dmem_signal.write_addr;
out_dmem.write_data <= dp_dmem_signal.write_data;
out_dmem.write_size <= to_stdlogicvector(cp_dmem_signal.write_size);
-- dmem read enable is overwritten if stall is active
dmem_read_en : with stall select out_dmem.read_en <=
'0' when '1',
cp_dmem_signal.read_en when others;
-- dmem write enable is overwritten if stall is active
dmem_write_en : with stall select out_dmem.write_en <=
'0' when '1',
cp_dmem_signal.write_en when others;
-- signals from instruction memory
imem_dec_signal.read_data <= in_imem.read_data;
imem_dec_signal.ready <= in_imem.ready;
-- signals to instruction memory
-- fill imem address, if pc width is smaller than memory width
-- all warnings of the type "Null range" can be safely ignored for pc_width = mem_width
imem_addr_fill : if (pc_width < mem_width) generate
out_imem.read_addr(mem_width - 1 downto pc_width) <= (others => '0');
end generate imem_addr_fill;
out_imem.read_addr(pc_width - 1 downto 0) <= std_logic_vector(pc_imem_signal.value);
-- imem read enable is overwritten if stall is active
imem_read_en : with stall_internal select out_imem.read_en <=
'0' when '1',
dec_imem_signal.en when others;
-- the halfword flag needs a delay as it refers to last clock cycles imem address
-- (the corresponding data is read in this clock cycle)
halfword_delay : process(clk) is
begin
if (rising_edge(clk)) then
if (rst = '1') then
-- reset to zero
imem_dec_signal.instruction_halfword_select <= '0';
elsif (stall_internal = '0') then
-- set to pc_value(1)
imem_dec_signal.instruction_halfword_select <= pc_imem_signal.value(1);
--! else? --TF
end if;
end if;
end process halfword_delay;
-- signals from interrupt controller
irq_dec_signal.num <= in_irq.num;
irq_dec_signal.priority <= in_irq.priority;
irq_dec_signal.req <= in_irq.req;
irq_dec_signal.nmi <= in_irq.nmi;
-- signals to interrupt controller
out_irq.ack <= dec_irq_signal.ack;
out_irq.trap_num <= dec_irq_signal.trap_num;
out_irq.trap_req <= dec_irq_signal.trap_req;
-- stall if dmem not ready, imem not ready is handled in decoder_fsm
stall_internal <= (not in_dmem.ready) or stall;
-- hardfault logic
hardfault <= hardfault_cp or hardfault_dp;
end architecture RTL;

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-- See the file "LICENSE" for the full license governing this code. --
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.lt16x32_internal.all;
use work.lt16x32_global.all;
use work.wishbone.all;
use work.config.all;
entity core2wb is
port(
clk : in std_logic;
rst : in std_logic;
in_dmem : out dmem_core;
out_dmem : in core_dmem;
-- wb master port
wmsti : in wb_mst_in_type;
wmsto : out wb_mst_out_type
);
end core2wb;
architecture Behavioral of core2wb is
signal msto : wb_mst_out_type := wbm_out_none;
type STATE_TYPE IS (ONEACC, SIMACCWR, SIMACCRD);
signal state, nstate: STATE_TYPE;
begin
reg: process(clk)
begin
if rst = '1' then
state <= ONEACC;
in_dmem.read_data <= (others => '0');
elsif rising_edge(clk) then
state <= nstate;
if wmsti.ack = '1' then
in_dmem.read_data <= dec_wb_dat(msto.sel, wmsti.dat);
end if;
end if;
end process;
nscl: process(state, out_dmem, wmsti.ack)
begin
case state is
when ONEACC =>
if out_dmem.read_en = '1' and out_dmem.write_en = '1' then
nstate <= SIMACCWR;
else
nstate <= state;
end if;
when SIMACCWR =>
if wmsti.ack = '1' then
nstate <= SIMACCRD;
else
nstate <= state; -- wait til get ack from wr request
end if;
when SIMACCRD =>
if wmsti.ack = '1' then -- read_ack
nstate <= ONEACC;
else
nstate <= state; -- feed the old read value from previous sim request
end if;
end case;
end process;
ocl: process(state, out_dmem, wmsti.ack)
begin
msto.dat <= (others => '0');
case state is
when ONEACC =>
if(out_dmem.write_en = '1') then
msto.we <= '1';
msto.stb <= '1';
msto.cyc <= '1';
msto.adr <= out_dmem.write_addr(memory_width - 1 downto WB_ADR_BOUND);
msto.sel <= gen_select(out_dmem.write_addr(1 downto 0), out_dmem.write_size);
msto.dat <= enc_wb_dat(out_dmem.write_addr(1 downto 0), out_dmem.write_size, out_dmem.write_data);
elsif(out_dmem.read_en = '1' and out_dmem.write_en = '0') then
msto.we <= '0';
msto.stb <= '1';
msto.cyc <= '1';
msto.adr <= out_dmem.read_addr(memory_width - 1 downto WB_ADR_BOUND);
msto.sel <= gen_select(out_dmem.read_addr(1 downto 0), out_dmem.read_size);
else
msto <= wbm_out_none;
end if;
when SIMACCRD => -- using previous address from sim request, no need since core will keep holding the value
msto.we <= '0';
msto.stb <= '1';
msto.cyc <= '1';
msto.adr <= out_dmem.read_addr(memory_width - 1 downto WB_ADR_BOUND);
msto.sel <= gen_select(out_dmem.read_addr(1 downto 0), out_dmem.read_size);
when SIMACCWR =>
msto.we <= '1';
msto.stb <= '1';
msto.cyc <= '1';
msto.adr <= out_dmem.write_addr(memory_width - 1 downto WB_ADR_BOUND);
msto.sel <= gen_select(out_dmem.write_addr(1 downto 0), out_dmem.write_size);
msto.dat <= enc_wb_dat(out_dmem.write_addr(1 downto 0), out_dmem.write_size, out_dmem.write_data);
end case;
end process;
wmsto <= msto;
-----------------------------
-- wbmi 2 core
-----------------------------
wb2core_reg: process(wmsti, state, out_dmem)
begin
in_dmem.ready <= '0';
if state = SIMACCWR then
in_dmem.ready <= '0';
elsif state = SIMACCRD then
in_dmem.ready <= wmsti.ack;
elsif state = ONEACC then
if (out_dmem.write_en xor out_dmem.read_en)='1' then
in_dmem.ready <= wmsti.ack;
--elsif out_dmem.write_en='0' and out_dmem.read_en='0' then
-- indmem.ready <= '1';
--elsif out_dmem.write_en='1' and out_dmem.read_en='1' then
-- indmem.ready <= '0';
else --instead of the fancy stuff above:
in_dmem.ready <= out_dmem.write_en nand out_dmem.read_en;
end if;
end if;
end process;
end Behavioral;

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-- See the file "LICENSE" for the full license governing this code. --
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.lt16x32_global.all;
-- this testbench testes the core in total
entity core_tb is
end entity core_tb;
architecture RTL of core_tb is
-- clock period, f = 1/period
constant period : time := 10 ns;
component core
port(clk : in std_logic;
rst : in std_logic;
stall : in std_logic;
in_dmem : in dmem_core;
out_dmem : out core_dmem;
in_imem : in imem_core;
out_imem : out core_imem;
in_irq : in irq_core;
out_irq : out core_irq;
hardfault : out std_logic);
end component core;
component memory
generic(filename : string := "program.ram";
size : integer := 256;
imem_latency : time := 5 ns;
dmem_latency : time := 5 ns);
port(clk : in std_logic;
rst : in std_logic;
in_dmem : in core_dmem;
out_dmem : out dmem_core;
in_imem : in core_imem;
out_imem : out imem_core;
fault : out std_logic;
out_byte : out std_logic_vector(7 downto 0));
end component memory;
component irq_controller
port(clk : in std_logic;
rst : in std_logic;
in_proc : in core_irq;
out_proc : out irq_core;
irq_lines : in std_logic_vector((2 ** irq_num_width) - 1 downto 0));
end component irq_controller;
-- clock signal
signal clk : std_logic := '0';
-- reset signal, active high
signal rst : std_logic := '1';
-- outbyte signal
signal out_byte : std_logic_vector(7 downto 0);
-- signals between instances
signal dmem_proc_signal : dmem_core;
signal proc_dmem_signal : core_dmem;
signal imem_proc_signal : imem_core;
signal proc_imem_signal : core_imem;
signal irq_proc_signal : irq_core;
signal proc_irq_signal : core_irq;
signal irq_lines : std_logic_vector((2 ** irq_num_width) - 1 downto 0);
begin
core_inst : component core
port map(clk => clk,
rst => rst,
stall => '0',
in_dmem => dmem_proc_signal,
out_dmem => proc_dmem_signal,
in_imem => imem_proc_signal,
out_imem => proc_imem_signal,
in_irq => irq_proc_signal,
out_irq => proc_irq_signal,
hardfault => irq_lines(1));
memory_inst : component memory
generic map(--filename => "sample-programs\test_endianess2.ram",
--filename => "sample-programs\rawhztest.ram",
filename => "sample-programs\rdmem.ram",
size => 256,
imem_latency => 0 ns,
dmem_latency => 0 ns)
port map(clk => clk,
rst => rst,
in_dmem => proc_dmem_signal,
out_dmem => dmem_proc_signal,
in_imem => proc_imem_signal,
out_imem => imem_proc_signal,
fault => irq_lines(2),
out_byte => out_byte);
irq_controller_inst : component irq_controller
port map(clk => clk,
rst => rst,
in_proc => proc_irq_signal,
out_proc => irq_proc_signal,
irq_lines => irq_lines);
-- irq line stimuli
irq_stimuli : process is
begin
irq_lines(irq_lines'high downto 3) <= (others => '0');
irq_lines(0) <= '0';
-- irq0 is reset
-- irq1 is hardfault
-- irq2 is memfault
-- wait for 600 ns;
-- wait until rising_edge(clk);
-- irq_lines(3) <= '1';
-- irq_lines(4) <= '1';
-- wait until rising_edge(clk);
-- irq_lines(3) <= '0';
-- irq_lines(4) <= '0';
wait;
end process irq_stimuli;
-- clock stimuli
clock : process is
begin
clk <= not clk;
wait for period / 2;
end process clock;
-- reset stimuli
reset : process is
begin
rst <= '1';
wait for 3.5 * period;
rst <= '0';
wait;
end process reset;
end architecture RTL;

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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/msys/1.0/home/Ben/hiwi/esysoc/core_tb_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="core_tb" />
<top_module name="lt16x32_global" />
<top_module name="lt16x32_internal" />
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="textio" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="6" />
<wvobject fp_name="/core_tb/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/out_byte" type="array" db_ref_id="1">
<obj_property name="ElementShortName">out_byte[7:0]</obj_property>
<obj_property name="ObjectShortName">out_byte[7:0]</obj_property>
</wvobject>
<wvobject fp_name="group35" type="group">
<obj_property name="label">D mem</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/core_tb/dmem_proc_signal" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dmem_proc_signal</obj_property>
<obj_property name="ObjectShortName">dmem_proc_signal</obj_property>
<wvobject fp_name="/core_tb/dmem_proc_signal.read_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.read_data</obj_property>
<obj_property name="ObjectShortName">dmem_proc_signal.read_data</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/dmem_proc_signal.ready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.ready</obj_property>
<obj_property name="ObjectShortName">dmem_proc_signal.ready</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/core_tb/proc_dmem_signal" type="array" db_ref_id="1">
<obj_property name="ElementShortName">proc_dmem_signal</obj_property>
<obj_property name="ObjectShortName">proc_dmem_signal</obj_property>
<wvobject fp_name="/core_tb/proc_dmem_signal.write_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.write_data</obj_property>
<obj_property name="ObjectShortName">proc_dmem_signal.write_data</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/proc_dmem_signal.write_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.write_addr</obj_property>
<obj_property name="ObjectShortName">proc_dmem_signal.write_addr</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/proc_dmem_signal.write_size" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.write_size</obj_property>
<obj_property name="ObjectShortName">proc_dmem_signal.write_size</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/proc_dmem_signal.write_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.write_en</obj_property>
<obj_property name="ObjectShortName">proc_dmem_signal.write_en</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/proc_dmem_signal.read_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.read_addr</obj_property>
<obj_property name="ObjectShortName">proc_dmem_signal.read_addr</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/proc_dmem_signal.read_size" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.read_size</obj_property>
<obj_property name="ObjectShortName">proc_dmem_signal.read_size</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/proc_dmem_signal.read_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.read_en</obj_property>
<obj_property name="ObjectShortName">proc_dmem_signal.read_en</obj_property>
</wvobject>
</wvobject>
</wvobject>
<wvobject fp_name="group34" type="group">
<obj_property name="label">I mem</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/core_tb/imem_proc_signal" type="array" db_ref_id="1">
<obj_property name="ElementShortName">imem_proc_signal</obj_property>
<obj_property name="ObjectShortName">imem_proc_signal</obj_property>
<wvobject fp_name="/core_tb/imem_proc_signal.read_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.read_data</obj_property>
<obj_property name="ObjectShortName">imem_proc_signal.read_data</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/imem_proc_signal.ready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.ready</obj_property>
<obj_property name="ObjectShortName">imem_proc_signal.ready</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/core_tb/proc_imem_signal" type="array" db_ref_id="1">
<obj_property name="ElementShortName">proc_imem_signal</obj_property>
<obj_property name="ObjectShortName">proc_imem_signal</obj_property>
<wvobject fp_name="/core_tb/proc_imem_signal.read_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.read_addr</obj_property>
<obj_property name="ObjectShortName">proc_imem_signal.read_addr</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/proc_imem_signal.read_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.read_en</obj_property>
<obj_property name="ObjectShortName">proc_imem_signal.read_en</obj_property>
</wvobject>
</wvobject>
</wvobject>
<wvobject fp_name="group33" type="group">
<obj_property name="label">IRQ</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/core_tb/irq_proc_signal" type="array" db_ref_id="1">
<obj_property name="ElementShortName">irq_proc_signal</obj_property>
<obj_property name="ObjectShortName">irq_proc_signal</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/proc_irq_signal" type="array" db_ref_id="1">
<obj_property name="ElementShortName">proc_irq_signal</obj_property>
<obj_property name="ObjectShortName">proc_irq_signal</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/irq_lines" type="array" db_ref_id="1">
<obj_property name="ElementShortName">irq_lines[15:0]</obj_property>
<obj_property name="ObjectShortName">irq_lines[15:0]</obj_property>
</wvobject>
</wvobject>
</wave_config>

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-- See the file "LICENSE" for the full license governing this code. --
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.lt16x32_internal.all;
use work.lt16x32_global.all;
use work.wishbone.all;
use work.config.all;
-- TODO: check core(big/little endian) -> assume as little !!
entity corewrapper is
port(
clk : in std_logic;
rst : in std_logic;
in_imem : in imem_core;
out_imem : out core_imem;
in_proc : in irq_core;
out_proc : out core_irq;
hardfault : out std_logic;
-- wb master port
wmsti : in wb_mst_in_type;
wmsto : out wb_mst_out_type
);
end entity corewrapper;
architecture RTL of corewrapper is
signal wbmo : wb_mst_out_type := wbm_out_none;
--signal indmem : dmem_core;
signal in_dmem : dmem_core;
signal out_dmem : core_dmem;
-- signal inimem : imem_core;
-- signal outimem : core_imem;
--//////////////////////////////////////////////////////
-- component
--//////////////////////////////////////////////////////
component core
port(
clk : in std_logic;
rst : in std_logic;
stall : in std_logic;
in_dmem : in dmem_core;
out_dmem : out core_dmem;
in_imem : in imem_core;
out_imem : out core_imem;
in_irq : in irq_core;
out_irq : out core_irq;
hardfault : out std_logic
);
end component;
component core2wb
port(
clk : in std_logic;
rst : in std_logic;
in_dmem : out dmem_core;
out_dmem : in core_dmem;
-- wb master port
wmsti : in wb_mst_in_type;
wmsto : out wb_mst_out_type
);
end component;
begin
--//////////////////////////////////////////////////////
-- Instantiate
--//////////////////////////////////////////////////////
--
core_inst: core
port map(
clk => clk,
rst => rst,
stall => '0', -- no stall for now -- wmsti.stall
in_dmem => in_dmem,
out_dmem => out_dmem,
in_imem => in_imem, -- inimem,
out_imem => out_imem, -- outimem,
in_irq => in_proc,
out_irq => out_proc,
hardfault => hardfault
);
core2wb_inst: core2wb
port map(
clk => clk,
rst => rst,
in_dmem => in_dmem,
out_dmem => out_dmem,
-- wb master port
wmsti => wmsti,
wmsto => wmsto
);
--//////////////////////////////////////////////////////
-- I - mem
--//////////////////////////////////////////////////////
-- core connect directly to the mem
-- imem: process(clk)
-- begin
-- if rising_edge(clk) then
-- if rst = '1' then
-- -- to core
-- inimem.read_data <= (others=>'-');
-- inimem.ready <= '0';
-- -- out from core
-- outimem.read_addr <= (others=>'0');
-- outimem.read_en <= '0';
--
-- out_imem.read_addr <= (others=>'0');
-- out_imem.read_en <= '0';
-- else
-- -- to core
-- inimem <= in_imem;
-- -- out from core
-- out_imem <= outimem;
-- end if;
-- end if;
-- end process;
end architecture RTL;

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-- See the file "LICENSE" for the full license governing this code. --
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.lt16x32_internal.all;
use work.lt16x32_global.all;
-- the datapath handles all data interactions, including the registerfile and the ALU
entity datapath is
port(
-- clock signal
clk : in std_logic;
-- reset signal, active high, synchronous
rst : in std_logic;
-- stall signal (halts pipelines and all flipflops), active high, synchronous
stall : in std_logic;
-- signals to decoder
out_dec : out dp_dec;
-- signals from control path
in_cp : in cp_dp;
-- signals to control path
out_cp : out dp_cp;
-- signals from PC counter
in_pc : in pc_dp;
-- signals to PC counter
out_pc : out dp_pc;
-- signals from data memory
in_dmem : in dmem_dp;
-- signals to data memory
out_dmem : out dp_dmem;
-- hardfault signal
hardfault : out std_logic
);
end entity datapath;
architecture RTL of datapath is
component alu
port(in_a : in signed(reg_width - 1 downto 0);
in_b : in signed(reg_width - 1 downto 0);
t_out : out std_logic;
ovf_out : out std_logic;
mode : in alu_mode_type;
data_out : out signed(reg_width - 1 downto 0));
end component alu;
component registerfile
port(clk : in std_logic;
rst : in std_logic;
stall : in std_logic;
a_num : in reg_number;
a_out : out signed(reg_width - 1 downto 0);
b_num : in reg_number;
b_out : out signed(reg_width - 1 downto 0);
pc_in : in unsigned(pc_width - 1 downto 0);
write_data : in signed(reg_width - 1 downto 0);
write_num : in reg_number;
write_en : in std_logic;
true_writeenable : in std_logic;
true_in : in std_logic;
true_out : out std_logic;
ovf_writeenable : in std_logic;
ovf_in : in std_logic;
runtime_priority : out unsigned(irq_prio_width - 1 downto 0));
end component registerfile;
-- signals from register file
signal regfile_reg_a : signed(reg_width - 1 downto 0);
signal regfile_reg_b : signed(reg_width - 1 downto 0);
signal regfile_tflag : std_logic;
-- signals from ALU
signal alu_result : signed(reg_width - 1 downto 0);
signal alu_tflag : std_logic;
signal alu_ovfflag : std_logic;
-- mux output signals
-- data written to register file (if registerfile.we = '1')
signal reg_write_data : signed(reg_width - 1 downto 0);
-- second alu input data
signal alu_input_b : signed(reg_width - 1 downto 0);
-- bit saved as truth-flag (if registerfile.tflag_we = '1')
signal tflag_write_data : std_logic;
-- forwarded register values
-- register a value after forwarding unit
signal regfile_reg_a_fwd : signed(reg_width - 1 downto 0);
-- register b value after forwarding unit
signal regfile_reg_b_fwd : signed(reg_width - 1 downto 0);
-- truth-flag after forwarding
signal regfile_tflag_fwd : std_logic;
-- pipelined signals
signal register_number_a_s2 : reg_number;
signal register_number_b_s2 : reg_number;
signal regfile_reg_a_s3 : signed(reg_width - 1 downto 0);
signal regfile_reg_b_s3 : signed(reg_width - 1 downto 0);
signal alu_result_s3 : signed(reg_width - 1 downto 0);
signal alu_tflag_s3 : std_logic;
signal alu_ovfflag_s3 : std_logic;
signal pc_value_s2 : unsigned(pc_width - 1 downto 0);
signal immediate_signext_s3 : signed(reg_width - 1 downto 0);
-- signals calculated internally in datapath
-- LDR address
signal ldr_address : signed(reg_width - 1 downto 0);
-- immediate value with signextension for use as alu input
signal immediate_signext : signed(reg_width - 1 downto 0);
-- write data to register file including masking for size
signal reg_write_data_sized : signed(reg_width - 1 downto 0);
-- dmem read data or'ed with 0xF0
signal dmemORx80 : std_logic_vector(reg_width - 1 downto 0);
-- hardfault signals
signal regwrite_size_error : std_logic;
-- returns minimum of (a, b). needed, since XILINX does not support constant conditional syntax
function minval(a : integer; b : integer) return integer is
begin
if (a <= b) then
return a;
else
return b;
end if;
end function minval;
begin
registerfile_inst : component registerfile
port map(clk => clk,
rst => rst,
stall => stall,
a_num => in_cp.s1.register_read_number_a,
a_out => regfile_reg_a,
b_num => in_cp.s1.register_read_number_b,
b_out => regfile_reg_b,
pc_in => pc_value_s2,
write_data => reg_write_data_sized,
write_num => in_cp.s3.register_write_number,
write_en => in_cp.s3.register_write_enable,
true_writeenable => in_cp.s3.tflag_write_enable,
true_in => tflag_write_data,
true_out => regfile_tflag,
ovf_writeenable => in_cp.s3.ovfflag_write_enable,
ovf_in => alu_ovfflag_s3,
runtime_priority => out_dec.runtime_priority);
alu_inst : component alu
port map(in_a => regfile_reg_a_fwd,
in_b => alu_input_b,
t_out => alu_tflag,
ovf_out => alu_ovfflag,
mode => in_cp.s2.alu_mode,
data_out => alu_result);
-- simple output assignments
out_pc.register_value <= regfile_reg_a_fwd(regfile_reg_a_fwd'high downto 1); -- last bit ignored for PC
hardfault <= regwrite_size_error;
out_dmem.write_addr(reg_width - 1 downto 0) <= std_logic_vector(regfile_reg_a_s3);
out_cp.s2.tflag <= regfile_tflag_fwd;
-- create signextended immediate
-- sign extension
immediate_signext(immediate_signext'left downto (in_cp.s2.immediate'left + 1)) <= (others => in_cp.s2.immediate(7));
-- actual data
immediate_signext(in_cp.s2.immediate'range) <= in_cp.s2.immediate;
-- ldr address calculation
-- ldr_address = PC + (immediate << 1)
ldr_address <= signed(pc_value_s2) + signed(immediate_signext(reg_width - 2 downto 0) & "0");
-- create immediate value for pc block
-- sign extension
pc_imm_fill : if (reg_width > 8) generate
out_pc.immediate_value(out_pc.immediate_value'left downto (in_cp.s2.immediate'left + 1)) <= (others => in_cp.s2.immediate(7));
end generate;
-- actual data, (left shift by one is performed by PC)
out_pc.immediate_value(minval(out_pc.immediate_value'high, in_cp.s2.immediate'left) downto 0) <= in_cp.s2.immediate(minval(out_pc.immediate_value'high, in_cp.s2.immediate'left) downto 0);
-- fill dmem read/write address and dmem write data, if reg width is smaller than memory width
-- all warnings of the type "Null range" can be safely ignored for reg_width = mem_width
dmem_fill : if (reg_width < mem_width) generate
out_dmem.write_addr(mem_width - 1 downto reg_width) <= (others => '0');
out_dmem.write_data(mem_width - 1 downto reg_width) <= (others => '0');
out_dmem.read_addr(mem_width - 1 downto reg_width) <= (others => '0');
end generate dmem_fill;
-- dmem data or'ing (dmemORx80 = dmem.read_data or 0x80)
dmemORx80_calc : process(in_dmem.read_data) is
begin
dmemORx80 <= in_dmem.read_data(reg_width - 1 downto 0);
dmemORx80(7) <= '1';
end process dmemORx80_calc;
-- multiplexer
regfile_write_data_mux : with in_cp.s3.register_write_data_select select reg_write_data <=
signed(in_dmem.read_data(reg_width - 1 downto 0)) when sel_memory,
alu_result_s3 when sel_alu_result,
immediate_signext_s3 when sel_immediate;
alu_in_b_mux : with in_cp.s2.alu_input_data_select select alu_input_b <=
regfile_reg_b_fwd when sel_register_b,
immediate_signext when sel_imm;
dmem_write_data_mux : with in_cp.s3.memory_write_data_select select out_dmem.write_data(reg_width - 1 downto 0) <=
std_logic_vector(regfile_reg_b_s3) when sel_register_value,
dmemORx80 when sel_dmemORx80;
dmem_read_addr_mux : with in_cp.s2.memory_read_addr_select select out_dmem.read_addr(reg_width - 1 downto 0) <=
std_logic_vector(regfile_reg_a_fwd) when sel_register_a,
std_logic_vector(regfile_reg_b_fwd) when sel_register_b,
std_logic_vector(ldr_address) when sel_ldr_address;
tflag_write_data_mux : with in_cp.s3.tflag_write_data_select select tflag_write_data <=
(not in_dmem.read_data(7)) when sel_dmem7,
alu_tflag_s3 when sel_alu;
-- forwarding units
forward_register_a : process(in_cp.s3.register_write_number, register_number_a_s2, reg_write_data_sized, regfile_reg_a, in_cp.s3.register_write_enable) is
begin
if ((in_cp.s3.register_write_enable = '1') and (in_cp.s3.register_write_number = register_number_a_s2)) then
-- next cycle, there's a write to register number a, forward new value
regfile_reg_a_fwd <= reg_write_data_sized;
else
-- next cycle is no write to register number a, no forwarding
regfile_reg_a_fwd <= regfile_reg_a;
end if;
end process forward_register_a;
forward_register_b : process(in_cp.s3.register_write_number, register_number_b_s2, reg_write_data_sized, regfile_reg_b, in_cp.s3.register_write_enable) is
begin
if ((in_cp.s3.register_write_enable = '1') and (in_cp.s3.register_write_number = register_number_b_s2)) then
-- next cycle, there's a write to register number b, forward new value
regfile_reg_b_fwd <= reg_write_data_sized;
else
-- next cycle is no write to register number b, no forwarding
regfile_reg_b_fwd <= regfile_reg_b;
end if;
end process forward_register_b;
forward_tflag : process(tflag_write_data, regfile_tflag, in_cp.s3.tflag_write_enable) is
begin
if (in_cp.s3.tflag_write_enable = '1') then
-- next cycle, there's a write to the truth flag, forward new value
regfile_tflag_fwd <= tflag_write_data;
else
-- next cycle is no write to the truth flag
regfile_tflag_fwd <= regfile_tflag;
end if;
end process forward_tflag;
-- generate size-matched data for the register file and forwarding units from the full-word write data
reg_write_data_sized_calc : process(reg_write_data, in_cp.s3.register_write_size) is
variable error : boolean;
begin
error := false;
reg_write_data_sized <= (others => '0');
case in_cp.s3.register_write_size is
when size_byte =>
reg_write_data_sized(7 downto 0) <= reg_write_data(7 downto 0);
when size_halfword =>
if (reg_width >= 16) then
reg_write_data_sized(minval(reg_width - 1, 15) downto 0) <= reg_write_data(minval(reg_width - 1, 15) downto 0);
else
error := true;
end if;
when size_word =>
if (reg_width >= 32) then
reg_write_data_sized(minval(reg_width - 1, 31) downto 0) <= reg_write_data(minval(reg_width - 1, 31) downto 0);
else
error := true;
end if;
end case;
if (error) then
-- synthesis translate_off
assert false report "size not supported" severity warning;
-- synthesis translate_on
regwrite_size_error <= '1';
else
regwrite_size_error <= '0';
end if;
end process reg_write_data_sized_calc;
-- pipelining
pipeline : process(clk) is
begin
if (rising_edge(clk)) then
if (rst = '1') then
-- default values in reset state
pc_value_s2 <= (others => '0');
alu_result_s3 <= (others => '0');
alu_tflag_s3 <= '0';
alu_ovfflag_s3 <= '0';
register_number_a_s2 <= (others => '0');
register_number_b_s2 <= (others => '0');
regfile_reg_a_s3 <= (others => '0');
regfile_reg_b_s3 <= (others => '0');
immediate_signext_s3 <= (others => '0');
elsif (stall = '0') then
-- if stall is not active, pipeline values
pc_value_s2 <= in_pc.value;
alu_result_s3 <= alu_result;
alu_tflag_s3 <= alu_tflag;
alu_ovfflag_s3 <= alu_ovfflag;
register_number_a_s2 <= in_cp.s1.register_read_number_a;
register_number_b_s2 <= in_cp.s1.register_read_number_b;
regfile_reg_a_s3 <= regfile_reg_a_fwd;
regfile_reg_b_s3 <= regfile_reg_b_fwd;
immediate_signext_s3 <= immediate_signext;
end if;
end if;
end process pipeline;
end architecture RTL;

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-- See the file "LICENSE" for the full license governing this code. --
library ieee;
use ieee.std_logic_1164.all;
use work.lt16x32_internal.all;
-- the decoder translates instructions from the memory into control signals.
-- it bundles pre-stage, finite stage machine and multiple instruction decoder (16bit, 32bit, shadow)
entity decoder is
port(
-- clock signal
clk : in std_logic;
-- reset signal, active high, synchronous
rst : in std_logic;
-- stall signal, active high, synchronous
stall : in std_logic;
-- signals from instruction memory
in_imem : in imem_dec;
-- signals to instruction memory
out_imem : out dec_imem;
-- signals from datapath
in_dp : in dp_dec;
-- signals from controlpath
in_cp : in cp_dec;
-- signals to controlpath
out_cp : out dec_cp;
-- signals to PC
out_pc : out dec_pc;
-- signals from interrupt controller
in_irq : in irq_dec;
-- signals to interrupt controller
out_irq : out dec_irq
);
end entity decoder;
architecture RTL of decoder is
component decoder_pre
port(input : in imem_dec;
output : out pre_fsm);
end component decoder_pre;
component decoder_16bit
port(input : in fsm_dec16;
output : out dec_cp);
end component decoder_16bit;
component decoder_32bit
port(input : in fsm_dec32;
output : out dec_cp);
end component decoder_32bit;
component decoder_shadow
port(input : in fsm_decshd;
output : out dec_cp);
end component decoder_shadow;
component decoder_fsm
port(clk : in std_logic;
rst : in std_logic;
stall : in std_logic;
in_pre : in pre_fsm;
in_cp : in cp_dec;
in_dp : in dp_dec;
out_16 : out fsm_dec16;
out_32 : out fsm_dec32;
out_shd : out fsm_decshd;
out_mux : out fsm_decmux;
out_pc : out dec_pc;
out_imem : out dec_imem;
in_irq : in irq_dec;
out_irq : out dec_irq);
end component decoder_fsm;
-- signals between instances
signal pre_fsm_signal : pre_fsm;
signal fsm_dec16_signal : fsm_dec16;
signal fsm_dec32_signal : fsm_dec32;
signal fsm_decshd_signal : fsm_decshd;
signal fsm_mux_signal : fsm_decmux;
signal fsm_pc_signal : dec_pc;
signal fsm_imem_signal : dec_imem;
signal dec16_mux_signal : dec_cp;
signal dec32_mux_signal : dec_cp;
signal decshd_mux_signal : dec_cp;
begin
decoder_pre_inst : component decoder_pre
port map(input => in_imem,
output => pre_fsm_signal);
decoder_fsm_inst : component decoder_fsm
port map(clk => clk,
rst => rst,
stall => stall,
in_pre => pre_fsm_signal,
in_cp => in_cp,
in_dp => in_dp,
in_irq => in_irq,
out_irq => out_irq,
out_16 => fsm_dec16_signal,
out_32 => fsm_dec32_signal,
out_shd => fsm_decshd_signal,
out_mux => fsm_mux_signal,
out_pc => fsm_pc_signal,
out_imem => fsm_imem_signal);
decoder_16_inst : component decoder_16bit
port map(input => fsm_dec16_signal,
output => dec16_mux_signal);
decoder_32_inst : component decoder_32bit
port map(input => fsm_dec32_signal,
output => dec32_mux_signal);
decoder_shd_inst : component decoder_shadow
port map(input => fsm_decshd_signal,
output => decshd_mux_signal);
-- multiplexer
mux_output : with fsm_mux_signal.mode select out_cp <=
dec16_mux_signal when sel_ir16,
dec32_mux_signal when sel_ir32,
decshd_mux_signal when sel_irshadow;
-- simple signal assignments
out_pc <= fsm_pc_signal;
out_imem <= fsm_imem_signal;
end architecture RTL;

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-- See the file "LICENSE" for the full license governing this code. --
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.lt16x32_internal.all;
-- the decoder_16bit decodes all 16bit instructions and is fully combinatoric
entity decoder_16bit is
port(
-- input signals from decoder_fsm
input : in fsm_dec16;
-- output signals to controlpath (or decoder mux)
output : out dec_cp
);
end entity decoder_16bit;
architecture RTL of decoder_16bit is
begin
-- decode instruction
decode : process(input) is
begin
-- set defaults to prevent taking values from previous operations
output.s1 <= get_default_dec_cp_s1;
output.s2 <= get_default_dec_cp_s2;
output.s3 <= get_default_dec_cp_s3;
output.hardfault <= '0';
-- directly forwarded instruction parts
output.s1.register_read_number_a <= reg_number(input.instruction(7 downto 4));
output.s1.register_read_number_b <= reg_number(input.instruction(3 downto 0));
output.s3.register_write_number <= reg_number(input.instruction(11 downto 8));
-- set opcode specific signals
case input.instruction(15 downto 12) is
when op_add => -- add instruction
output.s2.alu_mode <= alu_add;
output.s3.register_write_enable <= '1';
output.s3.ovfflag_write_enable <= '1';
when op_sub => -- subtract instruction
output.s2.alu_mode <= alu_sub;
output.s3.register_write_enable <= '1';
output.s3.ovfflag_write_enable <= '1';
when op_or => -- bitwise or instruction
output.s2.alu_mode <= alu_or;
output.s3.register_write_enable <= '1';
when op_and => -- bitwise and instruction
output.s2.alu_mode <= alu_and;
output.s3.register_write_enable <= '1';
when op_xor => -- bitwise xor instruction
output.s2.alu_mode <= alu_xor;
output.s3.register_write_enable <= '1';
when op_lsh => -- logic left shift instruction
output.s2.alu_mode <= alu_lsh;
output.s2.alu_input_data_select <= sel_imm;
output.s2.immediate <= signed("0000" & input.instruction(3 downto 0));
output.s3.register_write_enable <= '1';
when op_rsh => -- logic right shift instruction
output.s2.alu_mode <= alu_rsh;
output.s2.alu_input_data_select <= sel_imm;
output.s2.immediate <= signed("0000" & input.instruction(3 downto 0));
output.s3.register_write_enable <= '1';
when op_addi => -- add immediate instruction
output.s1.register_read_number_a <= reg_number(input.instruction(11 downto 8));
output.s2.alu_mode <= alu_add;
output.s2.alu_input_data_select <= sel_imm;
output.s2.immediate <= signed(input.instruction(7 downto 0));
output.s3.register_write_enable <= '1';
output.s3.ovfflag_write_enable <= '1';
when op_cmp => -- compare instruction
output.s3.tflag_write_enable <= '1';
case input.instruction(11 downto 8) is
when op_cmp_eq => -- compare for equal
output.s2.alu_mode <= alu_cmp_eq;
when op_cmp_neq => -- compare for not equal
output.s2.alu_mode <= alu_cmp_neq;
when op_cmp_ge => -- compare for greater than or equal
output.s2.alu_mode <= alu_cmp_ge;
when op_cmp_ll => -- compare for less than
output.s2.alu_mode <= alu_cmp_ll;
when op_cmp_gg => -- compare for greater than
output.s2.alu_mode <= alu_cmp_gg;
when op_cmp_le => -- compare for less than or equal
output.s2.alu_mode <= alu_cmp_le;
when op_cmp_true => -- set truth flag
output.s2.alu_mode <= alu_cmp_true;
when op_cmp_false => -- reset truth flag
output.s2.alu_mode <= alu_cmp_false;
when others =>
-- unknown compare mode, throw hardfault
output.hardfault <= '1';
-- synthesis translate_off
assert false report "cmp mode not supported" severity error;
-- synthesis translate_on
end case;
when op_bct => -- branch, call, trap, reti instruction
if (input.instruction(11 downto 9) = op_bct_reti) then
-- it's reti instruction, which is not allowed here (as it is handled earlier in decoder)
output.hardfault <= '1';
-- synthesis translate_off
assert false report "reti operation not allowed in 16 bit decoder stage" severity error;
-- synthesis translate_on
else -- table / branch / (call) / trap
-- decode source bit
if (input.instruction(9) = '0') then -- bct to immediate
if (input.instruction(11 downto 10) = op_bct_trap) then
-- trap is absolute to immediate
output.s2.pc_mode_select <= sel_absolute;
else
-- all other branches to immediate are relative
output.s2.pc_mode_select <= sel_relative;
end if;
-- immediate parameters
output.s2.pc_summand_select <= sel_immediate;
output.s2.immediate <= signed(input.instruction(7 downto 0));
else -- bct to register
if (input.instruction(11 downto 10) = op_bct_table) then
-- branch to table is pc relative
output.s2.pc_mode_select <= sel_relative;
else
-- all other branches to register are absolute
output.s2.pc_mode_select <= sel_absolute;
end if;
-- register parameters
output.s2.pc_summand_select <= sel_register_a;
end if;
-- decode conditional bit
if (input.instruction(8) = '1') then
output.s2.pc_condition <= sel_true;
else
output.s2.pc_condition <= sel_unconditional;
end if;
end if;
when op_mem => -- memory instructions
case input.instruction(11 downto 8) is
when op_mem_ld08 => -- load byte
output.s2.dmem_read_addr_select <= sel_register_b;
output.s2.dmem_read_en <= '1';
output.s2.dmem_read_size <= size_byte;
output.s3.register_write_data_select <= sel_memory;
output.s3.register_write_enable <= '1';
output.s3.register_write_size <= size_byte;
output.s3.register_write_number <= reg_number(input.instruction(7 downto 4));
when op_mem_ld16 => -- load halfword
output.s2.dmem_read_addr_select <= sel_register_b;
output.s2.dmem_read_en <= '1';
output.s2.dmem_read_size <= size_halfword;
output.s3.register_write_data_select <= sel_memory;
output.s3.register_write_enable <= '1';
output.s3.register_write_size <= size_halfword;
output.s3.register_write_number <= reg_number(input.instruction(7 downto 4));
when op_mem_ld32 => -- load word
output.s2.dmem_read_addr_select <= sel_register_b;
output.s2.dmem_read_en <= '1';
output.s2.dmem_read_size <= size_word;
output.s3.register_write_data_select <= sel_memory;
output.s3.register_write_enable <= '1';
output.s3.register_write_size <= size_word;
output.s3.register_write_number <= reg_number(input.instruction(7 downto 4));
when op_mem_st08 => -- store byte
output.s3.dmem_write_en <= '1';
output.s3.dmem_write_size <= size_byte;
output.s3.dmem_write_data_select <= sel_register_value;
when op_mem_st16 => -- store halfword
output.s3.dmem_write_en <= '1';
output.s3.dmem_write_size <= size_halfword;
output.s3.dmem_write_data_select <= sel_register_value;
when op_mem_st32 => -- store word
output.s3.dmem_write_en <= '1';
output.s3.dmem_write_size <= size_word;
output.s3.dmem_write_data_select <= sel_register_value;
when others =>
-- unknown memory mode, throw hardfault
output.hardfault <= '1';
-- synthesis translate_off
assert false report "memory mode not supported" severity error;
-- synthesis translate_on
end case;
when op_ldr => -- load pc relative (full register width)
output.s2.immediate <= signed(input.instruction(7 downto 0));
output.s2.dmem_read_addr_select <= sel_ldr_address;
output.s2.dmem_read_en <= '1';
output.s2.dmem_read_size <= reg_size;
output.s3.register_write_data_select <= sel_memory;
output.s3.register_write_enable <= '1';
output.s3.register_write_size <= reg_size;
when op_tst => -- test and set
output.s2.dmem_read_addr_select <= sel_register_a;
output.s2.dmem_read_en <= '1';
output.s2.dmem_read_size <= size_byte;
output.s3.register_write_data_select <= sel_memory;
output.s3.register_write_enable <= '1';
output.s3.register_write_size <= size_byte;
output.s3.dmem_write_en <= '1';
output.s3.dmem_write_size <= size_byte;
output.s3.dmem_write_data_select <= sel_dmemORx80;
output.s3.tflag_write_data_select <= sel_dmem7;
output.s3.tflag_write_enable <= '1';
-- synthesis translate_off
when "UUUU" =>
null; -- ignore startup
when "XXXX" =>
null; -- ignore IM delay
-- synthesis translate_on
when others =>
-- unkwown operation, throw hardfault
output.hardfault <= '1';
-- synthesis translate_off
assert false report "unknown operation not implemented" severity error;
-- synthesis translate_on
end case;
end process decode;
end architecture RTL;

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-- See the file "LICENSE" for the full license governing this code. --
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.lt16x32_internal.all;
-- the decoder_32bit decodes all 32bit instructions and is fully combinatoric
entity decoder_32bit is
port(
-- input signals from decoder finite state machine
input : in fsm_dec32;
-- output signals to control path (or decoder mux)
output : out dec_cp
);
end entity decoder_32bit;
architecture RTL of decoder_32bit is
begin
-- currently, there are no 32bit instructions, so output is
-- always nop and hardfault
output.s1 <= get_default_dec_cp_s1;
output.s2 <= get_default_dec_cp_s2;
output.s3 <= get_default_dec_cp_s3;
output.hardfault <= '1';
end architecture RTL;

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-- See the file "LICENSE" for the full license governing this code. --
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.lt16x32_internal.all;
use work.lt16x32_global.all;
-- the decoder_fsm is the finite state machine handling multi-cycle operation and interrupt acknowledgement
entity decoder_fsm is
port(
-- clock signal
clk : in std_logic;
-- reset signal, active high, synchronous
rst : in std_logic;
-- stall signal, active high
stall : in std_logic;
-- signals from pre-decoder
in_pre : in pre_fsm;
-- signals from control path
in_cp : in cp_dec;
-- signals from datapath
in_dp : in dp_dec;
-- signals to 16bit decoder
out_16 : out fsm_dec16;
-- signals to 32bit decoder
out_32 : out fsm_dec32;
-- signals to shadow decoder
out_shd : out fsm_decshd;
-- signals to decoder mux
out_mux : out fsm_decmux;
-- signals to pc counter
out_pc : out dec_pc;
-- signals to instruction memory
out_imem : out dec_imem;
-- signals from interrupt controller
in_irq : in irq_dec;
-- signals to interrupt controller
out_irq : out dec_irq
);
end entity decoder_fsm;
architecture RTL of decoder_fsm is
-- possible states of fsm
type state_type is (normal, reset, reset2, copyPCtoLR, branchdelay, irq_decSP1, irq_pushSR, irq_pushLR, irq_setSR, irq_setPC, reti_popLR, reti_incSP1, reti_popSR, reti_incSP2); --add irq_decSP2 for 4 instruction irq stack solution
-- current state
signal state : state_type := normal;
-- temporary storage for multicycle operations
signal multicycleinstruction : std_logic_vector(31 downto 0);
begin
-- the finite state machine is modelled as mealy-machine
-- generate output (combinatoric part)
output : process(in_pre, state, multicycleinstruction, in_cp.condition_holds) is
variable state_variable : state_type;
begin
-- standard output
out_16.instruction <= nop16;
out_32.instruction <= in_pre.instruction;
out_shd.instruction(31 downto 28) <= op_shd_push;
out_shd.instruction(27 downto 0) <= (others => '0');
out_mux.mode <= sel_ir16;
out_pc.stall <= '0';
out_imem.en <= '1';
out_irq.ack <= '0';
out_irq.trap_req <= '0';
out_irq.trap_num <= (others => '0');
-- copy state to variable for further processing
state_variable := state;
-- don't insert nop in branch delay if no branch taken
-- happens only, if execute_branch_delay_slot is false
if ((state = branchdelay) and (in_cp.condition_holds = '0')) then
state_variable := normal;
end if;
-- don't write LR if no call happens
if ((state = copyPCtoLR) and (in_cp.condition_holds = '0')) then
state_variable := normal;
end if;
-- generate state dependend output
case state_variable is
when reset => -- first cycle in reset
out_pc.stall <= '1';
out_shd.instruction(31 downto 28) <= op_shd_reset;
out_mux.mode <= sel_irshadow;
when reset2 => -- second cycle in reset
out_pc.stall <= '0';
out_16.instruction <= nop16;
out_mux.mode <= sel_ir16;
when normal => -- standard mode
out_pc.stall <= '0';
case in_pre.mode is -- check decoder_pre mode output
when sel_normal16 => -- normal 16 bit instruction
out_mux.mode <= sel_ir16;
out_16.instruction <= in_pre.instruction(15 downto 0);
when sel_normal32 => -- normal 32 bit instruction
out_mux.mode <= sel_ir32;
out_32.instruction <= in_pre.instruction;
when sel_branch => -- branch instruction
out_mux.mode <= sel_ir16;
out_16.instruction <= in_pre.instruction(15 downto 0);
when sel_call => -- call instruction
out_mux.mode <= sel_ir16;
out_16.instruction <= op_bct & "01" & in_pre.instruction(9 downto 0);
--out_imem.en <= '0'; -- imem must be read in case that condition does not hold and next instruction should be executed
when sel_trap => -- trap instruction
out_mux.mode <= sel_ir16;
out_16.instruction <= nop16;
out_irq.trap_num <= unsigned(in_pre.instruction(irq_num_width - 1 downto 0));
out_irq.trap_req <= '1';
when sel_reti => -- reti instruction
out_mux.mode <= sel_ir16;
out_16.instruction <= op_bct & "0110" & std_logic_vector(lr_num) & "0000";
out_imem.en <= '0';
when sel_stall => -- stall (i.e. imem not ready)
out_mux.mode <= sel_ir16;
out_16.instruction <= in_pre.instruction(15 downto 0);
out_pc.stall <= '1';
end case;
when copyPCtoLR => -- LR = PC, used in call and irq
-- only if condition true, else normal instruction (this check is done in state transition)
out_mux.mode <= sel_ir16;
out_16.instruction <= op_or & std_logic_vector(lr_num) & std_logic_vector(pc_num) & std_logic_vector(pc_num);
out_imem.en <= '1';
when branchdelay => -- insert NOP to branch delay slot if enabled in configuration
out_pc.stall <= '0';
out_mux.mode <= sel_ir16;
out_imem.en <= '1';
--when irq_pushLR => -- irq: push LR
-- out_pc.stall <= '1';
-- out_mux.mode <= sel_irshadow;
-- out_shd.instruction(31 downto 28) <= op_shd_push;
-- out_shd.instruction(3 downto 0) <= std_logic_vector(lr_num);
-- out_imem.en <= '0';
when irq_pushLR =>
out_pc.stall <= '1';
out_mux.mode <= sel_ir16;
out_16.instruction <= op_mem & op_mem_st32 & std_logic_vector(sp_num) & std_logic_vector(lr_num);
out_imem.en <= '1';
when irq_setSR => -- irq: push SR and set new SR value
out_pc.stall <= '1';
out_mux.mode <= sel_irshadow;
out_shd.instruction(31 downto 28) <= op_shd_setsr;
-- new runtime priority, other SR flags all zero
out_shd.instruction(7 downto (8 - irq_prio_width)) <= multicycleinstruction(16 + irq_prio_width - 1 downto 16);
out_imem.en <= '0';
when irq_setPC => -- irq: branch to irq address
out_pc.stall <= '1';
out_mux.mode <= sel_ir16;
out_16.instruction <= op_bct & "11" & multicycleinstruction(9 downto 0);
out_imem.en <= '0';
when reti_popLR => -- reti: load LR from stack
out_pc.stall <= '0'; --former 1
out_mux.mode <= sel_ir16;
out_16.instruction <= op_mem & op_mem_ld32 & std_logic_vector(lr_num) & std_logic_vector(sp_num);
out_imem.en <= '0';
when reti_popSR => -- reti: load SR from stack
out_pc.stall <= '1';
out_mux.mode <= sel_ir16;
out_16.instruction <= op_mem & op_mem_ld32 & std_logic_vector(sr_num) & std_logic_vector(sp_num);
out_imem.en <= '1';
when reti_incSP1 => -- reti: increment SP
out_pc.stall <= '1';
out_mux.mode <= sel_ir16;
out_16.instruction <= op_addi & std_logic_vector(sp_num) & std_logic_vector(to_signed(4, 8));
out_imem.en <= '0';
when reti_incSP2 => -- reti increment SP
out_pc.stall <= '1';
out_mux.mode <= sel_ir16;
out_16.instruction <= op_addi & std_logic_vector(sp_num) & std_logic_vector(to_signed(4, 8));
out_imem.en <= '0';
when irq_pushSR => -- irq: push SR (store and decrement SP afterwards)
out_mux.mode <= sel_irshadow;
out_shd.instruction(31 downto 28) <= op_shd_push;
out_shd.instruction(3 downto 0) <= std_logic_vector(sr_num);
out_irq.ack <= '1';
out_pc.stall <= '1';
--when irq_pushSR =>
-- out_pc.stall <= '1';
-- out_mux.mode <= sel_ir16;
-- out_16.instruction <= op_mem & op_mem_st32 & std_logic_vector(sp_num) & std_logic_vector(sr_num);
-- out_imem.en <= '1';
-- out_irq.ack <= '1';
when irq_decSP1 =>
out_pc.stall <= '1';
out_mux.mode <= sel_ir16;
out_16.instruction <= op_addi & std_logic_vector(sp_num) & std_logic_vector(to_signed(-4, 8));
out_imem.en <= '0';
--when irq_decSP2 =>
-- out_pc.stall <= '1';
-- out_mux.mode <= sel_ir16;
--out_16.instruction <= op_addi & std_logic_vector(sp_num) & std_logic_vector(to_signed(-4, 8));
--out_imem.en <= '0';
end case;
end process output;
-- state transition (clocked part)
state_transition : process(clk) is
begin
if (rising_edge(clk)) then
if (rst = '1') then
state <= reset;
elsif (stall = '0') then
state <= state; -- in default: keep state
-- check for interrupt request
if (
-- not near branch and not in multicycle operation
(in_pre.mode /= sel_branch) and (state = normal)
-- interrupt request
and (in_irq.req = '1')
-- priority higher than runtime priority or non maskable interrupt
and ((unsigned(in_irq.priority) > in_dp.runtime_priority) or (in_irq.nmi = '1'))
) then
-- in normal mode and irq request
--state <= irq_pushSR;
state <= irq_decSP1;
multicycleinstruction <= (others => '0');
multicycleinstruction(16 + irq_prio_width - 1 downto 16) <= std_logic_vector(in_irq.priority);
multicycleinstruction(irq_num_width downto 0) <= std_logic_vector(in_irq.num) & "0";
-- synthesis translate_off
assert false report "current runtime priority is " & integer'image(to_integer(in_dp.runtime_priority)) & ". IRQ priority is " & integer'image(to_integer(unsigned(in_irq.priority))) & "." severity note;
assert false report "handle irq request #" & integer'image(to_integer(unsigned(in_irq.num))) severity note;
-- synthesis translate_on
else
-- no irq request valid
-- for state transition diagram see documentation
case state is
when normal =>
case in_pre.mode is
when sel_normal16 =>
state <= normal;
when sel_normal32 =>
state <= normal;
when sel_call =>
state <= copyPCtoLR;
when sel_branch =>
if (execute_branch_delay_slot) then
state <= normal;
else
state <= branchdelay;
end if;
when sel_trap =>
state <= normal;
when sel_reti =>
--state <= reti_incSP1;
state <= reti_popLR;
when sel_stall =>
state <= normal;
end case;
when copyPCtoLR =>
state <= normal;
when branchdelay =>
state <= normal;
--! group by multicycle opertation/pseudo-instruction -TF
-- i.e. IRQ entry (multicycle)
when irq_decSP1 =>
state <= irq_pushSR;
when irq_pushSR =>
--state <= irq_decSP2;
state <= irq_pushLR;
--when irq_decSP2 =>
-- state <= irq_pushLR;
when irq_pushLR =>
state <= irq_setSR;
when irq_setSR =>
state <= irq_setPC;
when irq_setPC =>
state <= copyPCtoLR;
when reti_popLR =>
state <= reti_incSP1;
when reti_incSP1 =>
state <= reti_popSR;
when reti_popSR =>
state <= reti_incSP2;
when reti_incSP2 =>
state <= normal;
when reset =>
state <= reset2;
when reset2 =>
state <= normal;
end case;
end if;
end if;
end if;
end process state_transition;
end architecture RTL;

103
soc/core/decoder_pre.vhd Normal file
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-- See the file "LICENSE" for the full license governing this code. --
library ieee;
use ieee.std_logic_1164.all;
use work.lt16x32_internal.all;
-- the decoder_pre checks the new instruction for basic data, which is needed in the finite state machine as input.
-- it is fully combinatoric
entity decoder_pre is
port(
-- signals from instruction memory
input : in imem_dec;
-- signals to decoder finite state machine
output : out pre_fsm
);
end entity decoder_pre;
architecture RTL of decoder_pre is
begin
-- decodes instruction memory input and outputs signals to finite state machine
decode : process(input) is
-- fetched instruction, 16 bit instructions stored in (15 downto 0) bits
variable instruction : std_logic_vector(31 downto 0);
-- width of fetched instruction
variable instruction_width : instruction_width_type;
-- instruction mode, temporary storage for clean logic/output seperation
variable instruction_mode : instruction_mode_type;
begin
-- needed to avoid latch generation for upper half word
instruction := (others => '0');
if (input.ready = '1') then
-- instruction memory is ready
-- get relevant instruction from instruction word and extract instruction width
case input.instruction_halfword_select is
when '0' => -- 32bit aligned, might be 32bit instruction
if (input.read_data(31 downto 28) = "1111") then
-- is 32 bit instruction
instruction_width := sel_32bit;
instruction(31 downto 0) := std_logic_vector(input.read_data(31 downto 0));
else
-- is 16 bit instruction
instruction_width := sel_16bit;
instruction(15 downto 0) := std_logic_vector(input.read_data(31 downto 16));
end if;
when '1' => -- lower 16bit, always 16 bit instruction
instruction_width := sel_16bit;
instruction(15 downto 0) := std_logic_vector(input.read_data(15 downto 0));
when others =>
instruction_width := sel_16bit;
instruction(15 downto 0) := op_or & "0000" & "0000" & "0000";
assert false report "instruction halfword select must be either 0 or 1" severity warning;
end case;
-- check for special, multicycle or normal instructions
if (instruction_width = sel_16bit) then
-- 16 bit instructions
if (instruction(15 downto 10) = op_bct & op_bct_call) then
-- instruction is call
instruction_mode := sel_call;
elsif (instruction(15 downto 10) = op_bct & op_bct_trap) then
-- instruction is trap
instruction_mode := sel_trap;
elsif (instruction(15 downto 9) = op_bct & op_bct_reti) then
-- instruction is reti
instruction_mode := sel_reti;
elsif (instruction(15 downto 10) = op_bct & op_bct_branch) then
-- instruction is branch
instruction_mode := sel_branch;
elsif (instruction(15 downto 10) = op_bct & op_bct_table) then
-- instruction is branch to table
instruction_mode := sel_branch;
else
-- no special instruction
instruction_mode := sel_normal16;
end if;
else
-- 32bit instructions
instruction_mode := sel_normal32;
end if;
else
-- imem not ready
instruction(15 downto 0) := nop16;
instruction_mode := sel_stall;
end if;
-- output
output.instruction <= instruction;
output.mode <= instruction_mode;
end process decode;
end architecture RTL;

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