29 lines
761 B
VHDL
29 lines
761 B
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.lt16x32_internal.all;
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-- the decoder_32bit decodes all 32bit instructions and is fully combinatoric
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entity decoder_32bit is
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port(
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-- input signals from decoder finite state machine
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input : in fsm_dec32;
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-- output signals to control path (or decoder mux)
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output : out dec_cp
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);
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end entity decoder_32bit;
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architecture RTL of decoder_32bit is
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begin
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-- currently, there are no 32bit instructions, so output is
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-- always nop and hardfault
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output.s1 <= get_default_dec_cp_s1;
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output.s2 <= get_default_dec_cp_s2;
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output.s3 <= get_default_dec_cp_s3;
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output.hardfault <= '1';
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end architecture RTL;
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