142 lines
3.7 KiB
VHDL
142 lines
3.7 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.lt16x32_global.all;
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-- this testbench testes the core in total
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entity core_tb is
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end entity core_tb;
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architecture RTL of core_tb is
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-- clock period, f = 1/period
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constant period : time := 10 ns;
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component core
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port(clk : in std_logic;
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rst : in std_logic;
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stall : in std_logic;
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in_dmem : in dmem_core;
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out_dmem : out core_dmem;
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in_imem : in imem_core;
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out_imem : out core_imem;
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in_irq : in irq_core;
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out_irq : out core_irq;
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hardfault : out std_logic);
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end component core;
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component memory
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generic(filename : string := "program.ram";
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size : integer := 256;
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imem_latency : time := 5 ns;
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dmem_latency : time := 5 ns);
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port(clk : in std_logic;
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rst : in std_logic;
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in_dmem : in core_dmem;
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out_dmem : out dmem_core;
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in_imem : in core_imem;
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out_imem : out imem_core;
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fault : out std_logic;
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out_byte : out std_logic_vector(7 downto 0));
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end component memory;
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component irq_controller
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port(clk : in std_logic;
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rst : in std_logic;
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in_proc : in core_irq;
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out_proc : out irq_core;
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irq_lines : in std_logic_vector((2 ** irq_num_width) - 1 downto 0));
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end component irq_controller;
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-- clock signal
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signal clk : std_logic := '0';
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-- reset signal, active high
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signal rst : std_logic := '1';
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-- outbyte signal
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signal out_byte : std_logic_vector(7 downto 0);
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-- signals between instances
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signal dmem_proc_signal : dmem_core;
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signal proc_dmem_signal : core_dmem;
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signal imem_proc_signal : imem_core;
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signal proc_imem_signal : core_imem;
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signal irq_proc_signal : irq_core;
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signal proc_irq_signal : core_irq;
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signal irq_lines : std_logic_vector((2 ** irq_num_width) - 1 downto 0);
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begin
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core_inst : component core
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port map(clk => clk,
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rst => rst,
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stall => '0',
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in_dmem => dmem_proc_signal,
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out_dmem => proc_dmem_signal,
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in_imem => imem_proc_signal,
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out_imem => proc_imem_signal,
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in_irq => irq_proc_signal,
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out_irq => proc_irq_signal,
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hardfault => irq_lines(1));
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memory_inst : component memory
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generic map(--filename => "sample-programs\test_endianess2.ram",
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--filename => "sample-programs\rawhztest.ram",
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filename => "sample-programs\rdmem.ram",
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size => 256,
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imem_latency => 0 ns,
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dmem_latency => 0 ns)
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port map(clk => clk,
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rst => rst,
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in_dmem => proc_dmem_signal,
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out_dmem => dmem_proc_signal,
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in_imem => proc_imem_signal,
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out_imem => imem_proc_signal,
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fault => irq_lines(2),
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out_byte => out_byte);
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irq_controller_inst : component irq_controller
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port map(clk => clk,
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rst => rst,
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in_proc => proc_irq_signal,
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out_proc => irq_proc_signal,
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irq_lines => irq_lines);
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-- irq line stimuli
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irq_stimuli : process is
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begin
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irq_lines(irq_lines'high downto 3) <= (others => '0');
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irq_lines(0) <= '0';
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-- irq0 is reset
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-- irq1 is hardfault
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-- irq2 is memfault
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-- wait for 600 ns;
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-- wait until rising_edge(clk);
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-- irq_lines(3) <= '1';
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-- irq_lines(4) <= '1';
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-- wait until rising_edge(clk);
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-- irq_lines(3) <= '0';
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-- irq_lines(4) <= '0';
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wait;
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end process irq_stimuli;
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-- clock stimuli
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clock : process is
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begin
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clk <= not clk;
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wait for period / 2;
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end process clock;
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-- reset stimuli
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reset : process is
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begin
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rst <= '1';
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wait for 3.5 * period;
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rst <= '0';
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wait;
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end process reset;
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end architecture RTL;
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