143 lines
2.9 KiB
VHDL
143 lines
2.9 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.lt16x32_internal.all;
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use work.lt16x32_global.all;
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use work.wishbone.all;
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use work.config.all;
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-- TODO: check core(big/little endian) -> assume as little !!
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entity corewrapper is
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port(
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clk : in std_logic;
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rst : in std_logic;
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in_imem : in imem_core;
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out_imem : out core_imem;
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in_proc : in irq_core;
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out_proc : out core_irq;
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hardfault : out std_logic;
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-- wb master port
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wmsti : in wb_mst_in_type;
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wmsto : out wb_mst_out_type
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);
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end entity corewrapper;
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architecture RTL of corewrapper is
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signal wbmo : wb_mst_out_type := wbm_out_none;
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--signal indmem : dmem_core;
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signal in_dmem : dmem_core;
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signal out_dmem : core_dmem;
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-- signal inimem : imem_core;
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-- signal outimem : core_imem;
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--//////////////////////////////////////////////////////
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-- component
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--//////////////////////////////////////////////////////
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component core
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port(
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clk : in std_logic;
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rst : in std_logic;
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stall : in std_logic;
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in_dmem : in dmem_core;
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out_dmem : out core_dmem;
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in_imem : in imem_core;
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out_imem : out core_imem;
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in_irq : in irq_core;
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out_irq : out core_irq;
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hardfault : out std_logic
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);
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end component;
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component core2wb
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port(
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clk : in std_logic;
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rst : in std_logic;
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in_dmem : out dmem_core;
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out_dmem : in core_dmem;
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-- wb master port
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wmsti : in wb_mst_in_type;
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wmsto : out wb_mst_out_type
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);
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end component;
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begin
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--//////////////////////////////////////////////////////
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-- Instantiate
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--//////////////////////////////////////////////////////
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--
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core_inst: core
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port map(
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clk => clk,
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rst => rst,
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stall => '0', -- no stall for now -- wmsti.stall
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in_dmem => in_dmem,
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out_dmem => out_dmem,
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in_imem => in_imem, -- inimem,
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out_imem => out_imem, -- outimem,
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in_irq => in_proc,
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out_irq => out_proc,
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hardfault => hardfault
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);
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core2wb_inst: core2wb
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port map(
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clk => clk,
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rst => rst,
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in_dmem => in_dmem,
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out_dmem => out_dmem,
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-- wb master port
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wmsti => wmsti,
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wmsto => wmsto
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);
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--//////////////////////////////////////////////////////
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-- I - mem
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--//////////////////////////////////////////////////////
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-- core connect directly to the mem
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-- imem: process(clk)
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-- begin
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-- if rising_edge(clk) then
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-- if rst = '1' then
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-- -- to core
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-- inimem.read_data <= (others=>'-');
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-- inimem.ready <= '0';
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-- -- out from core
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-- outimem.read_addr <= (others=>'0');
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-- outimem.read_en <= '0';
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--
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-- out_imem.read_addr <= (others=>'0');
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-- out_imem.read_en <= '0';
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-- else
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-- -- to core
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-- inimem <= in_imem;
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-- -- out from core
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-- out_imem <= outimem;
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-- end if;
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-- end if;
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-- end process;
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end architecture RTL;
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