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f969c08ee2e69eed37f585404545b0058466cf29
gem5/src/cpu/o3
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Melissa Jost f969c08ee2 cpu: Remove duplicate base inst and op stats 
This change removes any duplicated numInsts, numOps, ipc, and
cpi stats, and makes sure that numInsts is only tracked per
thread.

Change-Id: I45d0f6cb5c523e53c0602b5152a5108108476936
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69109
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2023-05-08 19:09:51 +00:00
..
probe
python: Fix multiline quotes in a single line
2022-11-29 23:44:38 +00:00
BaseO3Checker.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
BaseO3CPU.py
arch,cpu: Add boilerplate support for matrix registers
2023-01-17 10:09:56 +00:00
checker.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
checker.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
comm.hh
misc: Stop including config/the_isa.hh.
2022-08-20 07:30:32 +00:00
commit.cc
cpu: Remove duplicate base inst and op stats
2023-05-08 19:09:51 +00:00
commit.hh
cpu: Remove duplicated execute stats
2023-05-08 19:09:51 +00:00
cpu.cc
cpu: Remove duplicated execute stats
2023-05-08 19:09:51 +00:00
cpu.hh
cpu: Remove duplicated execute stats
2023-05-08 19:09:51 +00:00
decode.cc
cpu-o3: Resolve the skid buffer overflow issue at decode stage
2023-01-06 00:54:30 +00:00
decode.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
dep_graph.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dyn_inst_ptr.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dyn_inst.cc
misc: Rename DEBUG macro into GEM5_DEBUG
2023-03-21 06:53:55 +00:00
dyn_inst.hh
cpu: Remove duplicated execute stats
2023-05-08 19:09:51 +00:00
fetch.cc
cpu: Remove duplicated execute stats
2023-05-08 19:09:51 +00:00
fetch.hh
cpu: Remove duplicated execute stats
2023-05-08 19:09:51 +00:00
free_list.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
free_list.hh
cpu-o3: Manage per-register-type free lists with an array.
2022-03-01 22:01:01 +00:00
fu_pool.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
fu_pool.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
FuncUnitConfig.py
arch-x86,cpu: Override the int div latency local to x86.
2022-09-02 10:20:51 +00:00
FUPool.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
iew.cc
cpu: Remove duplicated execute stats
2023-05-08 19:09:51 +00:00
iew.hh
cpu: Remove duplicated execute stats
2023-05-08 19:09:51 +00:00
inst_queue.cc
misc: Rename DEBUG macro into GEM5_DEBUG
2023-03-21 06:53:55 +00:00
inst_queue.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
limits.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
lsq_unit.cc
misc: Stop including config/the_isa.hh.
2022-08-20 07:30:32 +00:00
lsq_unit.hh
misc: Stop including config/the_isa.hh.
2022-08-20 07:30:32 +00:00
lsq.cc
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
lsq.hh
cpu: Handle external TLBI Sync requests in O3CPU
2022-04-11 07:31:34 +00:00
mem_dep_unit.cc
misc: Rename DEBUG macro into GEM5_DEBUG
2023-03-21 06:53:55 +00:00
mem_dep_unit.hh
misc: Rename DEBUG macro into GEM5_DEBUG
2023-03-21 06:53:55 +00:00
O3Checker.py
arch,cpu: Centralize the single arch CPU Simobject files.
2022-09-02 10:20:51 +00:00
O3CPU.py
arch,cpu: Centralize the single arch CPU Simobject files.
2022-09-02 10:20:51 +00:00
regfile.cc
arch,cpu: Add boilerplate support for matrix registers
2023-01-17 10:09:56 +00:00
regfile.hh
arch,cpu: Add boilerplate support for matrix registers
2023-01-17 10:09:56 +00:00
rename_map.cc
misc: Stop including arch/vecregs.hh and fix transitive includes.
2022-08-04 20:22:44 +00:00
rename_map.hh
arch,cpu: Remove the idea of a zero register.
2022-06-07 18:26:33 +00:00
rename.cc
arch,cpu: Add boilerplate support for matrix registers
2023-01-17 10:09:56 +00:00
rename.hh
arch,cpu: Add boilerplate support for matrix registers
2023-01-17 10:09:56 +00:00
rob.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
rob.hh
misc: Stop including config/the_isa.hh.
2022-08-20 07:30:32 +00:00
SConscript
arch,cpu: Centralize the single arch CPU Simobject files.
2022-09-02 10:20:51 +00:00
scoreboard.cc
arch,cpu: Remove the idea of a zero register.
2022-06-07 18:26:33 +00:00
scoreboard.hh
arch,cpu: Remove the idea of a zero register.
2022-06-07 18:26:33 +00:00
store_set.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
store_set.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
thread_context.cc
misc: Stop including config/the_isa.hh.
2022-08-20 07:30:32 +00:00
thread_context.hh
misc: Stop including config/the_isa.hh.
2022-08-20 07:30:32 +00:00
thread_state.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
thread_state.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00