arch-x86,cpu: Override the int div latency local to x86.

Remove the ISA check when selecting the default integer division latency
for O3. Instead, create a different default FUPool which is specific to
x86.

Change-Id: I1ef9ee94f4b16aebe03e043df5cdc6167efe6e64
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52497
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

src/arch/x86/X86CPU.py

@@ -30,6 +30,8 @@ from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
 from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
 from m5.objects.BaseO3CPU import BaseO3CPU
 from m5.objects.BaseMinorCPU import BaseMinorCPU
+from m5.objects.FuncUnit import *
+from m5.objects.FUPool import *
 from m5.objects.X86Decoder import X86Decoder
 from m5.objects.X86MMU import X86MMU
 from m5.objects.X86LocalApic import X86LocalApic
@@ -55,6 +57,34 @@ class X86TimingSimpleCPU(BaseTimingSimpleCPU, X86CPU):
     mmu = X86MMU()
 
 
+class X86IntMultDiv(IntMultDiv):
+    # DIV and IDIV instructions in x86 are implemented using a loop which
+    # issues division microops.  The latency of these microops should really be
+    # one (or a small number) cycle each since each of these computes one bit
+    # of the quotient.
+    opList = [
+        OpDesc(opClass="IntMult", opLat=3),
+        OpDesc(opClass="IntDiv", opLat=1, pipelined=False),
+    ]
+
+    count = 2
+
+
+class DefaultX86FUPool(FUPool):
+    FUList = [
+        IntALU(),
+        X86IntMultDiv(),
+        FP_ALU(),
+        FP_MultDiv(),
+        ReadPort(),
+        SIMD_Unit(),
+        PredALU(),
+        WritePort(),
+        RdWrPort(),
+        IprPort(),
+    ]
+
+
 class X86O3CPU(BaseO3CPU, X86CPU):
     mmu = X86MMU()
     needsTSO = True
@@ -67,6 +97,12 @@ class X86O3CPU(BaseO3CPU, X86CPU):
     # never be the bottleneck here.
     numPhysCCRegs = Self.numPhysIntRegs * 5
 
+    # DIV and IDIV instructions in x86 are implemented using a loop which
+    # issues division microops.  The latency of these microops should really be
+    # one (or a small number) cycle each since each of these computes one bit
+    # of the quotient.
+    fuPool = DefaultX86FUPool()
+
 
 class X86MinorCPU(BaseMinorCPU, X86CPU):
     mmu = X86MMU()

src/cpu/o3/FuncUnitConfig.py

@@ -54,13 +54,6 @@ class IntMultDiv(FUDesc):
         OpDesc(opClass="IntDiv", opLat=20, pipelined=False),
     ]
 
-    # DIV and IDIV instructions in x86 are implemented using a loop which
-    # issues division microops.  The latency of these microops should really be
-    # one (or a small number) cycle each since each of these computes one bit
-    # of the quotient.
-    if buildEnv["USE_X86_ISA"]:
-        opList[1].opLat = 1
-
     count = 2