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f73caae20fed7b4500a724ac85c20b637ee353a1
gem5/src/cpu
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Giacomo Travaglini f73caae20f cpu: Add byteEnable assertions to readMem and initateMemRead 
Those are already present in writeMem; looking for consistency

Change-Id: Ib85e0db228bc73e3ac64155d1290444cf6864a8c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23281
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-12-11 15:07:52 +00:00
..
checker
cpu: Add byteEnable assertions to readMem and initateMemRead
2019-12-11 15:07:52 +00:00
kvm
cpu: Get rid of the nextInstEventCount method.
2019-10-25 22:42:31 +00:00
minor
cpu: Add byteEnable assertions to readMem and initateMemRead
2019-12-11 15:07:52 +00:00
nocpu
arch, cpu: Factor out the ExecContext into a proper base class
2014-09-03 07:42:22 -04:00
o3
arch,cpu,sim: Push syscall number determination up to processes.
2019-12-10 23:58:14 +00:00
pred
cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB and 64KB)
2019-07-08 18:39:55 +00:00
simple
cpu: Add byteEnable assertions to readMem and initateMemRead
2019-12-11 15:07:52 +00:00
testers
cpu: Make use of DRAMCtrl::AddrMap in the traffic generators
2019-09-30 20:36:30 +00:00
trace
cpu: Make get(Data|Inst)Port return a Port and not a MasterPort.
2019-08-28 08:25:51 +00:00
activity.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
activity.hh
cpu: Useful getters for ActivityRecorder
2014-05-09 18:58:48 -04:00
base_dyn_inst_impl.hh
cpu-o3: Add support for pinned writes
2019-05-30 15:55:59 +00:00
base_dyn_inst.hh
cpu: Add byteEnable assertions to readMem and initateMemRead
2019-12-11 15:07:52 +00:00
base.cc
cpu: log thread activate and suspend with --debug-flags Thread
2019-11-25 12:02:30 +00:00
base.hh
cpu: Switch off of the CPU's comInstEventQueue.
2019-10-25 22:42:31 +00:00
BaseCPU.py
cpu,arm: Push the stage 2 MMUs out of the CPU into the TLBs.
2019-10-19 01:49:55 +00:00
CheckerCPU.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
cpuevent.cc
Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
2006-06-06 17:32:21 -04:00
cpuevent.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
CPUTracers.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
decode_cache.hh
arch: cpu: Make the ExtMachInst type a template argument in InstMap.
2018-03-27 10:57:54 +00:00
dummy_checker.cc
cpu: Get rid of load count based events.
2019-10-17 22:00:16 +00:00
dummy_checker.hh
cpu: Add header files for checker CPUs
2012-11-02 11:32:01 -05:00
DummyChecker.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
exec_context.cc
arch, cpu: Factor out the ExecContext into a proper base class
2014-09-03 07:42:22 -04:00
exec_context.hh
arch,cpu,sim: Push syscall number determination up to processes.
2019-12-10 23:58:14 +00:00
exetrace.cc
cpu: prefix ExecEnable to the native trace to match DPRINTF
2019-11-26 12:46:59 +00:00
exetrace.hh
cpu: prefix ExecEnable to the native trace to match DPRINTF
2019-11-26 12:46:59 +00:00
func_unit.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
func_unit.hh
cpu: Fix issue identified by UBSan
2015-07-30 03:41:22 -04:00
FuncUnit.py
arch-arm,cpu: Add initial support for Arm SVE
2019-03-14 10:42:27 +00:00
inst_pb_trace.cc
cpu: Stop extracting inst_flags from the machInst.
2018-03-27 10:57:36 +00:00
inst_pb_trace.hh
cpu: Use the new asBytes function in the protobuf inst tracer.
2018-03-26 22:34:03 +00:00
inst_res.hh
arch,cpu: Add vector predicate registers
2019-01-30 16:57:54 +00:00
inst_seq.hh
build: fix compile problems pointed out by gcc 4.4
2009-11-04 16:57:01 -08:00
InstPBTrace.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
inteltrace.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
inteltrace.hh
base: remove Trace::enabled flag
2015-09-30 15:21:55 -05:00
intr_control_noisa.cc
arch: Resurrect the NOISA build target and rename it NULL
2013-09-04 13:22:57 -04:00
intr_control.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
intr_control.hh
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
IntrControl.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
nativetrace.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
nativetrace.hh
style: fix missing spaces in control statements
2016-02-06 17:21:19 -08:00
op_class.hh
arch-arm,cpu: Add initial support for Arm SVE
2019-03-14 10:42:27 +00:00
pc_event.cc
cpu,sim: Get rid of a bunch of conditional compilation for PCEvents.
2019-10-25 22:42:31 +00:00
pc_event.hh
cpu: Pass the address to check into the PCEventQueue service method.
2019-10-25 22:42:31 +00:00
profile.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
profile.hh
arch: Use const StaticInstPtr references where possible
2014-09-27 09:08:36 -04:00
quiesce_event.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
quiesce_event.hh
clang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 12:05:52 -05:00
reg_class.cc
arch,cpu: Add vector predicate registers
2019-01-30 16:57:54 +00:00
reg_class.hh
arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0
2019-08-21 12:17:17 +00:00
SConscript
base: generalize ExecTicks to all messages with FmtTicksOff
2019-11-26 12:46:59 +00:00
simple_thread.cc
cpu: Switch off of the CPU's comInstEventQueue.
2019-10-25 22:42:31 +00:00
simple_thread.hh
arch,cpu,sim: Push syscall number determination up to processes.
2019-12-10 23:58:14 +00:00
smt.hh
includes: fix up code after sorting
2011-04-15 10:44:14 -07:00
static_inst_fwd.hh
cpu: Don't forward declare RefCountingPtr
2014-08-13 06:57:26 -04:00
static_inst.cc
cpu: Add a pointer to a generic Nop StaticInst.
2017-12-22 00:27:20 +00:00
static_inst.hh
arch,cpu: Add vector predicate registers
2019-01-30 16:57:54 +00:00
StaticInstFlags.py
cpu: add a new instruction type 'Atomic'
2018-06-14 22:41:30 +00:00
thread_context.cc
arch,cpu: Get rid of ISA_HAS_CC_REGS and its associated ifdefs.
2019-11-26 03:01:32 +00:00
thread_context.hh
arch,cpu,sim: Push syscall number determination up to processes.
2019-12-10 23:58:14 +00:00
thread_state.cc
cpu, mem: Add new getSendFunctional method to the base CPU.
2019-08-28 07:58:56 +00:00
thread_state.hh
arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.
2019-05-30 14:20:03 +00:00
timebuf.hh
style: remove trailing whitespace
2016-02-06 17:21:18 -08:00
timing_expr.cc
cpu: Simplify the rename interface and use RegId
2017-07-05 14:43:49 +00:00
timing_expr.hh
arch: Use const StaticInstPtr references where possible
2014-09-27 09:08:36 -04:00
TimingExpr.py
cpu: `Minor' in-order CPU model
2014-07-23 16:09:04 -05:00
translation.hh
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
utils.hh
cpu,mem: Add support for partial loads/stores and wide mem. accesses
2019-05-11 12:48:58 +00:00