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cpu: Make use of DRAMCtrl::AddrMap in the traffic generators

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Use the enum defined in the memory controller rather than custom
strings and int that are later converted to the DRAMCtrl::AddrMap
enum.

Change-Id: Ie5b19f915f9990fd2b7505d4d1b17b6fc2100f9e
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21080
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Nikos Nikoleris
2019-09-12 14:36:52 +01:00
parent 772ca27a97
commit 4c4520ca00
9 changed files with 48 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
configs/dram/low_power_sweep.py
View File

@@ -1,4 +1,4 @@
# Copyright (c) 2014-2015, 2017 ARM Limited
# Copyright (c) 2014-2015, 2017, 2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -78,8 +78,9 @@ parser.add_argument("--itt-list", "-t", default="1 20 100",
parser.add_argument("--rd-perc", type=int, default=100,
help = "Percentage of read commands")
parser.add_argument("--addr-map", type=int, default=1,
help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo")
parser.add_argument("--addr-map",
choices=m5.objects.AddrMap.vals,
default="RoRaBaCoCh", help = "DRAM address map policy")
parser.add_argument("--idle-end", type=int, default=50000000,
help = "time in ps of an idle period at the end ")
@@ -118,14 +119,7 @@ if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
system.mem_ctrls[0].null = True
# Set the address mapping based on input argument
# Default to RoRaBaCoCh
if args.addr_map == 0:
system.mem_ctrls[0].addr_mapping = "RoCoRaBaCh"
elif args.addr_map == 1:
system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh"
else:
fatal("Did not specify a valid address map argument")
system.mem_ctrls[0].addr_mapping = args.addr_map
system.mem_ctrls[0].page_policy = args.page_policy
# We create a traffic generator state for each param combination we want to
@@ -192,6 +186,8 @@ cfg_file.write("""# STATE state# period mode=DRAM
# read_percent start_addr end_addr req_size min_itt max_itt data_limit
# stride_size page_size #banks #banks_util addr_map #ranks\n""")
addr_map = m5.objects.AddrMap.map[args.addr_map]
nxt_state = 0
for itt_max in itt_max_values:
for bank in bank_util_values:
@@ -200,7 +196,7 @@ for itt_max in itt_max_values:
"%d %d %d %d %d %d %d %d %d\n" %
(nxt_state, period, "DRAM", args.rd_perc, max_addr,
burst_size, itt_min, itt_max, 0, stride_size,
page_size, nbr_banks, bank, args.addr_map,
page_size, nbr_banks, bank, addr_map,
args.mem_ranks))
nxt_state = nxt_state + 1

19
configs/dram/sweep.py
View File

@@ -1,4 +1,4 @@
# Copyright (c) 2014-2015, 2018 ARM Limited
# Copyright (c) 2014-2015, 2018-2019 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -78,8 +78,9 @@ parser.add_option("--mode", type="choice", default="DRAM",
help = "DRAM: Random traffic; \
DRAM_ROTATE: Traffic rotating across banks and ranks")
parser.add_option("--addr_map", type="int", default=1,
help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo")
parser.add_argument("--addr-map",
choices=m5.objects.AddrMap.vals,
default="RoRaBaCoCh", help = "DRAM address map policy")
(options, args) = parser.parse_args()
@@ -122,13 +123,7 @@ if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
system.mem_ctrls[0].null = True
# Set the address mapping based on input argument
# Default to RoRaBaCoCh
if options.addr_map == 0:
system.mem_ctrls[0].addr_mapping = "RoCoRaBaCh"
elif options.addr_map == 1:
system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh"
else:
fatal("Did not specify a valid address map argument")
system.mem_ctrls[0].addr_mapping = args.addr_map
# stay in each state for 0.25 ms, long enough to warm things up, and
# short enough to avoid hitting a refresh
@@ -183,6 +178,8 @@ root.system.mem_mode = 'timing'
m5.instantiate()
addr_map = m5.objects.AddrMap.map[args.addr_map]
def trace():
generator = dram_generators[options.mode](system.tgen)
for bank in range(1, nbr_banks + 1):
@@ -192,7 +189,7 @@ def trace():
0, max_addr, burst_size, int(itt), int(itt),
options.rd_perc, 0,
num_seq_pkts, page_size, nbr_banks, bank,
options.addr_map, options.mem_ranks)
addr_map, options.mem_ranks)
yield system.tgen.createExit(0)
system.tgen.start(trace())

5
src/cpu/testers/traffic_gen/base.cc
View File

@@ -55,6 +55,7 @@
#include "cpu/testers/traffic_gen/stream_gen.hh"
#include "debug/Checkpoint.hh"
#include "debug/TrafficGen.hh"
#include "enums/AddrMap.hh"
#include "params/BaseTrafficGen.hh"
#include "sim/sim_exit.hh"
#include "sim/stats.hh"
@@ -404,7 +405,7 @@ BaseTrafficGen::createDram(Tick duration,
unsigned int num_seq_pkts, unsigned int page_size,
unsigned int nbr_of_banks_DRAM,
unsigned int nbr_of_banks_util,
unsigned int addr_mapping,
Enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks)
{
return std::shared_ptr<BaseGen>(new DramGen(*this, masterID,
@@ -429,7 +430,7 @@ BaseTrafficGen::createDramRot(Tick duration,
unsigned int page_size,
unsigned int nbr_of_banks_DRAM,
unsigned int nbr_of_banks_util,
unsigned int addr_mapping,
Enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks,
unsigned int max_seq_count_per_rank)
{

5
src/cpu/testers/traffic_gen/base.hh
View File

@@ -47,6 +47,7 @@
#include <unordered_map>
#include "base/statistics.hh"
#include "enums/AddrMap.hh"
#include "mem/qport.hh"
#include "sim/clocked_object.hh"
@@ -278,7 +279,7 @@ class BaseTrafficGen : public ClockedObject
uint8_t read_percent, Addr data_limit,
unsigned int num_seq_pkts, unsigned int page_size,
unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
unsigned int addr_mapping,
Enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks);
std::shared_ptr<BaseGen> createDramRot(
@@ -288,7 +289,7 @@ class BaseTrafficGen : public ClockedObject
uint8_t read_percent, Addr data_limit,
unsigned int num_seq_pkts, unsigned int page_size,
unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
unsigned int addr_mapping,
Enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks,
unsigned int max_seq_count_per_rank);

25
src/cpu/testers/traffic_gen/dram_gen.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012-2013, 2016-2018 ARM Limited
* Copyright (c) 2012-2013, 2016-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -47,7 +47,7 @@
#include "base/random.hh"
#include "base/trace.hh"
#include "debug/TrafficGen.hh"
#include "enums/AddrMap.hh"
DramGen::DramGen(SimObject &obj,
MasterID master_id, Tick _duration,
@@ -58,7 +58,7 @@ DramGen::DramGen(SimObject &obj,
unsigned int num_seq_pkts, unsigned int page_size,
unsigned int nbr_of_banks_DRAM,
unsigned int nbr_of_banks_util,
unsigned int addr_mapping,
Enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks)
: RandomGen(obj, master_id, _duration, start_addr, end_addr,
_blocksize, cacheline_size, min_period, max_period,
@@ -73,11 +73,6 @@ DramGen::DramGen(SimObject &obj,
rankBits(floorLog2(nbr_of_ranks)),
nbrOfRanks(nbr_of_ranks)
{
if (addrMapping != 1 && addrMapping != 0) {
addrMapping = 1;
warn("Unknown address mapping specified, using RoRaBaCoCh\n");
}
if (nbr_of_banks_util > nbr_of_banks_DRAM)
fatal("Attempting to use more banks (%d) than "
"what is available (%d)\n",
@@ -115,14 +110,13 @@ DramGen::getNextPacket()
} else {
// increment the column by one
if (addrMapping == 1)
// addrMapping=1: RoRaBaCoCh/RoRaBaChCo
if (addrMapping == Enums::RoRaBaCoCh ||
addrMapping == Enums::RoRaBaChCo)
// Simply increment addr by blocksize to increment
// the column by one
addr += blocksize;
else if (addrMapping == 0) {
// addrMapping=0: RoCoRaBaCh
else if (addrMapping == Enums::RoCoRaBaCh) {
// Explicity increment the column bits
unsigned int new_col = ((addr / blocksize /
nbrOfBanksDRAM / nbrOfRanks) %
@@ -177,8 +171,8 @@ DramGen::genStartAddr(unsigned int new_bank, unsigned int new_rank)
unsigned int new_col =
random_mt.random<unsigned int>(0, columns_per_page - numSeqPkts);
if (addrMapping == 1) {
// addrMapping=1: RoRaBaCoCh/RoRaBaChCo
if (addrMapping == Enums::RoRaBaCoCh ||
addrMapping == Enums::RoRaBaChCo) {
// Block bits, then page bits, then bank bits, then rank bits
replaceBits(addr, blockBits + pageBits + bankBits - 1,
blockBits + pageBits, new_bank);
@@ -187,8 +181,7 @@ DramGen::genStartAddr(unsigned int new_bank, unsigned int new_rank)
replaceBits(addr, blockBits + pageBits + bankBits +rankBits - 1,
blockBits + pageBits + bankBits, new_rank);
}
} else if (addrMapping == 0) {
// addrMapping=0: RoCoRaBaCh
} else if (addrMapping == Enums::RoCoRaBaCh) {
// Block bits, then bank bits, then rank bits, then page bits
replaceBits(addr, blockBits + bankBits - 1, blockBits, new_bank);
replaceBits(addr, blockBits + bankBits + rankBits + pageBits - 1,

8
src/cpu/testers/traffic_gen/dram_gen.hh
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012-2013, 2017-2018 ARM Limited
* Copyright (c) 2012-2013, 2017-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -51,6 +51,7 @@
#include "base/bitfield.hh"
#include "base/intmath.hh"
#include "enums/AddrMap.hh"
#include "mem/packet.hh"
#include "random_gen.hh"
@@ -84,7 +85,6 @@ class DramGen : public RandomGen
* @param nbr_of_banks_util Number of banks to utilized,
* for N banks, we will use banks: 0->(N-1)
* @param addr_mapping Address mapping to be used,
* 0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo
* assumes single channel system
*/
DramGen(SimObject &obj,
@@ -95,7 +95,7 @@ class DramGen : public RandomGen
uint8_t read_percent, Addr data_limit,
unsigned int num_seq_pkts, unsigned int page_size,
unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
unsigned int addr_mapping,
Enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks);
PacketPtr getNextPacket();
@@ -141,7 +141,7 @@ class DramGen : public RandomGen
const unsigned int nbrOfBanksUtil;
/** Address mapping to be used */
unsigned int addrMapping;
Enums::AddrMap addrMapping;
/** Number of rank bits in DRAM address*/
const unsigned int rankBits;

10
src/cpu/testers/traffic_gen/dram_rot_gen.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012-2013, 2016-2017 ARM Limited
* Copyright (c) 2012-2013, 2016-2017, 2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -47,6 +47,7 @@
#include "base/random.hh"
#include "base/trace.hh"
#include "debug/TrafficGen.hh"
#include "enums/AddrMap.hh"
PacketPtr
DramRotGen::getNextPacket()
@@ -102,14 +103,13 @@ DramRotGen::getNextPacket()
} else {
// increment the column by one
if (addrMapping == 1)
// addrMapping=1: RoRaBaCoCh/RoRaBaChCo
if (addrMapping == Enums::RoRaBaCoCh ||
addrMapping == Enums::RoRaBaChCo)
// Simply increment addr by blocksize to
// increment the column by one
addr += blocksize;
else if (addrMapping == 0) {
// addrMapping=0: RoCoRaBaCh
else if (addrMapping == Enums::RoCoRaBaCh) {
// Explicity increment the column bits
unsigned int new_col = ((addr / blocksize /

6
src/cpu/testers/traffic_gen/dram_rot_gen.hh
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012-2013, 2017-2018 ARM Limited
* Copyright (c) 2012-2013, 2017-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -52,6 +52,7 @@
#include "base/bitfield.hh"
#include "base/intmath.hh"
#include "dram_gen.hh"
#include "enums/AddrMap.hh"
#include "mem/packet.hh"
class DramRotGen : public DramGen
@@ -84,7 +85,6 @@ class DramRotGen : public DramGen
* for N banks, we will use banks: 0->(N-1)
* @param nbr_of_ranks Number of ranks utilized,
* @param addr_mapping Address mapping to be used,
* 0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo
* assumes single channel system
*/
DramRotGen(SimObject &obj, MasterID master_id, Tick _duration,
@@ -94,7 +94,7 @@ class DramRotGen : public DramGen
uint8_t read_percent, Addr data_limit,
unsigned int num_seq_pkts, unsigned int page_size,
unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
unsigned int addr_mapping,
Enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks,
unsigned int max_seq_count_per_rank)
: DramGen(obj, master_id, _duration, start_addr, end_addr,

8
src/cpu/testers/traffic_gen/traffic_gen.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012-2013, 2016-2018 ARM Limited
* Copyright (c) 2012-2013, 2016-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -223,12 +223,14 @@ TrafficGen::parseConfig()
unsigned int page_size;
unsigned int nbr_of_banks_DRAM;
unsigned int nbr_of_banks_util;
unsigned int addr_mapping;
unsigned _addr_mapping;
unsigned int nbr_of_ranks;
is >> stride_size >> page_size >> nbr_of_banks_DRAM >>
nbr_of_banks_util >> addr_mapping >>
nbr_of_banks_util >> _addr_mapping >>
nbr_of_ranks;
Enums::AddrMap addr_mapping =
static_cast<Enums::AddrMap>(_addr_mapping);
if (stride_size > page_size)
warn("DRAM generator stride size (%d) is greater "