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cpu,arm: Push the stage 2 MMUs out of the CPU into the TLBs.

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This regularizes the TLB setup in the CPU so that ARM is no longer a
special case with extra objects.

Change-Id: I739b82578ff74f8f9777cd7e34cd5227b47b186c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21842
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Gabe Black
2019-10-15 21:48:31 -07:00
parent b6ef760ebb
commit 9d3b9e96c5
2 changed files with 10 additions and 8 deletions
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10
src/arch/arm/ArmTLB.py
View File

@@ -90,11 +90,17 @@ class ArmStage2MMU(SimObject):
class ArmStage2IMMU(ArmStage2MMU):
# We rely on the itb being a parameter of the CPU, and get the
# appropriate object that way
tlb = Parent.itb
tlb = Parent.any
stage2_tlb = ArmStage2TLB()
class ArmStage2DMMU(ArmStage2MMU):
# We rely on the dtb being a parameter of the CPU, and get the
# appropriate object that way
tlb = Parent.dtb
tlb = Parent.any
stage2_tlb = ArmStage2TLB()
class ArmITB(ArmTLB):
stage2_mmu = ArmStage2IMMU()
class ArmDTB(ArmTLB):
stage2_mmu = ArmStage2DMMU()

8
src/cpu/BaseCPU.py
View File

@@ -83,8 +83,7 @@ elif buildEnv['TARGET_ISA'] == 'mips':
from m5.objects.MipsISA import MipsISA as ArchISA
ArchISAsParam = VectorParam.MipsISA
elif buildEnv['TARGET_ISA'] == 'arm':
from m5.objects.ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB
from m5.objects.ArmTLB import ArmStage2IMMU, ArmStage2DMMU
from m5.objects.ArmTLB import ArmDTB as ArchDTB, ArmITB as ArchITB
from m5.objects.ArmInterrupts import ArmInterrupts as ArchInterrupts
from m5.objects.ArmISA import ArmISA as ArchISA
ArchISAsParam = VectorParam.ArmISA
@@ -174,10 +173,7 @@ class BaseCPU(ClockedObject):
dtb = Param.BaseTLB(ArchDTB(), "Data TLB")
itb = Param.BaseTLB(ArchITB(), "Instruction TLB")
if buildEnv['TARGET_ISA'] == 'arm':
istage2_mmu = ArmStage2IMMU()
dstage2_mmu = ArmStage2DMMU()
elif buildEnv['TARGET_ISA'] == 'power':
if buildEnv['TARGET_ISA'] == 'power':
UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
interrupts = VectorParam.BaseInterrupts([], "Interrupt Controller")
isa = ArchISAsParam([], "ISA instance")