cpu: add a new instruction type 'Atomic'
This patch adds a new flag named 'Atomic' to support ISA implementations that use AtomicOpFunctor to handle atomic instructions instead of a pair of locking load and unlocking store. Change-Id: I1fbee6e54432396cb49dfc59ad9006b75812d115 Reviewed-on: https://gem5-review.googlesource.com/8187 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
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@@ -64,6 +64,7 @@ class StaticInstFlags(Enum):
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'IsMemRef', # References memory (load, store, or prefetch)
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'IsLoad', # Reads from memory (load or prefetch).
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'IsStore', # Writes to memory.
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'IsAtomic', # Does atomic RMW to memory.
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'IsStoreConditional', # Store conditional instruction.
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'IsIndexed', # Accesses memory with an indexed address
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# computation
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@@ -505,6 +505,7 @@ class BaseDynInst : public ExecContext, public RefCounted
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bool isMemRef() const { return staticInst->isMemRef(); }
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bool isLoad() const { return staticInst->isLoad(); }
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bool isStore() const { return staticInst->isStore(); }
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bool isAtomic() const { return staticInst->isAtomic(); }
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bool isStoreConditional() const
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{ return staticInst->isStoreConditional(); }
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bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
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@@ -144,6 +144,7 @@ class StaticInst : public RefCounted, public StaticInstFlags
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bool isMemRef() const { return flags[IsMemRef]; }
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bool isLoad() const { return flags[IsLoad]; }
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bool isStore() const { return flags[IsStore]; }
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bool isAtomic() const { return flags[IsAtomic]; }
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bool isStoreConditional() const { return flags[IsStoreConditional]; }
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bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
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bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
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