Giacomo Travaglini ba1473f2a9 arch-riscv, arch-x86: Define unique PageTableWalker flag ...

Rather than defining multiple flags (one per ISA), we should define
a single PageTableWalker flag shared by all ISAs

Change-Id: Iad460bcd9a69d5c6f90443e43feec318429165aa
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44965
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2021-04-30 09:28:00 +00:00

..

freebsd

sim: Retrofit the VPtr type.

2020-07-04 17:53:54 +00:00

linux

arch: Remove unused variable pcbb from ThreadInfo

2020-09-01 06:25:28 +00:00

BaseInterrupts.py

arch: Delete authors lists from generic arch files.

2020-02-18 03:34:56 +00:00

BaseISA.py

arch: Delete authors lists from generic arch files.

2020-02-18 03:34:56 +00:00

BaseMMU.py

misc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB

2020-10-21 09:33:39 +00:00

BaseTLB.py

misc: Replaced master/slave terminology

2020-09-10 23:02:28 +00:00

debugfaults.hh

arch,cpu,sim: Move the null and nop StaticInstPtrs to their own files.

2021-04-17 22:39:37 +00:00

decode_cache.hh

arch: Templatize the BasicDecodeCache.

2021-02-03 03:54:34 +00:00

decoder.cc

cpu,arch: Delegate fetching ROM microops to the decoder.

2020-08-25 12:41:20 +00:00

decoder.hh

cpu,arch: Delegate fetching ROM microops to the decoder.

2020-08-25 12:41:20 +00:00

htm.cc

arch, mem: Initial Hardware Transactional Memory implementation

2020-09-02 08:30:11 +00:00

htm.hh

arch: Add a virtual destructor to BaseHTMCheckpoint.

2020-09-09 07:08:53 +00:00

interrupts.hh

misc: Remove unused params() definitions

2021-02-19 23:27:34 +00:00

isa.hh

arch,cpu: Move TheISA::copyRegs to TheISA::ISA::copyRegsFrom.

2021-03-22 21:01:33 +00:00

ISACommon.py

arch: Delete authors lists from generic arch files.

2020-02-18 03:34:56 +00:00

locked_mem.hh

arch: Don't add contents to the TheISA namespace in arch/generic.

2020-08-20 01:36:24 +00:00

memhelpers.hh

arch: Add raw read/writeMem helpers

2020-09-30 08:50:39 +00:00

mmu.cc

arch: Add generic BaseMMU

2020-10-07 10:48:14 +00:00

mmu.hh

arch-riscv: Fixed CPU switching and PLIC issue with MinorCPU

2021-03-13 08:06:29 +00:00

SConscript

arch-riscv, arch-x86: Define unique PageTableWalker flag

2021-04-30 09:28:00 +00:00

tlb.hh

misc: Standardize the way create() constructs SimObjects.

2020-10-14 12:06:44 +00:00

types.hh

arch,base,cpu: Move some type aliases into base/types.hh.

2021-04-27 02:19:11 +00:00

vec_pred_reg.hh

arch: Collapse unused size parameter from "as" VecPredReg method.

2021-04-20 00:14:09 +00:00

vec_reg.hh

arch,cpu,gpu-compute: Further simplify VecRegContainer.

2021-04-10 07:31:23 +00:00