Giacomo Travaglini e3db30912e arch-arm: Rewrite ISA::initID64 using BitUnions ...

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I3e8c7bdcf86c01eccbd90fccaa2d4306a501ed13
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70468
Tested-by: kokoro <noreply+kokoro@google.com>

2023-05-11 15:24:11 +00:00

..

amdgpu

arch-vega: Add decodings for new MI100 VOP2 insts

2023-04-28 00:48:35 +00:00

arm

arch-arm: Rewrite ISA::initID64 using BitUnions

2023-05-11 15:24:11 +00:00

generic

arch: Add a virtual method to the BaseISA to reset its ThreadContext.

2023-02-03 06:17:11 +00:00

isa_parser

misc: Use python f-strings for string formatting

2023-03-16 09:05:29 +00:00

mips

arch,base,dev,sim: Convert objects to use the HostSocket param type.

2023-04-12 02:18:22 +00:00

null

misc: Replace TARGET_ISA with USE_${ISA} variables.

2022-09-02 10:20:51 +00:00

power

arch,base,dev,sim: Convert objects to use the HostSocket param type.

2023-04-12 02:18:22 +00:00

riscv

arch-riscv: Add RV32 only Zk instruction extensions

2023-05-03 00:42:37 +00:00

sparc

misc: Fix 'unused variable' clang errors with gem5.fast

2023-05-08 22:54:06 +00:00

x86

arch,base,dev,sim: Convert objects to use the HostSocket param type.

2023-04-12 02:18:22 +00:00

micro_asm_test.py

misc: Use python f-strings for string formatting

2023-03-16 09:05:29 +00:00

micro_asm.py

misc: Use python f-strings for string formatting

2023-03-16 09:05:29 +00:00

SConscript

arch,cpu: Add boilerplate support for matrix registers

2023-01-17 10:09:56 +00:00

SConsopts

misc: Replace TARGET_ISA with USE_${ISA} variables.

2022-09-02 10:20:51 +00:00