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arch-vega: Add decodings for new MI100 VOP2 insts

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VOP2 with opcodes 55-61 were added in MI100 and are not in Vega10. This
changeset adds the decodings for these instructions.

The changeset does not implement the instructions, however the fatal
message is much more helpful for debugging compared so a generic
decode_invalid handler.

Change-Id: Ibde0880c35ff915bf8e50772df9ce263e55ca893
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70042
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
This commit is contained in:
Matthew Poremba
2023-04-21 19:36:47 -05:00
parent 316538bf8a
commit cd76f92c94
2 changed files with 84 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files

105
src/arch/amdgpu/vega/decoder.cc
View File

@@ -274,34 +274,34 @@ namespace VegaISA
&Decoder::decode_OP_VOP2__V_SUBREV_U32,
&Decoder::decode_OP_VOP2__V_SUBREV_U32,
&Decoder::decode_OP_VOP2__V_SUBREV_U32,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_OP_VOP2__V_DOT2C_F32_F16,
&Decoder::decode_OP_VOP2__V_DOT2C_F32_F16,
&Decoder::decode_OP_VOP2__V_DOT2C_F32_F16,
&Decoder::decode_OP_VOP2__V_DOT2C_F32_F16,
&Decoder::decode_OP_VOP2__V_DOT2C_I32_I16,
&Decoder::decode_OP_VOP2__V_DOT2C_I32_I16,
&Decoder::decode_OP_VOP2__V_DOT2C_I32_I16,
&Decoder::decode_OP_VOP2__V_DOT2C_I32_I16,
&Decoder::decode_OP_VOP2__V_DOT4C_I32_I8,
&Decoder::decode_OP_VOP2__V_DOT4C_I32_I8,
&Decoder::decode_OP_VOP2__V_DOT4C_I32_I8,
&Decoder::decode_OP_VOP2__V_DOT4C_I32_I8,
&Decoder::decode_OP_VOP2__V_DOT8C_I32_I4,
&Decoder::decode_OP_VOP2__V_DOT8C_I32_I4,
&Decoder::decode_OP_VOP2__V_DOT8C_I32_I4,
&Decoder::decode_OP_VOP2__V_DOT8C_I32_I4,
&Decoder::decode_OP_VOP2__V_FMAC_F32,
&Decoder::decode_OP_VOP2__V_FMAC_F32,
&Decoder::decode_OP_VOP2__V_FMAC_F32,
&Decoder::decode_OP_VOP2__V_FMAC_F32,
&Decoder::decode_OP_VOP2__V_PK_FMAC_F16,
&Decoder::decode_OP_VOP2__V_PK_FMAC_F16,
&Decoder::decode_OP_VOP2__V_PK_FMAC_F16,
&Decoder::decode_OP_VOP2__V_PK_FMAC_F16,
&Decoder::decode_OP_VOP2__V_XNOR_B32,
&Decoder::decode_OP_VOP2__V_XNOR_B32,
&Decoder::decode_OP_VOP2__V_XNOR_B32,
&Decoder::decode_OP_VOP2__V_XNOR_B32,
&Decoder::subDecode_OP_VOPC,
&Decoder::subDecode_OP_VOPC,
&Decoder::subDecode_OP_VOPC,
@@ -4171,6 +4171,55 @@ namespace VegaISA
return new Inst_VOP2__V_SUBREV_U32(&iFmt->iFmt_VOP2);
}
GPUStaticInst*
Decoder::decode_OP_VOP2__V_DOT2C_F32_F16(MachInst iFmt)
{
fatal("Trying to decode instruction without a class\n");
return nullptr;
}
GPUStaticInst*
Decoder::decode_OP_VOP2__V_DOT2C_I32_I16(MachInst iFmt)
{
fatal("Trying to decode instruction without a class\n");
return nullptr;
}
GPUStaticInst*
Decoder::decode_OP_VOP2__V_DOT4C_I32_I8(MachInst iFmt)
{
fatal("Trying to decode instruction without a class\n");
return nullptr;
}
GPUStaticInst*
Decoder::decode_OP_VOP2__V_DOT8C_I32_I4(MachInst iFmt)
{
fatal("Trying to decode instruction without a class\n");
return nullptr;
}
GPUStaticInst*
Decoder::decode_OP_VOP2__V_FMAC_F32(MachInst iFmt)
{
fatal("Trying to decode instruction without a class\n");
return nullptr;
}
GPUStaticInst*
Decoder::decode_OP_VOP2__V_PK_FMAC_F16(MachInst iFmt)
{
fatal("Trying to decode instruction without a class\n");
return nullptr;
}
GPUStaticInst*
Decoder::decode_OP_VOP2__V_XNOR_B32(MachInst iFmt)
{
fatal("Trying to decode instruction without a class\n");
return nullptr;
}
GPUStaticInst*
Decoder::decode_OP_SOP2__S_ADD_U32(MachInst iFmt)
{

7
src/arch/amdgpu/vega/gpu_decoder.hh
View File

@@ -1358,6 +1358,13 @@ namespace VegaISA
GPUStaticInst* decode_OP_VOP2__V_ADD_U32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_SUB_U32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_SUBREV_U32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_DOT2C_F32_F16(MachInst);
GPUStaticInst* decode_OP_VOP2__V_DOT2C_I32_I16(MachInst);
GPUStaticInst* decode_OP_VOP2__V_DOT4C_I32_I8(MachInst);
GPUStaticInst* decode_OP_VOP2__V_DOT8C_I32_I4(MachInst);
GPUStaticInst* decode_OP_VOP2__V_FMAC_F32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_PK_FMAC_F16(MachInst);
GPUStaticInst* decode_OP_VOP2__V_XNOR_B32(MachInst);
GPUStaticInst* decode_OP_VOPC__V_CMP_CLASS_F32(MachInst);
GPUStaticInst* decode_OP_VOPC__V_CMPX_CLASS_F32(MachInst);
GPUStaticInst* decode_OP_VOPC__V_CMP_CLASS_F64(MachInst);