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Bobby R. Bruce d42eeb6b68 cpu: Explicitly define cache_line_size -> 64-bit unsigned int (#329) 
While it's plausible to define the cache_line_size as a 32-bit unsigned
int, the use of cache_line_size is way out of its original scope.

cache_line_size has been used to produce an address mask, which masking
out the offset bits from an address. For example, [1], [2], [3], and
[4]. However, since the cache_line_size is an "unsigned int", the type
of the value is not guaranteed to be 64-bit long. Subsequently, the bit
twiddling hacks in [1], [2], [3], and [4] produce 32-bit mask, i.e.,
0x00000000FFFFFFC0.

This behavior at least caused a problem in LLSC in RISC-V [5], where the
load reservation (LR) relies on the mask to produce the cache block
address. Two distinct 64-bit addresses can be mapped to the same cache
block using the above mask.

This patch explicitly defines cache_line_size as a 64-bit unsigned int
so the cache block mask can be produced correctly for 64-bit addresses.

[1]
3bdcfd6f7a/src/cpu/simple/atomic.hh (L147)
[2]
3bdcfd6f7a/src/cpu/simple/timing.hh (L224)
[3]
3bdcfd6f7a/src/cpu/o3/lsq_unit.cc (L241)
[4]
3bdcfd6f7a/src/cpu/minor/lsq.cc (L1425)
[5]
3bdcfd6f7a/src/arch/riscv/isa.cc (L787)
2023-10-16 07:50:35 -07:00
..
guest_abi
sim,arch: Remove the GuestABI namespace
2023-01-17 09:16:20 +00:00
power
misc,python: Run pre-commit run --all-files
2023-10-10 21:47:07 -07:00
probe
sim: Probe listener template with lambda
2023-09-25 08:51:00 +00:00
async.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
async.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
aux_vector.hh
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
backtrace_glibc.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
backtrace_none.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
backtrace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
bufval.cc
sim: Add some helpers for working with values in buffers.
2022-02-26 09:56:26 +00:00
bufval.hh
sim: Add some helpers for working with values in buffers.
2022-02-26 09:56:26 +00:00
bufval.test.cc
sim: Avoid -Werror=unused-variable in bufval unittests
2022-03-02 08:19:58 +00:00
byteswap.hh
misc: Replace type_traits.hh XX::value with XX_v.
2021-07-28 01:48:03 +00:00
byteswap.test.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
clock_domain.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
clock_domain.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
ClockDomain.py
misc: Run pre-commit run --all-files
2023-10-10 14:01:58 -07:00
clocked_object.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
clocked_object.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
ClockedObject.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
core.cc
sim: Remove a couple of deprecated namespaces
2023-01-17 09:16:20 +00:00
core.hh
sim: Remove a couple of deprecated namespaces
2023-01-17 09:16:20 +00:00
cur_tick.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
cur_tick.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
cxx_config_ini.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
cxx_config_ini.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
cxx_config.cc
scons,sim: Eliminate the generated cxx_config/init.cc file.
2022-01-13 05:21:41 +00:00
cxx_config.hh
scons,sim: Eliminate the generated cxx_config/init.cc file.
2022-01-13 05:21:41 +00:00
cxx_manager.cc
scons,sim: Eliminate the generated cxx_config/init.cc file.
2022-01-13 05:21:41 +00:00
cxx_manager.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
debug.cc
sim: allow specifying remote gdb port for each workload
2022-11-03 05:34:09 +00:00
debug.hh
sim: allow specifying remote gdb port for each workload
2022-11-03 05:34:09 +00:00
drain.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
drain.hh
misc: Run pre-commit run on all files in repo
2022-08-24 21:47:07 +00:00
dvfs_handler.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dvfs_handler.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
DVFSHandler.py
misc: Run pre-commit run --all-files
2023-10-10 14:01:58 -07:00
emul_driver.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
eventq.cc
systemc: fix -Wno-free-nonheap-object for building scheduler.cc
2023-01-13 05:58:51 +00:00
eventq.hh
sim: Deprecate pointer version of MemberEventWrapper constructor
2023-03-13 06:47:09 +00:00
faults.cc
base,sim,ext: Adding GDB signals definition
2022-11-22 10:45:30 +00:00
faults.hh
misc: Include static_inst_fwd.hh in sim/faults.hh.
2021-10-01 04:57:56 +00:00
fd_array.cc
sim:fixed some style issues
2023-09-07 08:52:24 -07:00
fd_array.hh
sim: check redirect path when unserialize for cpt
2023-09-07 08:52:24 -07:00
fd_entry.cc
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
fd_entry.hh
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
full_system.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
futex_map.cc
sim: Fix erasure ordering in the futex map.
2022-06-03 07:23:18 +00:00
futex_map.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
global_event.cc
misc: Remove sim/cur_tick dependency from sim/core.hh
2021-07-06 09:59:11 +00:00
global_event.hh
sim: Add missing virtual destructor to GlobalSyncEvent
2022-11-29 18:54:12 +00:00
globals.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
globals.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
globals.test.cc
sim,tests: Add unit test for Globals
2022-02-09 10:24:54 +00:00
guest_abi.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
guest_abi.test.cc
sim,arch: Remove the GuestABI namespace
2023-01-17 09:16:20 +00:00
init_signals.cc
base: Output link to common errors page
2023-05-26 04:42:25 +00:00
init_signals.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
init.cc
sim: Make the EmbeddedPyBind::initAll method work correctly.
2021-12-16 01:57:26 +00:00
init.hh
sim: Make the EmbeddedPyBind::initAll method work correctly.
2021-12-16 01:57:26 +00:00
insttracer.hh
misc: Replace namespace Trace with lowercase trace
2022-10-02 16:30:15 +00:00
InstTracer.py
misc: Replace namespace Trace with lowercase trace
2022-10-02 16:30:15 +00:00
kernel_workload.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
kernel_workload.hh
arch,sim: Add a byteOrder accessor to the Workload class.
2021-11-18 07:09:00 +00:00
linear_solver.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
linear_solver.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
main.cc
sim,python: follow the new CPython startup sequence
2023-07-10 23:00:31 +00:00
mathexpr.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mathexpr.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mem_pool.cc
sim: Fix Mempool overrides during checkpoint
2022-03-29 07:13:44 +00:00
mem_pool.hh
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
mem_state.cc
sim-se: unmap reclaimed heap pages in brk syscall emulation
2023-10-06 20:39:57 +00:00
mem_state.hh
sim-se: unmap reclaimed heap pages in brk syscall emulation
2023-10-06 20:39:57 +00:00
port.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
port.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
port.test.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
power_domain.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
power_domain.hh
sim: Switch from EventWrapper to MemberEventWrapper before deprec
2023-03-13 06:47:09 +00:00
power_state.cc
misc: Remove sim/cur_tick dependency from sim/core.hh
2021-07-06 09:59:11 +00:00
power_state.hh
misc: Remove sim/cur_tick dependency from sim/core.hh
2021-07-06 09:59:11 +00:00
PowerDomain.py
misc: Run pre-commit run --all-files
2023-10-10 14:01:58 -07:00
PowerState.py
misc: Run pre-commit run --all-files
2023-10-10 14:01:58 -07:00
process_impl.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
process.cc
sim: check redirect path when unserialize for cpt
2023-09-07 08:52:24 -07:00
process.hh
base: Remove the Loader namespace
2023-01-17 09:16:20 +00:00
Process.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
proxy_ptr.hh
sim,arch: Remove the GuestABI namespace
2023-01-17 09:16:20 +00:00
proxy_ptr.test.cc
sim,arch: Remove the GuestABI namespace
2023-01-17 09:16:20 +00:00
pseudo_inst.cc
sim: Remove a couple of deprecated namespaces
2023-01-17 09:16:20 +00:00
pseudo_inst.hh
sim: Remove a couple of deprecated namespaces
2023-01-17 09:16:20 +00:00
py_interact.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
py_interact.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
python.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
redirect_path.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
redirect_path.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
RedirectPath.py
misc: Run pre-commit run on all files in repo
2022-08-24 21:47:07 +00:00
root.cc
sim: Don't serialize a root.isa string in checkpoints.
2021-07-31 18:06:52 +00:00
root.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
Root.py
misc: Run pre-commit run --all-files
2023-10-10 14:01:58 -07:00
SConscript
sim: Add some helpers for setting up Signal*Ports in python.
2023-02-02 01:01:56 +00:00
SConsopts
scons: fix systrace header test
2022-10-18 12:11:25 +00:00
se_signal.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
se_signal.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
se_workload.cc
sim: Fix Mempool overrides during checkpoint
2022-03-29 07:13:44 +00:00
se_workload.hh
sim: Fix Mempool overrides during checkpoint
2022-03-29 07:13:44 +00:00
serialize_handlers.hh
misc: Replace type_traits.hh XX::value with XX_v.
2021-07-28 01:48:03 +00:00
serialize_handlers.test.cc
sim: Fix serialize_handlers.test.cc on Arm platforms
2022-09-13 08:46:56 +00:00
serialize.cc
base: Unit tests miscellaneous patches (#73)
2023-07-19 08:45:29 -07:00
serialize.hh
sim: Explicitly specify the namespace of serialization helpers.
2021-08-28 04:18:12 +00:00
serialize.test.cc
sim,tests: Add unit test for sim/serialize.hh
2021-09-22 05:31:01 +00:00
signal.hh
sim: add bypass_on_change to the set() of a signal
2023-09-07 11:54:56 +08:00
SignalPort.py
sim: Add some helpers for setting up Signal*Ports in python.
2023-02-02 01:01:56 +00:00
sim_events.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
sim_events.hh
base,sim: Adding monitor function to GDB
2022-11-22 16:02:53 +00:00
sim_exit.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
sim_object.cc
sim: Remove unused SimObject::debugObjectBreak
2023-03-21 06:53:55 +00:00
sim_object.hh
sim: Remove unused SimObject::debugObjectBreak
2023-03-21 06:53:55 +00:00
simulate.cc
sim: handle async events in main thread only
2023-02-08 00:28:02 +00:00
simulate.hh
python: Remove 'scheduleTickExit' in favor of 'exitSimLoop'
2022-12-06 18:04:46 +00:00
stat_control.cc
base: Remove the Stats namespace
2023-01-17 09:16:20 +00:00
stat_control.hh
base: Remove the Stats namespace
2023-01-17 09:16:20 +00:00
stat_register.cc
base: Remove the Stats namespace
2023-01-17 09:16:20 +00:00
stat_register.hh
base: Remove the Stats namespace
2023-01-17 09:16:20 +00:00
stats.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
stats.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
sub_system.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
sub_system.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
SubSystem.py
misc: Run pre-commit run --all-files
2023-10-10 14:01:58 -07:00
syscall_abi.hh
sim,arch: Remove the GuestABI namespace
2023-01-17 09:16:20 +00:00
syscall_debug_macros.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
syscall_desc.cc
sim-se: (Re)add support for retrying system calls.
2021-12-17 05:45:26 +00:00
syscall_desc.hh
sim-se: (Re)add support for retrying system calls.
2021-12-17 05:45:26 +00:00
syscall_emul_buf.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
syscall_emul.cc
sim-se: Fix crash in chdirFunc() on nonexistent directory
2023-09-07 03:18:58 +00:00
syscall_emul.hh
sim-se: Use tgt_stat64 instead of tgt_stat in newfstatatFunc (#283)
2023-09-12 08:33:42 -07:00
syscall_return.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
system.cc
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
system.hh
mem,sim: Change the type of cache_line_size to Addr
2023-09-20 14:00:45 -07:00
System.py
python: Fix multiline quotes in a single line
2022-11-29 23:44:38 +00:00
ticked_object.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
ticked_object.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
TickedObject.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
vma.cc
sim,sim-se: Fix restoring of VMAs of memory-mapped files
2022-12-15 21:38:01 +00:00
vma.hh
sim,sim-se: Fix restoring of VMAs of memory-mapped files
2022-12-15 21:38:01 +00:00
voltage_domain.cc
mem,sim: Replace the deprecated chatty_assert with gem5_assert.
2021-08-21 00:54:54 +00:00
voltage_domain.hh
mem,sim: Replace the deprecated chatty_assert with gem5_assert.
2021-08-21 00:54:54 +00:00
VoltageDomain.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
workload.cc
base,cpu,dev,sim: Pull common logic into ListenSocket::listen().
2023-03-29 03:05:06 +00:00
workload.hh
base,sim,ext: Adding GDB signals definition
2022-11-22 10:45:30 +00:00
Workload.py
arch,base,dev,sim: Convert objects to use the HostSocket param type.
2023-04-12 02:18:22 +00:00