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ca07a068936fd1fd840c3fa2c330f7e3dc8ca2aa
gem5/src/sim
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handsomeliu-google 956b164a43 Add Python interface to get port actual name (#1744) 
In our usecase, we'd like to intercept some gadgets in some gem5 ports,
and register them to a Python-level collection. The registered name is
the string from C++ constructor argument (portName), and it would be
great if we can access that from Python-level as well. This commit
enable this by exporting a py-binded method to access the portName.

Change-Id: I93398697536f27a52d3a1dd0e658fcb321b9e293
2024-11-02 08:59:50 -05:00
..
guest_abi
sim: adding constructor to GuestAddr
2024-04-01 18:05:56 +00:00
power
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
probe
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
async.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
async.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
aux_vector.hh
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
backtrace_glibc.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
backtrace_none.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
backtrace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
bufval.cc
sim: Add some helpers for working with values in buffers.
2022-02-26 09:56:26 +00:00
bufval.hh
sim: Add some helpers for working with values in buffers.
2022-02-26 09:56:26 +00:00
bufval.test.cc
sim: Avoid -Werror=unused-variable in bufval unittests
2022-03-02 08:19:58 +00:00
byteswap.hh
misc: Replace type_traits.hh XX::value with XX_v.
2021-07-28 01:48:03 +00:00
byteswap.test.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
clock_domain.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
clock_domain.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
ClockDomain.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
clocked_object.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
clocked_object.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
ClockedObject.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
core.cc
sim: Remove a couple of deprecated namespaces
2023-01-17 09:16:20 +00:00
core.hh
sim: Remove a couple of deprecated namespaces
2023-01-17 09:16:20 +00:00
cur_tick.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
cur_tick.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
cxx_config_ini.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
cxx_config_ini.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
cxx_config.cc
scons,sim: Eliminate the generated cxx_config/init.cc file.
2022-01-13 05:21:41 +00:00
cxx_config.hh
scons,sim: Eliminate the generated cxx_config/init.cc file.
2022-01-13 05:21:41 +00:00
cxx_manager.cc
scons,sim: Eliminate the generated cxx_config/init.cc file.
2022-01-13 05:21:41 +00:00
cxx_manager.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
debug.cc
sim: allow specifying remote gdb port for each workload
2022-11-03 05:34:09 +00:00
debug.hh
sim: allow specifying remote gdb port for each workload
2022-11-03 05:34:09 +00:00
drain.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
drain.hh
misc: Run pre-commit run on all files in repo
2022-08-24 21:47:07 +00:00
dvfs_handler.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dvfs_handler.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
DVFSHandler.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
emul_driver.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
eventq.cc
systemc: fix -Wno-free-nonheap-object for building scheduler.cc
2023-01-13 05:58:51 +00:00
eventq.hh
sim: Deprecate pointer version of MemberEventWrapper constructor
2023-03-13 06:47:09 +00:00
faults.cc
base,sim,ext: Adding GDB signals definition
2022-11-22 10:45:30 +00:00
faults.hh
misc: Include static_inst_fwd.hh in sim/faults.hh.
2021-10-01 04:57:56 +00:00
fd_array.cc
sim:fixed some style issues
2023-09-07 08:52:24 -07:00
fd_array.hh
sim: check redirect path when unserialize for cpt
2023-09-07 08:52:24 -07:00
fd_entry.cc
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
fd_entry.hh
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
full_system.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
futex_map.cc
sim: Fix erasure ordering in the futex map.
2022-06-03 07:23:18 +00:00
futex_map.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
global_event.cc
misc: Remove sim/cur_tick dependency from sim/core.hh
2021-07-06 09:59:11 +00:00
global_event.hh
sim: Add missing virtual destructor to GlobalSyncEvent
2022-11-29 18:54:12 +00:00
globals.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
globals.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
globals.test.cc
sim,tests: Add unit test for Globals
2022-02-09 10:24:54 +00:00
guest_abi.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
guest_abi.test.cc
sim,arch: Remove the GuestABI namespace
2023-01-17 09:16:20 +00:00
init_signals.cc
sim,python: Restore sigint handler in python (#531)
2023-11-30 07:27:52 -08:00
init_signals.hh
sim,python: Restore sigint handler in python (#531)
2023-11-30 07:27:52 -08:00
init.cc
sim: Make the EmbeddedPyBind::initAll method work correctly.
2021-12-16 01:57:26 +00:00
init.hh
sim: Make the EmbeddedPyBind::initAll method work correctly.
2021-12-16 01:57:26 +00:00
insttracer.hh
arch,cpu,sim: Add mechanism to partially print vector regs (#1234)
2024-06-17 14:05:47 -07:00
InstTracer.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
kernel_workload.cc
sim: Add error message for kernel exceeding memory size (#1329)
2024-07-30 19:39:41 -07:00
kernel_workload.hh
arch,sim: Add a byteOrder accessor to the Workload class.
2021-11-18 07:09:00 +00:00
linear_solver.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
linear_solver.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
main.cc
sim,python: follow the new CPython startup sequence
2023-07-10 23:00:31 +00:00
mathexpr.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mathexpr.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mem_pool.cc
sim: Fix Mempool overrides during checkpoint
2022-03-29 07:13:44 +00:00
mem_pool.hh
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
mem_state.cc
sim-se: unmap reclaimed heap pages in brk syscall emulation
2023-10-06 20:39:57 +00:00
mem_state.hh
sim-se: unmap reclaimed heap pages in brk syscall emulation
2023-10-06 20:39:57 +00:00
port.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
port.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
port.test.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
power_domain.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
power_domain.hh
sim: Switch from EventWrapper to MemberEventWrapper before deprec
2023-03-13 06:47:09 +00:00
power_state.cc
misc: Remove sim/cur_tick dependency from sim/core.hh
2021-07-06 09:59:11 +00:00
power_state.hh
misc: Remove sim/cur_tick dependency from sim/core.hh
2021-07-06 09:59:11 +00:00
PowerDomain.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
PowerState.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
process_impl.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
process.cc
sim: Updating Process::Map (#835)
2024-02-05 12:17:05 -08:00
process.hh
sim: Updating Process::Map (#835)
2024-02-05 12:17:05 -08:00
Process.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
proxy_ptr.hh
sim,arch: Remove the GuestABI namespace
2023-01-17 09:16:20 +00:00
proxy_ptr.test.cc
sim,arch: Remove the GuestABI namespace
2023-01-17 09:16:20 +00:00
pseudo_inst.cc
sim: enable pseudo instructions with varying pointer size
2024-03-11 15:27:58 +00:00
pseudo_inst.hh
sim: adding constructor to GuestAddr
2024-04-01 18:05:56 +00:00
py_interact.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
py_interact.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
python.cc
Add Python interface to get port actual name (#1744)
2024-11-02 08:59:50 -05:00
redirect_path.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
redirect_path.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
RedirectPath.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
root.cc
sim: Don't serialize a root.isa string in checkpoints.
2021-07-31 18:06:52 +00:00
root.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
Root.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
SConscript
sim: Rework the Linux Kernel exit events (#639)
2023-12-01 17:33:59 -08:00
SConsopts
scons: fix systrace header test
2022-10-18 12:11:25 +00:00
se_signal.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
se_signal.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
se_workload.cc
sim: Fix Mempool overrides during checkpoint
2022-03-29 07:13:44 +00:00
se_workload.hh
sim: Fix Mempool overrides during checkpoint
2022-03-29 07:13:44 +00:00
serialize_handlers.hh
misc: Replace type_traits.hh XX::value with XX_v.
2021-07-28 01:48:03 +00:00
serialize_handlers.test.cc
sim: Fix serialize_handlers.test.cc on Arm platforms
2022-09-13 08:46:56 +00:00
serialize.cc
base: Unit tests miscellaneous patches (#73)
2023-07-19 08:45:29 -07:00
serialize.hh
sim: Explicitly specify the namespace of serialization helpers.
2021-08-28 04:18:12 +00:00
serialize.test.cc
sim,tests: Add unit test for sim/serialize.hh
2021-09-22 05:31:01 +00:00
signal.hh
sim: Make SignalSinkPort::set virtual (#1679)
2024-10-18 05:41:05 -07:00
SignalPort.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
sim_events.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
sim_events.hh
base,sim: Adding monitor function to GDB
2022-11-22 16:02:53 +00:00
sim_exit.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
sim_object.cc
sim: Remove unused SimObject::debugObjectBreak
2023-03-21 06:53:55 +00:00
sim_object.hh
sim: Remove unused SimObject::debugObjectBreak
2023-03-21 06:53:55 +00:00
simulate.cc
sim,python: Restore sigint handler in python (#531)
2023-11-30 07:27:52 -08:00
simulate.hh
sim: Add include guards in simulate.hh (#1737)
2024-10-31 00:34:39 -07:00
stat_control.cc
base: Remove the Stats namespace
2023-01-17 09:16:20 +00:00
stat_control.hh
base: Remove the Stats namespace
2023-01-17 09:16:20 +00:00
stat_register.cc
base: Remove the Stats namespace
2023-01-17 09:16:20 +00:00
stat_register.hh
base: Remove the Stats namespace
2023-01-17 09:16:20 +00:00
stats.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
stats.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
sub_system.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
sub_system.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
SubSystem.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
syscall_abi.hh
sim: adding constructor to GuestAddr
2024-04-01 18:05:56 +00:00
syscall_debug_macros.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
syscall_desc.cc
sim-se: (Re)add support for retrying system calls.
2021-12-17 05:45:26 +00:00
syscall_desc.hh
sim-se: (Re)add support for retrying system calls.
2021-12-17 05:45:26 +00:00
syscall_emul_buf.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
syscall_emul.cc
arch-arm, sim-se: Fix VPtr bug
2024-08-20 16:18:24 +01:00
syscall_emul.hh
arch-arm, sim-se: Fix VPtr bug
2024-08-20 16:18:24 +01:00
syscall_return.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
system.cc
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
system.hh
mem,sim: Change the type of cache_line_size to Addr
2023-09-20 14:00:45 -07:00
System.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
ticked_object.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
ticked_object.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
TickedObject.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
vma.cc
sim,sim-se: Fix restoring of VMAs of memory-mapped files
2022-12-15 21:38:01 +00:00
vma.hh
sim,sim-se: Fix restoring of VMAs of memory-mapped files
2022-12-15 21:38:01 +00:00
voltage_domain.cc
mem,sim: Replace the deprecated chatty_assert with gem5_assert.
2021-08-21 00:54:54 +00:00
voltage_domain.hh
mem,sim: Replace the deprecated chatty_assert with gem5_assert.
2021-08-21 00:54:54 +00:00
VoltageDomain.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
workload.cc
base,cpu,dev,sim: Pull common logic into ListenSocket::listen().
2023-03-29 03:05:06 +00:00
workload.hh
arch-riscv: Add support for RISC-V semihosting (#681)
2024-04-27 05:12:32 -07:00
Workload.py
sim-se: Catch None value if binary is not compatible with gem5 (#903)
2024-03-01 16:41:18 -08:00