Yu-Cheng Chang 70c211236a arch-riscv: sign-extend the PC when enter/leave trap handler (#1756) ...

The PR https://github.com/gem5/gem5/pull/1316 changes the sign-extend
address generation. We also need to sign-extend the address when setting
the PC in enter/leave trap handler

Change-Id: I62d58a26dba0b0c64125fea8ac9376ebf55c4952

2024-11-05 12:14:55 -08:00

..

arch

arch-riscv: sign-extend the PC when enter/leave trap handler (#1756)

2024-11-05 12:14:55 -08:00

base

base: Make BaseGdbRegCache::data() non constant (#1734)

2024-11-05 10:43:41 -08:00

cpu

Implement BTB using the cache library (#1537)

2024-10-10 17:05:22 +01:00

dev

dev-amdgpu, gpu-compute, mem-ruby: Add support for writeback L2 in GPU (#1692)

2024-11-05 10:45:46 -08:00

doc

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doxygen

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gpu-compute

dev-amdgpu, gpu-compute, mem-ruby: Add support for writeback L2 in GPU (#1692)

2024-11-05 10:45:46 -08:00

kern

arch, sim-se: Fix off_t size mismatch bug

2024-08-20 16:18:24 +01:00

learning_gem5

configs, dev, learning-gem5, python, tests: more clarification

2024-08-23 18:02:42 -07:00

mem

dev-amdgpu, gpu-compute, mem-ruby: Add support for writeback L2 in GPU (#1692)

2024-11-05 10:45:46 -08:00

proto

scons: Use Kconfig to configure gem5.

2023-11-23 08:26:10 +08:00

python

stdlib: address requested changes to X86, Riscv boards

2024-10-28 15:00:19 -07:00

sim

Add Python interface to get port actual name (#1744)

2024-11-02 08:59:50 -05:00

sst

mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner

2023-02-03 06:11:45 +00:00

systemc

systemc: Disable 'overloaded-virtual' warn for clang (#1662)

2024-10-18 05:40:10 -07:00

test_objects

stdlib: Add SparseHist to PyStats

2024-05-23 14:54:59 -07:00

Doxyfile

misc: Update versioning for develop branch

2024-06-27 23:36:07 -07:00

Kconfig

scons,tests: Add 'USE_TEST_OBJECTS' kconfig

2024-04-04 13:04:21 -07:00

SConscript

python: Add importer to standalone gem5py_m5

2023-09-28 11:22:33 -07:00