Commit Graph

1443 Commits

Author SHA1 Message Date
handsomeliu-google
956b164a43 Add Python interface to get port actual name (#1744)
In our usecase, we'd like to intercept some gadgets in some gem5 ports,
and register them to a Python-level collection. The registered name is
the string from C++ constructor argument (portName), and it would be
great if we can access that from Python-level as well. This commit
enable this by exporting a py-binded method to access the portName.

Change-Id: I93398697536f27a52d3a1dd0e658fcb321b9e293
2024-11-02 08:59:50 -05:00
Bobby R. Bruce
b5a73b59ef sim: Add include guards in simulate.hh (#1737) 2024-10-31 00:34:39 -07:00
handsomeliu-google
3fc6cc7763 sim: Make SignalSinkPort::set virtual (#1679)
We are implementing derived classes of SignalSinkPort that does some
additional logic after it's triggered (set() invoked by SignalSourcePort
peer), and before executing the callback that a device provides (in
onChange_). The logic is like additional logging, or providing debugging
features. However, set() itself directly calls the onChange_ callback.

Making the set() virtual could provide the flexibility to achieve this
feature.
2024-10-18 05:41:05 -07:00
Tiberiu Bucur
88de81f167 arch-arm, sim-se: Fix VPtr bug
Some syscalls were incorrectly using 64 bit
integers instead of VPtr's guest pointers,
causing parameter value corruption. This
commit addresses this issue.

Change-Id: If9e27a7c776b802dda18979d1a83a76c23557359
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2024-08-20 16:18:24 +01:00
Tiberiu Bucur
107e8f3d17 arch, sim-se: Fix size_t size mismatch bug
Same as with the off_t, some syscalls were using
incorrect size parametres in place of a guest-defined
size_t. This commit changes the signature of said
syscalls and adds the size_t typedef to the
arch-dependent Linux OSs.

Change-Id: Iece43814971a8e6275d25f6789e41528d241d1f4
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2024-08-20 16:18:24 +01:00
Tiberiu Bucur
f74260c552 arch, sim-se: Fix off_t size mismatch bug
Some system calls were using incorrect sizing for
offset parametres, which was causing the ABI to pass
wrong values due to size mismatches. One such syscall
is lseek, which in the Arm syscall table was
incorrectly marked as llseek, which does not exist
in aarch64 Linux. In addition, the off_t alias for
general Linux was changed from an unsigned to a
signed type, to accurately reflect the behaviour
in the real-life Linux operating system.

Change-Id: Iada4b66a8933466c162ba9ec901dbdae73c73a18
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2024-08-20 16:18:24 +01:00
Erin (Jianghua) Le
2bfafa726f sim: Add error message for kernel exceeding memory size (#1329)
This commit adds an error message to src/sim/kernel_workload.cc to tell
the user when the end address of the kernel is greater than the size of
memory. The error message also specifies the minimum memory size needed
to fit the kernel.

Change-Id: I7d8f50889ed8172f64b84f98301a35e5f2f352d3
2024-07-30 19:39:41 -07:00
Hoa Nguyen
15e0236a8b arch,cpu,sim: Add mechanism to partially print vector regs (#1234)
Currently, gem5's inst tracer prints the whole vector register container
by default. The size of vector register containers in gem5 is the
maximum size allowed by the ISA. For vector-length agnostic (VLA) vector
registers, this means ARM SVE vector container is 2048 bits long, and
RISC-V vector container is 65535 bits long. Note that VLA implementation
in gem5 allows the vector length to be varied within the limit specified
by the ISAs.

However, in most use cases of gem5, the vector length is much less than
65535 bits. This causes two issues: (1) the vector container requires
allocating and moving around a large amount of unused data while only a
fraction of it is used, and (2) printing the execution trace of a vector
register results in a wall of text with a small amount of useful data.

This change addresses the problem (2) by providing a mechanism to limit
the amount data printed by the instruction tracer. This is done by
adding a function printing the first X bits of a vector register
container, where X is the vector length determined at runtime, as
opposed to the vector container size, which is determined at compilation
time.

Change-Id: I815fa5aa738373510afcfb0d544a5b19c40dc0c7

---------

Signed-off-by: Hoa Nguyen <hn@hnpl.org>
2024-06-17 14:05:47 -07:00
Alexander Richardson
1bb5d3b99e arch-riscv: Add support for RISC-V semihosting (#681)
See https://github.com/riscv-software-src/riscv-semihosting for the
current specification. Almost all code is shared with the Arm
implementation.

Tested by running some binaries built with
[picolibc](https://github.com/picolibc/picolibc).
2024-04-27 05:12:32 -07:00
Ivana Mitrovic
a8d778516d arch-riscv,sim: m5ops argument / return fix for 32 bit RISC-V (#900)
M5Ops C / C++ functions partially use 64 bit arguments and return value.
In general, 64 bit arguments and return values are possible for 32 bit
RISC-V systems as well, since the arguments and the return value is
split into two registers. However, at the moment, this does not work for
32 bit RISC-V systems on the simulator side, since there is a one to one
mapping between argument registers and m5op function parameters.

To solve this problem, the get() function of the RISC-V reg_abi is
updated. It now will merge two registers if there is a 64 bit argument.
For this, the function code has to be passed to the get() function. The
default value of this function code is set to 0xF00, since 0x00 is
already used for M5_ARM. The parameter list of other get() functions for
argument return is also extended by this function code parameter with
the keyword [[maybe_unused]].

To enable a return value of size 64 bit, a0 is assigned with the lower
32 bit and a1 with the higher 32 bit.

Related Issue: https://github.com/gem5/gem5/issues/881
2024-04-08 10:09:17 -07:00
Nicholas Mosier
32ee09df4a sim-se: Fix copyOutStatxBuf compile error (#989)
Fix #988. Rewrite statxFunc and copyOutStatxBuf to use platform-agnostic
stat system call, not Linux-specific statx system call.

Change-Id: I3d17e14684e9cd77cdbfd0141b93c3bcbd27dbeb
2024-04-02 14:59:24 -07:00
Robert Hauser
f9a9e50007 sim: adding constructor to GuestAddr
A constructor is added to GuestAddr as suggested in the pull request
feedback. This allows a cast conversion from uint64_t GuestAddr. Hence,
the casting from uint64_t to GuestAddr by reinterpret_cast is removed
(was added in a previous commit).

using namespace pseudo_inst is also removed as requested.

Comments are added to GuestAddr.

Change-Id: Ib76de2bff285f4e53ad03361969c27f7bb2dfe9e
2024-04-01 18:05:56 +00:00
Nicholas Mosier
00d4b6825c sim-se: Implement statx system call for Linux x86-64 (#887)
Implement the statx Linux-specific system call for x86-64. statx is used
by LLVM's libc.

Change-Id: Ic000a36a5e5c1399996f520fa357b9354c73c864
2024-04-01 08:23:39 -07:00
Robert Hauser
0fc08acf92 sim: add whitespace for correct coding style
This commit adds two additional whitespaces in the definition of
GuestAddr as well as in the operator << overload.

Change-Id: Ifb371a09b378fcf4862a768f113b5963b45bd167
2024-03-16 09:07:38 +00:00
Robert Hauser
de52f3614c sim: enable pseudo instructions with varying pointer size
In this patch, Addr is subtituted by a struct wrapper (uint64_t) in the
pseudo instruction functions. This enables a correct argument handling
in systems where pointer size != 64 bit.

Change-Id: Ie84b43b4ab8e6c0d38c7b6b16e19fc043110681b
2024-03-11 15:27:58 +00:00
Ivana Mitrovic
fae5f5e00b sim-se: Catch None value if binary is not compatible with gem5 (#903)
Adding an error message in case the binary is not compatible with gem5.

This PR is addressing the comments in issue #807.

Change-Id: I66466ed6f657276c13d237fde3b1ec12c20cfe91
2024-03-01 16:41:18 -08:00
Mahyar Samani
8efe6dc1bc sim: Updating Process::Map (#835)
Changing size from int to int64_t to allow for mapping regions bigger
than 2GB.
2024-02-05 12:17:05 -08:00
Tiberiu Bucur
9b0bf33f79 sim: Remove trailing / from proc/meminfo special path (#689)
Note: A bug was identified in that the one of the special file paths,
namely /proc/meminfo contained an extra trailing /, implicitly making
the incorrect assumption that meminfo was a directory, when it is, in
fact, a (pseudo-)file. This was causing application in SE mode to fail
opening the meminfo pseudo-file with errno 13. This commit fixes this
issue.

Change-Id: I93fa81cab49645d70775088f1e634f067b300698
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
2023-12-17 22:07:39 -08:00
Bobby R. Bruce
21919addca Fix for gem5 Issue #550 (#636)
This Pull-Request addresses gem5 Issue #550. The code that dumps the
Dmesg buffer is now templated on the two variants of the `Metadata`
structure, and the correct one is chosen based on the detected Kernel
version.

To support this functionality, the pull request also adds Symbol Size
data to the loader Symbol Table, and adds a method to query the Kernel
Version from the image in guest memory. The new attributes in the Symbol
class are de-serialized speculatively, so no checkpoint upgrader is
required to support this change.
2023-12-01 18:06:20 -08:00
Richard Cooper
d9c870f641 sim: Rework the Linux Kernel exit events (#639)
This patch reworks the Linux Kernel panic and oops events. The code has
been re-factored to provide re-usable events that can be applied to all
ISAs from the base `KernelWorkload` `SimObject`. At the moment they are
installed for the Arm workloads.

This update also provides more configuration options that can be
specified using the new `KernelPanicOopsBehaviour` enum. The options are
applied to the Kernel Workload parameters `on_panic` and `on_oops` which
are available to all subclasses of `KernelWorkload`.

The main rationale for this reworking is to add the option to cleanly
exit the simulation after dumping the Dmesg buffer. Without this option,
the simulation would continue running after a Kernel panic. If system
components (e.g. a system timer) keep the event queue alive, this causes
the simulation to run slowly to the maximum allowed tick.
2023-12-01 17:33:59 -08:00
Richard Cooper
2fbbdad618 base: Add encapsulation to the loader::Symbol class
This commit converts `gem5::loader::Symbol` to a full class with
private members, enforcing encapsulation. Until now client code has
been able to (and does) access members directly.

This change will enable class invariants to be enforced via accessor
methods.

Change-Id: Ia0b5b080d4f656637a211808e13dce1ddca74541
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2023-12-01 22:00:26 +00:00
Jason Lowe-Power
9afe9932bc sim,python: Restore sigint handler in python (#531)
Currently, if you try to use ctrl-c while python code is running nothing
happens. This is not ideal. This change enables users to use ctrl-c
while python is running (e.g., when a large disk image is downloading).
To do this, we moved the `initSignals` function in gem5 from `main` to
the simulate loop. Thus, every time the simulate loop starts (i.e., is
called from python) gem5 will install its signal handlers. Also, when
the control is returned to python, we put python's default SIGINT
handler back.

Change-Id: I14490e48d931eb316e8c641217bf8d8ddaa340ed
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2023-11-30 07:27:52 -08:00
Bobby R. Bruce
d11c40dcac misc: Run pre-commit run --all-files
This ensures `isort` is applied to all files in the repo.

Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9
2023-11-29 22:06:41 -08:00
Hoa Nguyen
697cab0544 base,sim: Add the SymbolType field to the Symbol object
Symbol type is part of the info provided by an ELF object's symtab.
It indicates whether a symbol is a file symbol, or a function symbol, etc.

Change-Id: I827e79f8439c47ac9e889734aaf354c653aff530
Signed-off-by: Hoa Nguyen <hn@hnpl.org>
2023-10-30 21:35:01 +00:00
Giacomo Travaglini
2d85707a75 sim: Define an InstructionDisassembler SimObject
We want to be able to configure from python the disassembler
used by an instruction tracer. The default/base version will
reuse existing instruction logic and it will simply
call the StaticInst::disassemble method.

Change-Id: Ieb16f059a436757c5892dcc82882f6d42090927f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2023-10-20 09:27:50 +01:00
Bobby R. Bruce
d42eeb6b68 cpu: Explicitly define cache_line_size -> 64-bit unsigned int (#329)
While it's plausible to define the cache_line_size as a 32-bit unsigned
int, the use of cache_line_size is way out of its original scope.

cache_line_size has been used to produce an address mask, which masking
out the offset bits from an address. For example, [1], [2], [3], and
[4]. However, since the cache_line_size is an "unsigned int", the type
of the value is not guaranteed to be 64-bit long. Subsequently, the bit
twiddling hacks in [1], [2], [3], and [4] produce 32-bit mask, i.e.,
0x00000000FFFFFFC0.

This behavior at least caused a problem in LLSC in RISC-V [5], where the
load reservation (LR) relies on the mask to produce the cache block
address. Two distinct 64-bit addresses can be mapped to the same cache
block using the above mask.

This patch explicitly defines cache_line_size as a 64-bit unsigned int
so the cache block mask can be produced correctly for 64-bit addresses.

[1]
3bdcfd6f7a/src/cpu/simple/atomic.hh (L147)
[2]
3bdcfd6f7a/src/cpu/simple/timing.hh (L224)
[3]
3bdcfd6f7a/src/cpu/o3/lsq_unit.cc (L241)
[4]
3bdcfd6f7a/src/cpu/minor/lsq.cc (L1425)
[5]
3bdcfd6f7a/src/arch/riscv/isa.cc (L787)
2023-10-16 07:50:35 -07:00
Bobby R. Bruce
298119e402 misc,python: Run pre-commit run --all-files
Applies the `pyupgrade` hook to all files in the repo.

Change-Id: I9879c634a65c5fcaa9567c63bc5977ff97d5d3bf
2023-10-10 21:47:07 -07:00
Bobby R. Bruce
ddf6cb88e4 misc: Run pre-commit run --all-files
This is reflect the updates made to black when running `pre-commit
autoupdate`.

Change-Id: Ifb7fea117f354c7f02f26926a5afdf7d67bc5919
2023-10-10 14:01:58 -07:00
Giacomo Travaglini
5cd70bf9bf sim-se: zero out memory allocated via brk() (#343)
The syscall emulation of brk() incorrectly did not ensure that newly
allocated memory was zero-initialized, which Linux guarantees and which
seems to be the expectation of glibc's malloc() and free()
implementation. This patch fixes the incorrect behavior by zero-
initalizing all memory allocations via brk().

GitHub issue: https://github.com/gem5/gem5/issues/342

Change-Id: I53cf29d6f3f83285c8e813e18c06c2e9a69d7cc2
2023-10-09 13:48:53 +01:00
Nicholas Mosier
0dcf0fb829 sim-se: unmap reclaimed heap pages in brk syscall emulation
gem5::MemState::updateBrkRegion(), which is called during the syscall
emulation of brk, did not unmap deallocated heap pages when the brk
region is receding. Instead, it kept it mapped for simplicity. This
introduced a bug where subequent expansions of the brk region reused
prior heap page mappings that were not zero-filled. This violates
the assumptions of glibc malloc, resulting in heap corruption and
crashes.

This patch fixes the bug by always unmapping pages that are deallocated
during a call to brk() that reduces the heap size. This makes the
gem5::MemState::_endBrkPoint field obsolete, so this patch removes it.

GitHub issue: https://github.com/gem5/gem5/issues/342

Change-Id: Ib2244e1aa4d2a26666ad60d231fdde2c22d2df35
2023-10-06 20:39:57 +00:00
David Schall
7cb308db90 sim: Probe listener template with lambda
Adds a new probe listener template which can be used
to instantiate with a lambda function that is called by
notify(). It is similar to ProbeListenerArg with class but
provides more flexibility. I.e. the can be another object
than the one instantiating the lambda which allows to listen
to any object. Furthermore additional parameters can be
passed in easily.

Change-Id: Iba451357182caf25097b9ae201cd5c647aff3a4f
Signed-off-by: David Schall <david.schall@ed.ac.uk>
2023-09-25 08:51:00 +00:00
Hoa Nguyen
ac5280fedc mem,sim: Change the type of cache_line_size to Addr
Change-Id: Id39e8249fef89c0d59bb39f8104650257ff00245
Signed-off-by: Hoa Nguyen <hn@hnpl.org>
2023-09-20 14:00:45 -07:00
Bobby R. Bruce
1bebf6a3cc sim-se: Use tgt_stat64 instead of tgt_stat in newfstatatFunc (#283)
The syscall emulation of newfstatat incorrectly treated the output stat
buffer to be of type `OS::tgt_stat`, not `OS::tgt_stat64`, causing the
invalid output stat buffer in the application to hold invalid data.

This patch fixes the bug by simply substituting the type `OS::tgt_stat`
with `OS::tgt_stat64` in `newstatatFunc()`.

GitHub issue: https://github.com/gem5/gem5/issues/281
2023-09-12 08:33:42 -07:00
Nicholas Mosier
8740385f9e sim-se: Fix tgkill logic bug in handling signal argument
The syscall emulation of tgkill contained a simple logic bug
(a `||` instead of a `&&`), causing the signal argument to always
be considered invalid. This patch fixes the bug by simply changing
the `||` to a `&&`.

GitHub issue: https://github.com/gem5/gem5/issues/284

Change-Id: I3b02c618c369ef56d32a0b04e0b13eacc9fb4977
2023-09-09 08:51:41 -07:00
Jason Lowe-Power
ebde1133c0 redirect_path patch for restoring cpt (#221)
Modify the FDArray::unserialize function to perform a checkPathRedirect
if a Process pointer is passed in.
Currently when restoring a checkpoint, it doesn't perform
checkPathRedirect for files that were opened during checkpointing. This
patch adds a checkPathRedirect in the FDArray::unserialize to redirect
app path for restoring checkpoints.
2023-09-08 15:30:53 -07:00
Nicholas Mosier
259a5d6272 sim-se: Use tgt_stat64 instead of tgt_stat in newfstatatFunc
The syscall emulation of newfstatat incorrectly treated the output
stat buffer to be of type `OS::tgt_stat`, not `OS::tgt_stat64`, causing
the invalid output stat buffer in the application to hold invalid
data.

This patch fixes the bug by simply substituting the type `OS::tgt_stat`
with `OS::tgt_stat64` in `newstatatFunc()`.

GitHub issue: https://github.com/gem5/gem5/issues/281

Change-Id: Ice97c1fc4cccbfb6824e313ebecde00f134ebf9c
2023-09-08 11:28:54 -07:00
Nicholas Mosier
62e81930d6 Merge branch 'develop' into bugfix-chdir 2023-09-07 09:54:35 -07:00
studyztp
e206b16f73 sim:fixed some style issues
Change-Id: I0832a8b68e802e9671b755d3a71fd9c8f17e1648
2023-09-07 08:52:24 -07:00
studyztp
377c875733 sim: check redirect path when unserialize for cpt
sim/fd_array.hh:
Add "class Process;" to forward declare Process for unserialize
function to pass in a Process object pointer.
Fix the styling issue with include files.

sim/fd_array.cc"
Add comments.

Change-Id: Ifb21eb1c7bad119028b8fd8e610a125100fde696
2023-09-07 08:52:24 -07:00
studyztp
2a4f3f206b sim: modifed the type of path
Change-Id: I56be3b62b1804371b9b9e0f84ee1ec49cbedf553
2023-09-07 08:52:24 -07:00
studyztp
0dab27f24a sim: check redirect path when unserialize for cpt
Change-Id: I55b8ce1770b0580d52b8dfa782572d492c1bf727
2023-09-07 08:52:24 -07:00
Johnny
105839ae2b sim: add bypass_on_change to the set() of a signal
When reset a port, we don't want to trigger a onChange().
Offer an option to bypass it and update state only.

Change-Id: Ia53b7a76d2a320ea67101096cdbfe2eafaf440d2
2023-09-07 11:54:56 +08:00
Nicholas Mosier
6cdaa2c16a sim-se: Fix crash in chdirFunc() on nonexistent directory
This commit fixes a crash in the syscall emulation of the chdir(2)
syscall, implemented by chdirFunc() in src/sim/syscall_emul.cc,
when passed a nonexistent directory. The buggy code did not check
the return value of realpath().

This patch adds code to check the return value of realpath(), and
if it is NULL (i.e., there was an error with the requested directory
to change to), propagates the error in `errno` to the application.

GitHub issue: https://github.com/gem5/gem5/issues/276

Change-Id: I8a576f60fe3687f320d0cfc28e9d3a6b477d7054
2023-09-07 03:18:58 +00:00
Johnny
76fe71ebd0 sim: provide a signal constructor with an init_state
Add more description to the code

Change-Id: Iff8fb20762baa0c9d0b7e5f24fb8769d7e198b5c
2023-08-23 10:49:15 +08:00
Johnny
6acb687975 sim: provide a signal constructor with an init_state
1. The current SignalSinkPort and SignalSourcePort have no
   ways to assign the init value of the state. Add a new constructor
   for them with the param init_state
2. After the source and sink are bound, the state at both side should
   be the same. Set the the state of sink to the state of source in the
   bind() function.

Change-Id: Idde0a12aa0ddd0c9c599ef47059674fb12aa5d68
2023-08-23 10:12:41 +08:00
Gabriel Busnot
4c4419296b base: Unit tests miscellaneous patches (#73)
* base: Fix Memoizer constructor parameter type

* base: switch from new to mk_unq in amo.test.cc

* base: Fix memory management in IniFile

* base: Fix memory management in Trie

* sim: Fix out-of-bounds access in CheckpointIn::setDir

Change-Id: Iac50bbf01b6d7acc458c786da8ac371582a4ce09

---------

Co-authored-by: Gabriel Busnot <gabriel.busnot@arteris.com>
2023-07-19 08:45:29 -07:00
Luming Wang
c634b23305 sim,python: follow the new CPython startup sequence
Currently, gem5 suffers from several bugs related
to Python interpreter's locale encoding issues.
gem5 will crash when the working directory contains
Non-ASCII characters.

The reason is that Python 3.8+ introduces a new
interpreter startup sequence [1]. The startup
sequence consists of three phases:

1. Python core runtime preinitialization
2. Python core runtime initialization
3. Main interpreter configuration

Stage 1 determining the encodings used for system
interfaces.

However, gem5 doesn't preinitialize the Python
interpreter. Thus, the locale settings do not take
effect. This patch preinitialize the Python for
Python 3.8+.

Also, this patch avoid the use of `Py_SetProgramName`,
which is deprecated since Python 3.11[3].

[1] https://peps.python.org/pep-0432/
[2] https://peps.python.org/pep-0587/
[3] https://docs.python.org/3/c-api/init.html#c.Py_SetProgramName

Change-Id: I08a2ec6ab2b39a95ab194909932c8fc578c745ce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70898
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Roger Chang <rogerycchang@google.com>
2023-07-10 23:00:31 +00:00
Melissa Jost
65d077d795 base: Output link to common errors page
This change adds a link to the common errors page that outputs
whenever a fatal signal is raised, showing when the program
aborts or segfaults.

Change-Id: I88420a594423570af670b460cfce7c03c4208120
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70978
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2023-05-26 04:42:25 +00:00
Gabe Black
716c154b51 arch,base,dev,sim: Convert objects to use the HostSocket param type.
This will make it possible to connect any of these objects with a
named socket, in addition to the usual port numbers.

Change-Id: Id441c3628f62d60608a07c5cb697786e33199981
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69166
Reviewed-by: Jui-min Lee <fcrh@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
2023-04-12 02:18:22 +00:00
Gabe Black
67fb75d659 base,cpu,dev,sim: Pull common logic into ListenSocket::listen().
Create a version of listen() which handles common logic internally,
including scanning for an available port number, and notifying what
port was chosen.

The port is managed internal to ListenSocket, so that the logic
interacting with it doesn't need to manually manage a port number, and
hence a port number does not need to exist for non AF_INET sockets.

Change-Id: Ie371eccc4d0da5e7b90714508e4cb72fb0091875
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69160
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2023-03-29 03:05:06 +00:00