Giacomo Travaglini aff1ddb196 arch-arm: Implement FEAT_TLBIOS ...

This feature is mandatory in Armv8.4
We are currently not distinguishing Inner and Outer domains.
We therefore implement TLBIOS instructions as TLBIIS

Change-Id: I2198e6155f1eea7c5f8083c6ffb178d3a3d163d3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70567
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

2023-05-17 08:11:06 +00:00

..

amdgpu

arch-gcn3,arch-vega: Fix ds_read2st64_b32

2023-05-13 20:09:37 +00:00

arm

arch-arm: Implement FEAT_TLBIOS

2023-05-17 08:11:06 +00:00

generic

arch: Add a virtual method to the BaseISA to reset its ThreadContext.

2023-02-03 06:17:11 +00:00

isa_parser

misc: Use python f-strings for string formatting

2023-03-16 09:05:29 +00:00

mips

arch,base,dev,sim: Convert objects to use the HostSocket param type.

2023-04-12 02:18:22 +00:00

null

misc: Replace TARGET_ISA with USE_${ISA} variables.

2022-09-02 10:20:51 +00:00

power

arch,base,dev,sim: Convert objects to use the HostSocket param type.

2023-04-12 02:18:22 +00:00

riscv

arch-riscv: Refactor RVC decode flow when funct4==0b1001 and op==C2

2023-05-12 00:01:12 +00:00

sparc

misc: Fix 'unused variable' clang errors with gem5.fast

2023-05-08 22:54:06 +00:00

x86

arch,base,dev,sim: Convert objects to use the HostSocket param type.

2023-04-12 02:18:22 +00:00

micro_asm_test.py

misc: Use python f-strings for string formatting

2023-03-16 09:05:29 +00:00

micro_asm.py

misc: Use python f-strings for string formatting

2023-03-16 09:05:29 +00:00

SConscript

arch,cpu: Add boilerplate support for matrix registers

2023-01-17 10:09:56 +00:00

SConsopts

misc: Replace TARGET_ISA with USE_${ISA} variables.

2022-09-02 10:20:51 +00:00