Matthew Poremba 3584c3126c arch-x86: Expose CR4.osxsave bit ...

Related to the recent changes with moving CPUID values to python, this
value is needed to enable AVX and needs a way to be exposed to python as
well in order to set the bit and the corresponding CPUID values at the
same time.

Change-Id: I3cadb0fe61ff4ebf6de903018a8d8a411bfdb4e0

2023-07-28 11:34:04 -05:00

..

amdgpu

gpu-compute, tests: Fix GPU_X86 compilation, add compiler tests (#64)

2023-07-11 14:35:03 -07:00

arm

arch-arm: Hook TLBIOS instructions to the TlbiShareable obj

2023-07-24 09:05:01 +01:00

generic

arch-riscv: Fix clearLoadReservation merge (#81)

2023-07-14 08:48:43 -07:00

isa_parser

arch: Add setRegOperand in VecRegOperand

2023-07-10 22:59:12 +00:00

mips

arch,base,dev,sim: Convert objects to use the HostSocket param type.

2023-04-12 02:18:22 +00:00

null

misc: Replace TARGET_ISA with USE_${ISA} variables.

2022-09-02 10:20:51 +00:00

power

arch,base,dev,sim: Convert objects to use the HostSocket param type.

2023-04-12 02:18:22 +00:00

riscv

arch-riscv: Set default check alignment True (#98)

2023-07-19 11:14:27 -07:00

sparc

misc: Fix 'unused variable' clang errors with gem5.fast

2023-05-08 22:54:06 +00:00

x86

arch-x86: Expose CR4.osxsave bit

2023-07-28 11:34:04 -05:00

micro_asm_test.py

misc: Use python f-strings for string formatting

2023-03-16 09:05:29 +00:00

micro_asm.py

misc: Use python f-strings for string formatting

2023-03-16 09:05:29 +00:00

SConscript

arch,cpu: Add boilerplate support for matrix registers

2023-01-17 10:09:56 +00:00

SConsopts

misc: Replace TARGET_ISA with USE_${ISA} variables.

2022-09-02 10:20:51 +00:00