gpu-compute, tests: Fix GPU_X86 compilation, add compiler tests (#64)

* gpu-compute: Remove use of 'std::random_shuffle'

This was deprecated in C++14 and removed in C++17. This has been
replaced with std::random. This has been implemented to ensure
reproducible results despite (pseudo)random behavior.

Change-Id: Idd52bc997547c7f8c1be88f6130adff8a37b4116

* dev-amdgpu: Add missing 'overrides'

This causes warnings/errors in some compilers.

Change-Id: I36a3548943c030d2578c2f581c8985c12eaeb0ae

* dev: Fix Linux specific includes to be portable

This allows for compilation in non-linux systems (e.g., Mac OS).

Change-Id: Ib6c9406baf42db8caaad335ebc670c1905584ea2

* tests: Add 'VEGA_X86' build target to compiler-tests.sh

Change-Id: Icbf1d60a096b1791a4718a7edf17466f854b6ae5

* tests: Add 'GCN3_X86' build target to compiler-tests.sh

Change-Id: Ie7c9c20bb090f8688e48c8619667312196a7c123

.github/workflows/compiler-tests.yaml

@@ -35,7 +35,7 @@ jobs:
   latest-compilers-all-gem5-builds:
     strategy:
       matrix:
-        gem5-compilation: [ARM, ARM_MESI_Three_Level, ARM_MESI_Three_Level_HTM, ARM_MOESI_hammer, Garnet_standalone, GCN3_X86, MIPS, 'NULL', NULL_MESI_Two_Level, NULL_MOESI_CMP_directory, NULL_MOESI_CMP_token, NULL_MOESI_hammer, POWER, RISCV, SPARC, X86, X86_MI_example, X86_MOESI_AMD_Base]
+        gem5-compilation: [ARM, ARM_MESI_Three_Level, ARM_MESI_Three_Level_HTM, ARM_MOESI_hammer, Garnet_standalone, GCN3_X86, MIPS, 'NULL', NULL_MESI_Two_Level, NULL_MOESI_CMP_directory, NULL_MOESI_CMP_token, NULL_MOESI_hammer, POWER, RISCV, SPARC, X86, X86_MI_example, X86_MOESI_AMD_Base, VEGA_X86, GCN3_X86]
         image: [gcc-version-12, clang-version-14]
         opts: [.opt]
     runs-on: [self-hosted, linux, x64, run]

src/arch/amdgpu/vega/insts/instructions.hh

@@ -31534,8 +31534,8 @@ namespace VegaISA
         } // getOperandSize
 
         void execute(GPUDynInstPtr) override;
-        void initiateAcc(GPUDynInstPtr gpuDynInst);
-        void completeAcc(GPUDynInstPtr gpuDynInst);
+        void initiateAcc(GPUDynInstPtr gpuDynInst) override;
+        void completeAcc(GPUDynInstPtr gpuDynInst) override;
     }; // Inst_DS__DS_OR_B32
 
     class Inst_DS__DS_XOR_B32 : public Inst_DS

src/cpu/testers/gpu_ruby_test/address_manager.cc

@@ -32,6 +32,8 @@
 #include "cpu/testers/gpu_ruby_test/address_manager.hh"
 
 #include <algorithm>
+#include <climits>
+#include <random>
 
 #include "base/intmath.hh"
 #include "base/logging.hh"
@@ -58,8 +60,13 @@ AddressManager::AddressManager(int n_atomic_locs, int n_normal_locs_per_atomic)
         randAddressMap[i] = (Addr)((i + 128) << floorLog2(sizeof(Value)));
     }
 
-    // randomly shuffle randAddressMap
-    std::random_shuffle(randAddressMap.begin(), randAddressMap.end());
+    // randomly shuffle randAddressMap. The seed is determined by the random_mt
+    // gem5 rng. This allows for deterministic randomization.
+    std::shuffle(
+        randAddressMap.begin(),
+        randAddressMap.end(),
+        std::default_random_engine(random_mt.random<unsigned>(0,UINT_MAX))
+    );
 
     // initialize atomic locations
     // first and last normal location per atomic location

src/dev/hsa/kfd_ioctl.h

@@ -23,9 +23,10 @@
 #ifndef KFD_IOCTL_H_INCLUDED
 #define KFD_IOCTL_H_INCLUDED
 
+#include <sys/ioctl.h>
+#include <sys/types.h>
+
 #include <cstdint>
-#include <linux/ioctl.h>
-#include <linux/types.h>
 
 namespace gem5
 {

tests/compiler-tests.sh

@@ -58,6 +58,8 @@ builds=("ALL"
         "POWER"
         "RISCV"
         "SPARC"
+        "GCN3_X86"
+        "VEGA_X86"
         "X86"
         "X86_MI_example"
         "X86_MOESI_AMD_Base")