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312f44831f45c363bb1a97fdc601cb5efc8d5652
gem5/src/arch/arm
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Giacomo Travaglini 312f44831f arch-arm: Move MiscReg BitUnions into a separate header file 
As the number of MiscRegs increases there is the need of a cleaner
header file; this patch is separating miscreg.[cc,hh] where the miscreg
decoding/utility functions are defined/declared from the MiscReg
register types (BitUnion).

Change-Id: I815f53b117b50e47f93aa13d78356ef09d2a2541
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/13065
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01 15:47:55 +00:00
..
freebsd
arm: Remove unused DumpStatsPCEventF class in FreeBSD system
2017-05-12 09:21:41 +00:00
insts
arch-arm: AArch32 execution triggering AArch64 SW Break
2018-06-22 10:53:40 +00:00
isa
arm: Add support for RCpc load-acquire instructions (ARMv8.3)
2018-08-10 12:25:45 +00:00
kvm
dev-arm: rename Pl390 to GicV2
2018-09-12 10:27:06 +00:00
linux
sim: Remove _numContexts member in System class
2018-02-09 15:09:00 +00:00
tracers
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
ArmInterrupts.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
ArmISA.py
arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP
2018-05-29 10:17:47 +00:00
ArmNativeTrace.py
cpu: Put all CPU instruction tracers in a single file
2015-01-25 07:22:17 -05:00
ArmPMU.py
arm: Use the interrupt adaptor in the PMU
2018-09-10 09:57:26 +00:00
ArmSemihosting.py
arch-arm: Add support for semihosting STDIO redirection
2018-05-16 17:20:27 +00:00
ArmSystem.py
arch-arm: Add aarch64 semihosting support
2018-02-19 14:24:46 +00:00
ArmTLB.py
arm, power: Make the python TLB simobjects inherit from BaseTLB.
2018-01-11 09:34:23 +00:00
ccregs.hh
arm: use condition code registers for ARM ISA
2014-04-29 16:05:02 -05:00
decoder.cc
arch-arm: Add Illegal Execution flag to PCState
2018-06-14 13:45:49 +00:00
decoder.hh
isa: Add parameter to pick different decoder inside ISA
2015-10-09 14:50:54 -05:00
faults.cc
arch-arm: AArch32 execution triggering AArch64 SW Break
2018-06-22 10:53:40 +00:00
faults.hh
arch-arm: Adjust breakpoint EC depending on source state
2018-06-06 13:52:39 +00:00
interrupts.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
interrupts.hh
arm: Fix secure state checking in various places
2016-08-02 10:38:02 +01:00
intregs.hh
arm: ISA X31 destination register fix
2014-09-03 07:42:43 -04:00
isa_device.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
isa_device.hh
arm: Add support for tracking TCs in ISA devices
2018-09-10 09:57:26 +00:00
isa_traits.hh
alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.
2018-01-10 12:19:54 +00:00
isa.cc
arch-arm: Init AArch64 ID registers in SE mode
2018-10-01 15:47:55 +00:00
isa.hh
arch-arm: Init AArch64 ID registers in SE mode
2018-10-01 15:47:55 +00:00
kernel_stats.hh
stats: Get rid of some kernel stats related cruft.
2017-09-11 04:58:38 +00:00
locked_mem.hh
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
microcode_rom.hh
arm: include missing file for arm
2009-04-21 15:40:26 -07:00
miscregs_types.hh
arch-arm: Move MiscReg BitUnions into a separate header file
2018-10-01 15:47:55 +00:00
miscregs.cc
arch-arm: Introduce ARMv8.1 Virtual Timer System Registers
2018-07-16 08:18:56 +00:00
miscregs.hh
arch-arm: Move MiscReg BitUnions into a separate header file
2018-10-01 15:47:55 +00:00
mmapped_ipr.hh
arch: Add support for m5ops using mmapped IPRs
2013-09-30 12:20:43 +02:00
nativetrace.cc
cpu: Added interface for vector reg file
2017-07-05 14:43:49 +00:00
nativetrace.hh
ARM: Add vfpv3 support to native trace.
2011-05-04 20:38:26 -05:00
pagetable.hh
arm: Mark uninitialized new TLB entries as not valid
2016-06-20 15:51:31 +01:00
pmu.cc
arch-arm: raise/clear IRQ when writing to PMOVSCLR/SET
2018-09-28 10:13:05 +00:00
pmu.hh
arch-arm: raise/clear IRQ when writing to PMOVSCLR/SET
2018-09-28 10:13:05 +00:00
process.cc
syscall_emul: expand AuxVector class
2018-09-19 20:51:17 +00:00
process.hh
arch,mem: Move page table construction into the arch classes.
2018-01-11 06:29:58 +00:00
pseudo_inst.hh
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
registers.hh
cpu: Added interface for vector reg file
2017-07-05 14:43:49 +00:00
remote_gdb.cc
arch, mem: Make the page table lookup function return a pointer.
2018-01-20 08:06:56 +00:00
remote_gdb.hh
sim, arch, base: Refactor the base remote GDB class.
2018-01-20 07:28:42 +00:00
SConscript
arch-arm: Fix AArch32 branch instructions disassemble
2018-04-06 09:58:41 +00:00
SConsopts
arm: add ARM support to M5
2009-04-05 18:53:15 -07:00
semihosting.cc
arch-arm: Fix semihosting arg count for SYS_GET_CMDLINE
2018-05-16 17:20:27 +00:00
semihosting.hh
arch-arm: Add support for semihosting STDIO redirection
2018-05-16 17:20:27 +00:00
stacktrace.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
stacktrace.hh
arch: Use const StaticInstPtr references where possible
2014-09-27 09:08:36 -04:00
stage2_lookup.cc
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
stage2_lookup.hh
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
stage2_mmu.cc
arch-arm: Fix missing Request allocation
2018-06-13 09:30:17 +00:00
stage2_mmu.hh
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
system.cc
arch-arm: Semihosting not available in syscall emulation
2018-02-19 16:12:25 +00:00
system.hh
arch-arm: Add aarch64 semihosting support
2018-02-19 14:24:46 +00:00
table_walker.cc
arch-arm: Correction for address size in EL1&0 translation
2018-09-13 09:08:19 +00:00
table_walker.hh
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
tlb.cc
arch-arm: Add Illegal Execution flag to PCState
2018-06-14 13:45:49 +00:00
tlb.hh
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
tlbi_op.cc
arch-arm: Distinguish IS TLBI from non-IS
2018-03-23 10:24:24 +00:00
tlbi_op.hh
arch-arm: Distinguish IS TLBI from non-IS
2018-03-23 10:24:24 +00:00
types.hh
arch-arm: BadMode checking if corresponding EL is implemented
2018-06-22 10:52:55 +00:00
utility.cc
arch-arm: BadMode checking if corresponding EL is implemented
2018-06-22 10:52:55 +00:00
utility.hh
arch-arm: BadMode checking if corresponding EL is implemented
2018-06-22 10:52:55 +00:00
vtophys.cc
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
vtophys.hh
gcc: Clean-up of non-C++0x compliant code, first steps
2012-03-19 06:36:09 -04:00